版图寄生效应

• Need accurate model of y-parameters of unit cell
– Used 120µmwide device – Trouble accurately fitting y-parameters using traditional small signal model – Instead used measured y-parameters from 120µm device
→ Degradation of large device performance!
SSC San Diego
HIGH SPEED DEVICE GROUP
SOS Technology
Device gg(µm) Device L L (µm) NMOS 0.5 NMOS 0.5 PMOS 0.5 PMOS 0.5 ft (GHz) F (dB) Ga (dB) max MIN ft(GHz) (GHz) ff F max (GHz) MIN (dB) G a (dB) 25 66 0.9 21 25 66 0.9 21 14 41 0.9 13 14 41 0.9 13
High S peed High Power
Lower Sp eed
• Microwave gain drops
– Technology to increase breakdown – Use of many fingers in parallel
SSC San Diego
HIGH SPEED DEVICE GROUP
SSC San Diego
Model Verification (Wg=432µm)
0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 0 5 10
Frequency (GHz) Model: Model: Meas: Meas: Real Y11 Imaginary Y11 Real Y11 Imaginary Y11
Model: Model: Meas: Meas:
Real Y21 Imaginary Y21 Real Y21 Imaginary Y11
0.02 0.01 0.01 0.00 0 5 10 Frequency (GHz) 15 20
SSC San Diego
HIGH SPEED DEVICE GROUP
Real Y12 Imaginary Y12 Real Y12 Imaginary Y12
0.20
0.00 -0.05
0.00
-0.10 -0.15 -0.20
-0.20
-0.40 0 5 10 Frequency (GHz) 15 20
SSC San Diego
HIGH SPEED DEVICE GROUP
f max (GHz)
f t (GHz)
Transmission Line Model
• Elements are distributed • Usually used to model gate finger • Small signal model used for unit gate finger
Large FET RF Performance
20 18 16 14 12 10 8 6 4 2 0 0 1000 2000 3000 4000 5000 Gate Width ( µm)
45 40 35 30 25 20 15 10 5 0 0 1000 2000 3000 4000 Gate Width (µ m) 5000
in So ur Dr a ce
Rg Cgs Ri Cgd Rd
g m e jτ
Cds
Rout
Rs
SSC San Diego
HIGH SPEED DEVICE GROUP
Problem Setup
Id Ig Is Gate Source
vg ′( x) = − Zg ⋅ ig ( x) + jω ⋅ [ Mgd ⋅ id ( x) − Mgs ⋅ is ( x)] vd ′( x) = Zd ⋅ id ( x) + jω ⋅ [− Mgd ⋅ ig ( x) − Mds ⋅ is ( x)] vs ′( x) = − Zs ⋅ is ( x) + jω ⋅ [ Mds ⋅ id ( x) − Mgs ⋅ ig ( x)]
Outline
• Introduction • Large FET Performance • Transmission Line Model • Verify Model • Summary
SSC San Diego
HIGH SPEED DEVICE GROUP
Device Scaling
gm ft = 2πCin
Model Verification (Wg=1296µm)
0.80
0.25
0.60
Model: Model: Meas: Meas:
Real Y11 Imaginary Y11 Real Y11 Imaginary Y11
0.20 0.15 0.10 0.05
0.40
Model: Model: Meas: Meas:
• Need many fingers connected in parallel
– Interconnects introduce extra resistance, capacitance, and delay → ft and fmax decrease with width
Drain Gate
vgs ′′( x) = α ⋅ vgs ( x) + β ⋅ vds( x) vds ′′( x) = δ ⋅ vgs( x) + γ ⋅ vds( x)
Drain
• Derive expressions for change in voltage and current along the lines
2160µm
Gate
• Simple devices design so that analytical solution would be good representation • Drain/Gate/Source bus lines straight transmission lines
HIGH SPEED DEVICE GROUP
Rg Cgs Ri Cgd Rd
g m e jτω
Cds
Rout
g d e jτ 2ω
Rs
SSC San Diego
HIGH SPEED DEVICE GROUP
Experiment
Drain x1 x3 x5
Drain
Drain Drain
Source Gate
Gate
432µm
Gate
1296µm
– Ig(0)=Ig, – Id(0)=0, Ig(L)=0 Id(L)=Id
– Vgs(0)=Vgs Vds(0)=Vds
jω 2 2 − α − jω M β − M β + M 2 2 r+ gd ds gs r+ −α Z g r− −α − Z M gd β + M ds β − M gs r− −α Zg g − Z11 = 2 −r 2 r+ Tanh( r+ L ) r− Tanh( r− L ) r− + Z gδ 2 2 r− − r+
Layout Parasitic Effects on Microwave Characteristics of Large Periphery Transistors
M. Wetzel, P. R. de la Houssaye*, P.M. Asbeck, I. Lagnado*
Department of Electrical and Computer Engineering, UCSD * Space and Naval Warfare Systems Center, San Diego
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• Currents used in solution of Vgs(x) and Vds(x) • Z-parameters
– Z dij
= Vi Ij
Z 21 =
jω M gd β − M ds β jω M gd β − M gsδ + M gs 1− + M gs 1− Z 2 −α 2 −α Zg g r+ r− − r− Sinh( r− L ) r+ Sinh( r + L )
Inductance (nH), Quality Factor
25
• Leff=0.35µm, Si thickness=1000Å, metal T-gate • Interconnect modeling can be applied to any technology
Aluminum T-Gate Al TiSi2 SiO2 Al TiSi2
f max ft = 2 2πf t Rg C gd + G o [Rg + Rs ]
Source • Parameter scaling – Conductances and capacitances scale linearly with width – Resistances scale inversely with width → ft and fmax ideally do not change with width
0.05 0.05 0.04 0.04 0.03 0.03