Lab1_体系结构实验报告

2012年3月1日一、实验目的和要求1.understand the principles of ALU and master methods of ALU design2.understand the principles of ALU controller and master methods of ALUcontroller design3.understand the principles of register file and master methods of register filedesignso the task isfirst, design a ALU with ALU controllerthen, design a register file二、实验内容和原理2.1 ALU with ALU controllerWe input the operand r, s; both are 32 bit integer, and aluc is the control code that defines the operation.So we just make the code block, totally as ALU block, ALUC block, display block.Figure 1 the input and output diagramFigure 2 ALU operationsFigure 3 the truth table of operation cod eFigure 4 principle of ALU2.2 register fileThe process is similar to the 2.1, when we get the principle of register file , it can be easily coding.Figure 5 the input and outputFigure 6 The Circuit Integrating ALU三、实验过程和数据记录1.ALU and ALU ControllerHere is the code:Top block:module ALUC(input CCLK, input [1:0]BTN, input [3:0] SW, output LCDRS, LCDRW, LCDE, output [3:0] LCDDAT,output LED);wire [3:0] lcdd;wire rslcd, rwlcd, elcd;wire o_zf;wire [31:0] o_alu;wire [2:0] i_aluc;wire [1:0] alu_op;wire [3:0] func;reg [31:0] o_alu_old;reg [255:0] strdata;reg [31:0] i_r;reg [31:0] i_s;reg rst;assign LCDDAT[3] = lcdd[3];assign LCDDAT[2] = lcdd[2];assign LCDDAT[1] = lcdd[1];assign LCDDAT[0] = lcdd[0];assign LCDRS = rslcd;assign LCDRW = rwlcd;assign LCDE = elcd;assign LED = o_zf;assign func[0] = SW[0];assign func[1] = SW[1];assign func[2] = SW[2];assign func[3] = SW[3];assign alu_op[0] = BTN[0];assign alu_op[1] = BTN[1];initial beginstrdata = "1111 2222 ";i_r = 32'h1111;i_s = 32'h2222;rst = 0;o_alu_old = 0;enddisplay M0 (CCLK, rst, strdata, rslcd, rwlcd, elcd, lcdd); single_alu M1(i_r, i_s, i_aluc, o_zf, o_alu);single_aluc M2(alu_op, func, i_aluc);always @(posedge CCLK) beginif (o_alu_old != o_alu) beginstrdata[127:120] = 8'h30 + o_alu[15:12];strdata[119:112] = 8'h30 + o_alu[11:8];strdata[111:104] = 8'h30 + o_alu[7:4];strdata[103:96] = 8'h30 + o_alu[3:0];o_alu_old = o_alu;endelserst = 0;endendmoduledisplay:module display(input CCLK, reset,input [255:0]strdata, output rslcd, rwlcd, elcd,output [3:0] lcdd);wire [7:0] lcddatin;lcd M0 (CCLK, resetlcd, clearlcd, homelcd, datalcd, addrlcd,lcdreset, lcdclear, lcdhome, lcddata, lcdaddr,rslcd, rwlcd, elcd, lcdd, lcddatin, initlcd);genlcd M1 (CCLK, reset, strdata, resetlcd, clearlcd, homelcd, datalcd,addrlcd, initlcd, lcdreset, lcdclear, lcdhome,lcddata, lcdaddr, lcddatin); endmodulemodule genlcd(input CCLK, debpb0, input [255:0]strdata, output reg resetlcd,output reg clearlcd, output reg homelcd,output reg datalcd, output reg addrlcd,output reg initlcd, input lcdreset, lcdclear,input lcdhome, lcddata, lcdaddr,output reg [7:0] lcddatin);reg [3:0] gstate; // state register integer i;always@(posedge CCLK)beginif (debpb0==1)beginresetlcd=0;clearlcd=0;homelcd=0;datalcd=0;gstate=0;endelsecase (gstate)0: begininitlcd=1;gstate=1;end1: begininitlcd=0;gstate=2;end2: beginresetlcd=1;if (lcdreset==1)beginresetlcd=0;gstate=3;endend3: begininitlcd=1;gstate=4;end4: begininitlcd=0;gstate=5;end5: beginclearlcd=1;if (lcdclear==1)beginclearlcd=0;gstate=6;endend6: begininitlcd=1;gstate=7;end7: begininitlcd=0;i=255;gstate=8;end8: beginif(i>127)lcddatin[7:0]=8'b0000_0000;elselcddatin[7:0]=8'b0100_0000;addrlcd=1;if (lcdaddr==1)beginaddrlcd=0;gstate=9;endend9: begininitlcd=1;gstate=10;end10: begininitlcd=0;gstate=11;end11: beginlcddatin[7:0]=strdata[i-:8];datalcd=1;if (lcddata==1)begindatalcd=0;gstate=12;endend12: begininitlcd=1;gstate=13;end13: begininitlcd=0;gstate=14;end14: begini=i-8;if (i<0)gstate=15;else if (i==127)gstate=8;elsegstate=11;end15: gstate=15;default: gstate=15;endcaseendendmodulemodule single_alu(i_r,i_s,i_aluc,o_zf,o_alu);input [31:0] i_r; //i_r: r inputinput [31:0] i_s; //i_s: s inputinput [2:0] i_aluc; //i_aluc: ctrl inputoutput o_zf; //o_zf: zero flag outputoutput [31:0] o_alu; //o_alu: alu result outputreg o_zf;reg [31:0] o_alu;always @(i_aluc or i_r or i_s) begincase (i_aluc)3'b010:o_alu=i_r+i_s;3'b110:o_alu=i_r-i_s;3'b000:o_alu=i_r&i_s;3'b001:o_alu=i_r|i_s;3'b111:o_alu=i_r<i_s?1:0;/////////////////////////////////////////在此添加根据i_aluc的值对o_alu和o_zf进行赋值endcaseif(o_alu==0)o_zf=1;elseo_zf=0;endendmodulemodule single_aluc(aluop, func, aluc);input [1:0] aluop;input [5:0] func;output [2:0] aluc;reg [2:0] aluc;always @(aluop or func) begincase (aluop)2'b00:aluc=3'b010;2'b01:aluc=3'b110;default:begincase (func[3:0])4'b0000:aluc=3'b010;4'b0010:aluc=3'b110;4'b0100:aluc=3'b000;4'b0101:aluc=3'b001;4'b1010:aluc=3'b111;endcaseend//根据aluop和func的不同值，对aluc进行赋值。