A Low Jitter 125-1250MHz Process Independent

25.2 A Low Jitter 125-1250MHz Process Independent0.18µm CMOS PLL Based on a Sample-ResetLoop FilterAdr an Max m, Baker Scott, Ed Schne der, Melv n Hagge, Steve Chacko, Dan StiurcaCrystal - Cirrus Logic Inc. Austin TXIn mixed analog-digital VLSI ICs, the on-chip PLLs operate in a noisy environment with the most noise contributed by the supply and sub-strate. The low-jitter requirements of these PLLs impose high loop bandwidths, which in standard charge-pump architectures necessi-tate a tradeoff in frequency resolution [1, 2]. This low-jitter high-res-olution ripple-pole-less process-independent 0.18µm CMOS PLL is based on a sample-reset loop filter technique. The key feature of this architecture is elimination of phase detector frequency spurs due to the ICO control current spikes during input phase difference. This is accomplished by averaging the charge injected by the proportional path over an entire input update period. As a consequence, the ICO control current has a shape characterized by a staircase of low ampli-tude steps, versus one characterized by narrow high amplitude puls-es, and needs much less filtering for low-jitter operation.Figure 25.2.1 presents the block diagram of the proposed current-mode process-independent PLL. To reduce the jitter due to power sup-ply noise, the analog and digital portions of the PLL are biased off of two different on-chip 1.5V sub-regulators. A low-jitter PLL synthesiz-er requires high bandwidth (B), and therefore a high input-update fre-quency (fupdate >10*B). A simple high-bandwidth low-resolution sample-reset PLL at the input boosts the reference frequency to approximately 1.3GH z for the input divider of the high-resolution, high-bandwidth PLL. The bandwidth of the high-resolution PLL is equal to or less than the bandwidth of the input PLL, to minimize phase noise contributed by the internal oscillator of the input PLL. The phase frequency detector is a standard 7 NAND gate design with dead-zone avoidance [1, 2]. The charge pump uses source switches to minimize clock feedthrough from the noisy digital supply. The inte-gral path of the loop filter consists of a main charge-pump (Ipmp) that integrates the input phase difference on the Cint capacitance for use by the transconductance stage (Mint), which converts this voltage into a current. The proportional path samples the phase difference for each update period on a Czero capacitance by integrating the current from the feed-forward charge-pump (Ipmpz). This voltage is used to provide a constant current during the entire update period, through a process independent gm stage. To avoid introducing an additional pole in the loop due to the integration on Czero, the voltage on it is reset at the end of each update period. The wide frequency range is achieved with a differential ring oscillator [2], controlled by current, to minimize the coupled noise. The M feedback programmable divider uses a dual modulus architecture with a divide by 2 prescaler and a pulse swallower counter. The output of the divider is resynchronized with the ICO clock to minimize the jitter contribution of the divider.A bandgap circuit provides the PLL with two types of bias currents: a temperature and process independent current (Iti) which is digitally calibrated to an external resistor, and a current (Ibg) proportional to the bandgap voltage (Vbg), divided by an internal reference resistance (Rbg). This gives a process independent mechanism to transfer ratios of the bandgap voltage around the IC (V=a*Ibg* Rbg).Figure 25.2.2 presents the simplified schematic of the current-mode loop filter. A process-independent reference transconductance is gen-erated by a differential pair (Mrgm+, Mrgm-) that is tuned to a con-stant gm by a feedback circuit that regulates its tail current. The input of the gm tune loop differential pair is a process independent bandgap voltage, Vbg. An offset current derived from the Iti current is summed into the drains of the differential pair. The resulting transconductance (gm = 1/Rgm ∝Iti/Vbg) is virtually process inde-pendent. The tail current of the reference gm stage is mirrored into several replica gm stages. By controlling the addition of their output currents, a process-independent programmable gm stage is achieved. This gm is used in conjunction with Czero to form the programmable stabilizing zero for the loop. The resulting stabilizing zero (ωz) is set by the ratio of charge-pump currents, times a ratio of resistances and a ratio of capacitances. It has a low process dependence due to Rint and tracks the natural frequency (ωn):where Kico ∝Ibg*Rbg/Ctotal is the ring oscillator gain, and Ctotal is the total capacitance charged and discharged in the ring element. The resulting damping factor (ξ) is virtually process independent, provid-ed that both Ipmp and Ipmpz are of Ibg type, so that Ipmp*Rint is process independent:To keep the variation of the damping factor less than ±30% over the entire output frequency range, the Cint capacitance is programmed in accordance with the PLL feedback divider value (M) and gm*Czero is programmed with reference to the phase detector update frequency. The sampling capacitance (Czero) is realized by two sets of differen-tial capacitors (Czp_even/odd and Czn_even/odd), which are charged in opposite directions by the Ipmpzp/Ipmpzn proportional path charge-pumps. During even update periods the first set is reset and then samples the phase difference, and during odd update periods it is connected to the programmable gm stage to generate the feed-for-ward current. The second set of capacitances operates in complemen-tary fashion.Figure 25.2.3 presents the top level schematic of the current con-trolled, four ring element oscillator. It uses an active load differential inverter [2], which produces a smaller process dispersion in the Kico gain versus other differential inverters. By matching the devices Mrefp/Mrefn and Mlimitp/Mlimitn, the amplitude of oscillation can be made a multiple of the Vbg. This process and supply-voltage-inde-pendent swing further reduce the dispersion of the gain and improve the PSRR. To achieve a wide frequency range with linear control, the ICO current range should be minimized. Therefore the gain of the oscillator is decreased at low output frequencies by connecting addi-tional capacitances (Cgain) at the differential output of the ring ele-ments. The update frequency ripple of the control current due to the dead-zone avoidance pulses is filtered-out by the loop. The high-fre-quency pole seen at the ring element input (gm(Min)/Cpole_intern) eliminates the need for an additional on-chip ripple filtering capaci-tance. The PLL exhibits low-jitter operation with pole-zero separation ωp/ωz=150-300, which increases the phase margin towards 90°, simi-lar to type II second-order PLLs.Figure 25.2.4 presents the differential to single-ended converter that consists of a wide-band diode-load differential input stage followed by a shunt feedback differential pair that performs the conversion. By including an inverter in the shunt feedback of the differential pair that matches the output inverter, the trip point of the differential to single ended converter behaves well over process and temperature, giving a precise 50±0.5% duty-cycle output signal.Figure 25.2.5 presents the PLL transient locking waveforms. The top plot shows the integral and proportional path currents, together with the total ICO control current, while the bottom plot displays the dif-ferential voltage at the input of the process independent gm stage. Figure 25.2.6 shows the process and temperature variation of the ICO frequency-versus-current curves. Gain variation of the oscillator is only ±9% over the worst-case process and temperature corners. The main PLL specifications are: frequency range 125-1250MHz, resolu-tion better than 500kHz, supply voltage 2.5V analog/1.5V digital, jit-ter <0.3%Tosc, and power consumption 75mW.References:[1] J. Maneatis, “Low jitter process independent DLL and PLL based on self-biased techniques”, IEEE JSCC, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [2] D. Mijuskovic, e. a., “Cell based fully integrated CMOS frequency synthesizer”, IEEE JSSC, vol. 29, no. 3, pp. 271-279, March 1994.Figure 25.2.5: Transient locking waveforms.Figure 25.2.6: ICO frequency-versus-current curves.Figure 25.2.2: Current-mode sample-reset loop filter.Figure 25.2.3: ICO with process independent output amplitude.。