TPS73601QDBVRQ1, 规格书,Datasheet 资料

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FEATURES
Qualified for Automotive Applications Stable with No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range of 1.7V to 5.5V Ultra-Low Dropout Voltage: 75mV typ Excellent Load Transient Response—with or without Optional Output Capacitor New NMOS Topology Delivers Low Reverse Leakage Current Low Noise: 30mVRMS typ (10Hz to 100kHz) 0.5% Initial Accuracy 1% Overall Accuracy Over Line, Load, and Temperature Less Than 1mA max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.20V to 3.3V – Adjustable Output from 1.20V to 5.5V
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
SLVSAI3 – SEPTEMBER 2010
Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection
Check for Samples: TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
SLVSAI3 – SEPTEMBER 2010
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA OUTPUT VOLTAGE adjustable –40°C to 125°C 2.5 V 3.3 V (1) (2) (3) SOT (SOT-23) – DBV Reel of 3000 PACKAGE (2) ORDERABLE PART NUMBER TPS73601QDBVRQ1 TPS73625QDBVRQ1
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Typical Application Circuit for Fixed-Voltage Versions
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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°C/W
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For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. Thermal data for the DBV package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) DBV: There is no exposed pad with the DBV package. (b) DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.