中星微Mobile Multimedia Processor-988-2007-9-30
金士顿e MMC 5.1嵌入式多媒体卡（e
Embedded Multi-Media Card(e•MMC™ 5.1)EMMC16G-IB29-PE90EMMC32G-IB29-PE90EMMC64G-IB29-PE90v1.0Product Features•Packaged managed NAND flash memory with e•MMC™ 5.1 interface•Backward compatible with all prior e•MMC™ specification revisions•153-ball JEDEC FBGA RoHS Compliant package•Operating voltage range:o VCCQ = 1.8 V/3.3 Vo VCC = 3.3 V•Operating Temperature (T case) - 40C to +85C•Storage Temperature -55C to +85C•Compliant with e•MMC™ 5.1 JEDEC Standard Number JESD84-B51•Factory configured with pseudo Single Level Cell (pSLC) mode for enhanced reliability and performance•Factory configured with reliable writee•MMC™ Specific Feature Support•High-speed e•MMC™ protocol•Variable clock frequencies of 0-200MHz•Ten-wire bus interface (clock, 1 bit command, 8 bit data bus) with an optional hardware reset •Supports three different data bus widths: 1 bit(default), 4 bits, 8 bits•Bus Modes:o Single data transfer rate: up to 52MB/s (using 8 parallel data lines at 52MHz)o Dual data rate mode (DDR-104) : up to 104MB/s @ 52MHzo High speed, single data rate mode (HS-200) : up to 200MB/s @ 200MHzo High speed, dual data rate mode (HS-400) : up to 400MB/s @ 200MHz•Supports alternate boot operation mode to provide a simple boot sequence methodo Supports SLEEP/AWAKE (CMD5)o Host initiated explicit sleep mode for power saving•Enhanced write protection with permanent and partial protection options•Multiple user data partition with enhanced attribute for increased reliability•Error free memory accesso Cyclic Redundancy Code (CRC) for reliable command and data communicationo Internal error correction code (ECC) for improved data storage integrityo Internal enhanced data management algorithmo Data protection for sudden power failure during program operations•Securityo Secure bad block erase commandso Enhanced write protection with permanent and partial protection options•Power off notification for sleep•Field firmware update (FFU)•Production state awareness•Device health report•Command queuing•Enhanced strobe•Cache flushing report•Cache barrier•Background operation control & High Priority Interrupt (HPI)•RPMB throughput improvement•Secure write protection•Pre EOL information•Optimal sizeProduct DescriptionKingston’s e•MMC™ products conform to the JEDEC e•MMC™ 5.1standard. These devices are an ideal universal storage solution for many commercial and industrial applications. In a single integrated packaged device, e•MMC™ combines triple-level cell (TLC) NAND flash memory with an onboard e•MMC™ controller, providing an industry standard interface to the host system. The integrated e•MMC™ controller directly manages NAND flash media which relieves the host processor of these tasks, including flash media error control, wear-leveling, NAND flash management and performance optimization. Future revision to the JEDEC e•MMC™ standard will always maintain backward compatibility. The industry standard interface to the host processor ensures compatibility across future NAND flash generations as well, easing product sustainment throughout the product life cycle. ConfigurationsKingston’s e•MMC™ products support a variety of configurations that allow the e•MMC™ device to be tailored to your specific application needs. The most popular configurations described below are each offered under standard part numbers.Standard TLC – By default the e•MMC™ device is configured with the NAND flash in a standard TLC mode. This configuration provides reasonable performance and reliability for many applications. Pseudo Single Level Cell (pSLC) – The TLC NAND flash in the Kingston e•MMC™ device can be configured to further improve device endurance, data retention, reliability and performance over the standard TLC configuration. This is done by converting the NAND TLC cells to a pseudo single level cell (SLC) configuration. In this configuration, along with the performance and reliability gains, the device capacity is reduced by 2/3 of the capacity. This one-time configuration is achieved by setting the e•MMC™ enhanced attribute for the hardware partition.Kingston e•MMC™ can be ordered preconfigured with the option of reliable write or pSLC at no additional cost. Standard TLC devices can also be one-time configured in-field by following the procedures outlined in the JEDEC e•MMC™ specification. The JEDEC e•MMC™ specification allows for many additional configurations such as up to 4 additional general purpose (GPn) hardware partitions each with the option to support pSLC and reliable write. Additionally, Kingston provides a content loading service that can streamline your product assembly while reducing production costs. For more information, contact your Kingston representative.Kingston e•MMC™ devices are fully compliant with the JEDEC Standard Specification No. JESD84-B51. This datasheet provides technical specifications for Kingston’s family of e•MMC™ devices. Refer to the JEDEC e•MMC™ standard for specific information related to e•MMC™ device function and operation. See: /sites/default/files/docs/JESD84-B51.pdfe•MMC™ Mode and ControllerTLC mode using PS8229 - Leading edge 3D NAND flash technology in TLC mode rated to 3,000 endurance cycles.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.pSLC mode using PS8229 - Leading edge 3D NAND flash technology in pSLC mode.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.Part NumberingFigure 1 – Part Number FormatEMMC 16G - xxxx - PE90A B C DPart Number FieldsA: Product Family : EMMCB: Device Capacity : Available capacities of 16GB – 64GBC: Hardware Revision and ConfigurationD: Device Firmware Revision and ConfigurationTable 1 - Device SummaryDevice PerformanceTable 2 below provides sequential read and write speeds for all capacities. Performance numbers can vary under different operating conditions. Values are given at HS400 bus mode. Contact your Kingston Representative for performance numbers using other bus modes.Power ConsumptionDevice current consumption for various device configurations is defined in the power class fields of the EXT_CSD register. Power consumption values are summarized in Table 3 below.Device and Partition CapacityThe device NAND flash capacity is divided across two boot partitions (2048 KB each), a Replay Protected Memory Block (RPMB) partition (512 KB), and the main user storage area. Four additional general purpose storage partitions can be created from the user partition. These partitions can be factory preconfigured or configured in-field by following the procedure outlined in section 6.2 of the JEDEC e•MMC™ specification JESD84-B51. A small portion of the NAND storage capacity is used for the storage of the onboard controller firmware and mapping tables. Additionally, several NAND blocks are held in reserve to boost performance and extend the life of the e•MMC™ device. Table 4 identifies the specific capacity of each partition. This information is reported in the device EXT_CSD register. The contents of this register are also listed in the Appendix.e•MMC™ Bus ModesKingston e•MMC™ devices support all bus modes defined in the JEDEC e•MMC™ 5.1 specification. These modes are summarized in Table 6 below.Signal DescriptionTable 7 - e•MMC™ Signals Name Type DescriptionCLK I Clock: Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.DAT[7:0] I/O/PP Data: These are bidirectional data channels. The DAT signals operate in push-pull mode. These bidirectional signals are driven by either the e•MMC™ device or the host controller. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the e•MMC™ host controller. The e•MMC™ device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode, the device disconnects the internal pull-ups of lines DAT1–DAT7.CMD I/O/PP/OD Command: This signal is a bidirectional command channel used for device initialization and transfer of commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands are sent from the e•MMC™ host controller to the e•MMC™ device and responses are sent from the device to the host.DS O This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for positive edge and the other bit for negative edge. For CRC status response output and CMD response output (enabled only HS400 enhanced strobe mode), the CRC status and CMD Response are latched on the positive edge only, and don't care on the negative edge.RST_n I Hardware Reset: By default, hardware reset is disabled and must be enabled in the EXT_CSD register if used. Otherwise, it can be left un-connected.RFU - Reserved for future use: These pins are not internally connected. Leave floatingNC - Not Connected: These pins are not internally connected. Signals can be routed through these balls to ease printed circuit board design. See Kingston’s Design Guidelines for further details.VSF - Vendor Specific Function: These pins are not internally connectedVddi - Internal Voltage Node: Note that this is not a power supply input. This pin provides access to the output of an internal voltage regulator to allow for the connection of an external Creg capacitor. See Kingston’s Design Guidelines for further details.Vcc S Supply voltage for core Vccq S Supply voltage for I/ODesign GuidelinesDesign guidelines are outlined in a separate document. Contact your Kingston Representative for more information.Package DimensionsFigure 2 – Package DimensionsFigure 3 – Ball Pattern DimensionsBall Assignment (153 ball)Table 8 – Ball Assignment, Top View (HS400)1 2 3 4 5 6 7 8 9 10 11 12 13 14A NC NC DAT0 DAT1 DAT2 Vss RFU NC NC NC NC NC NC NC AB NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC BC NC Vddi NC Vssq NC Vccq NC NC NC NC NC NC NC NC CD NC NC NC NC NC NC NC DE NC NC NC RFU Vcc Vss VSF VSF VSF NC NC NC EF NC NC NC Vcc VSF NC NC NC FG NC NC RFU Vss VSF NC NC NC GH NC NC NC DS Vss NC NC NC H J NC NC NC Vss Vcc NC NC NC J K NC NC NC RST_n RFU RFU Vss Vcc VSF NC NC NC K L NC NC NC NC NC NC L M NC NC NC Vccq CMD CLK NC NC NC NC NC NC NC NC M N NC Vssq NC Vccq Vssq NC NC NC NC NC NC NC NC NC N P NC NC Vccq Vssq Vccq Vssq RFU NC NC RFU NC NC NC NC P1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: VSF, RFU and NC balls are not electrically connected. RFU balls may be defined with functionality by the Joint Electron Device Engineering Council (JEDEC) in future revisions of the e•MMC™ standard. Please refer to Kingston’s design guidelines for more info.Device MarkingFigure 4 - EMMC Package Marking240xxxx-xxx.xxxxYYWW PPPPPPPPxxxxxxx-xxxx2xxxxxxTAIWANKingston Logo240xxxx-xxx.xxxx：Internal control numberYYWW：Date code (YY– Last 2 digits ofyear, WW- Work week)PPPPPPPP： Internal control numberxxxxxxx-xxxx Sales P/N2xxxxxx : Internal control numberCountry：TAIWANCard Identification Register (CID)The Card Identification (CID) register is a 128-bit register that contains device identification information used during the e•MMC™ protocol device identification phase. Refer to JEDEC Standard Specification No.JESD84-B51 for details.Field Byte ValueMID [127:120] 0x70reserved [119:114] 0x00CBX [113:112] 0x01OID [111:104] 0x00PNM [103:56 ] IB2916(16G) IB2932(32G) IB2964(64G)PRV [ 55:48 ] 0x90PSN [ 47:16 ] RandomMDT [ 15:8 ] month, yearCRC [ 7:1 ] Follows JEDEC Standard reserved [ 0:0 ] 0x01Card Specific Data Register [CSD]The Card-Specific Data (CSD) register provides information on how to access the contents stored in e•MMC™. The CSD registers are used to define the error correction type, maximum data access time, data transfer speed, data format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueCSD_Structure [127:126] 0x03 (V2.0)SPEC_VER [125:122] 0x04 (V4.0~4.2)reserved [121:120] 0x00TAAC [119:112] 0x4F (40ms)NSAC [111:104] 0x01TRAN_SPEED [103:96 ] 0x32 (26Mbit/s)CCC [ 95:84 ] 0x0F5READ_BL_LEN [ 83:80 ] 0x09 (512 Bytes)READ_BL_PARTIAL [ 79:79 ] 0x00WRITE_BLK_MISALIGN [ 78:78 ] 0x00READ_BLK_MISALIGN [ 77:77 ] 0x00DSR_IMP [ 76:76 ] 0x00reserved [ 75:74 ] 0x00C_SIZE [ 73:62 ] 0xFFFVDD_R_CURR_MIN [ 61:59 ] 0x07 (100mA)VDD_R_CURR_MAX [ 58:56 ] 0x07 (200mA)VDD_W_CURR_MIN [ 55:53 ] 0x07 (100mA)VDD_W_CURR_MAX [ 52:50 ] 0x07 (200mA)C_SIZE_MULT [ 49:47 ] 0x07 (512 Bytes)ERASE_GRP_SIZE [ 46:42 ] 0x1FERASE_GRP_MULT [ 41:37 ] 0x1FWP_GRP_SIZE [ 36:32 ] 0x0FWP_GRP_ENABLE [ 31:31 ] 0x01DEFAULT_ECC [ 30:29 ] 0x00R2W_FACTOR [ 28:26 ] 0x02WRITE_BL_LEN [ 25:22 ] 0x09 (512 Bytes)WRITE_BL_PARTIAL [ 21:21 ] 0x00reserved [ 20:17 ] 0x00CONTENT_PROT_APP [ 16:16 ] 0x00FILE_FORMAT_GRP [ 15:15 ] 0x00COPY [ 14:14 ] 0x00PERM_WRITE_PROTECT [ 13:13 ] 0x00TMP_WRITE_PROTECT [ 12:12 ] 0x00FILE_FORMAT [ 11:10 ] 0x00Field Byte ValueECC [ 9:8 ] 0x00CRC [ 7:1 ] Follow JEDEC Standard reserved [ 0:0 ] 0x01Extended Card Specific Data Register [EXT_CSD]The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working in. These modes can be changed by the host by means of the SWITCH command. For details, refer to section 7.4 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueReserved [511:506] 0EXT_SECURITY_ERR [505:505] 0x00S_CMD_SET [504:504] 0x01HPI_FEATURES [503:503] 0x01BKOPS_SUPPORT [502:502] 0x01MAX_PACKED_READS [501:501] 0x3CMAX_PACKED_WRITES [500:500] 0x20DATA_TAG_SUPPORT [499:499] 0x01TAG_UNIT_SIZE [498:498] 0x03TAG_RES_SIZE [497:497] 0x00CONTEXT_CAPABILITIES [496:496] 0x05LARGE_UNIT_SIZE_M1 [495:495] 0x17(16G) 0x2F(32G) 0x5F(64G)EXT_SUPPORT [494:494] 0x03 SUPPORTED_MODES [493:493] 0x01FFU_FEATURES [492:492] 0x00 OPERATION_CODE_TIMEOUT [491:491] 0x00FFU_ARG [490:487] 65535 BARRIER_SUPPORT [486:486] 0x01Reserved [485:309] 0CMDQ_SUPPORT [308:308] 0x01CMDQ_DEPTH [307:307] 0x0FReserved [306:306] 0x00 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305:302] 0 VENDOR_PROPRIETARY_HEALTH_REPORT [301:270] 0 DEVICE_LIFE_TIME_EST_TYP_B [269:269] 0x01DEVICE_LIFE_TIME_EST_TYP_A [268:268] 0x01PRE_EOL_INFO [267:267] 0x01 OPTIMAL_READ_SIZE [266:266] 0x01OPTIMAL_WRITE_SIZE [265:265] 0x08Field Byte Value OPTIMAL_TRIM_UNIT_SIZE [264:264] 0x01 DEVICE_VERSION [263:262] 0FIRMWARE_VERSION [261:254] 0x90 PWR_CL_DDR_200_360 [253:253] 0x00 CACHE_SIZE [252:249] 1024 GENERIC_CMD6_TIME [248:248] 0x32 POWER_OFF_LONG_TIME [247:247] 0xFF BKOPS_STATUS [246:246] 0x00 CORRECTLY_PRG_SECTORS_NUM [245:242] 0 INI_TIMEOUT_AP [241:241] 0x64 CACHE_FLUSH_POLICY [240:240] 0x01 PWR_CL_DDR_52_360 [239:239] 0x00 PWR_CL_DDR_52_195 [238:238] 0x00PWR_CL_200_195 [237:237] 0x00PWR_CL_200_130 [236:236] 0x00 MIN_PERF_DDR_W_8_52 [235:235] 0x00 MIN_PERF_DDR_R_8_52 [234:234] 0x00 Reserved [233:233] 0x00TRIM_MULT [232:232] 0x11(16G) 0x11(32G) 0x22(64G)SEC_FEATURE_SUPPORT [231:231] 0x55 SEC_ERASE_MULT [230:230] 0xF7 SEC_TRIM_MULT [229:229] 0xF7 BOOT_INFO [228:228] 0x07Reserved [227:227] 0x00 BOOT_SIZE_MULT [226:226] 0x20ACC_SIZE [225:225] 0x07(16G) 0x08(32G) 0x09(64G)HC_ERASE_GRP_SIZE [224:224] 0x01ERASE_TIMEOUT_MULT [223:223] 0x11(16G) 0x11(32G) 0x22(64G)REL_WR_SEC_C [222:222] 0x01HC_WP_GRP_SIZE [221:221] 0x10 S_C_VCC [220:220] 0x08S_C_VCCQ [219:219] 0x08 PRODUCTION_STATE_AWARENESS_TIMEOUT [218:218] 0x14 S_A_TIMEOUT [217:217] 0x15 SLEEP_NOTIFICATION_TIME [216:216] 0x0FField Byte ValueSEC_COUNT [215:212] 10207232 (16G) 20414464 (32G) 40828928 (64G)SECURE_WP_INFO [211:211] 0x01 MIN_PERF_W_8_52 [210:210] 0x08 MIN_PERF_R_8_52 [209:209] 0x08 MIN_PERF_W_8_26_4_52 [208:208] 0x08 MIN_PERF_R_8_26_4_52 [207:207] 0x08 MIN_PERF_W_4_26 [206:206] 0x08 MIN_PERF_R_4_26 [205:205] 0x08 Reserved [204:204] 0x00 PWR_CL_26_360 [203:203] 0x00 PWR_CL_52_360 [202:202] 0x00 PWR_CL_26_195 [201:201] 0x00 PWR_CL_52_195 [200:200] 0x00 PARTITION_SWITCH_TIME [199:199] 0xFF OUT_OF_INTERRUPT_TIME [198:198] 0xFF DRIVER_STRENGTH [197:197] 0x1F DEVICE_TYPE [196:196] 0x57 Reserved [195:195] 0x00 CSD_STRUCTURE [194:194] 0x02 Reserved [193:193] 0x00 EXT_CSD_REV [192:192] 0x08 CMD_SET [191:191] 0x00Reserved [190:190] 0x00 CMD_SET_REV [189:189] 0x00 Reserved [188:188] 0x00 POWER_CLASS [187:187] 0x00 Reserved [186:186] 0x00HS_TIMING [185:185] 0x01 STROBE_SUPPORT [184:184] 0x01 BUS_WIDTH [183:183] 0x02Reserved [182:182] 0x00 ERASED_MEM_CONT [181:181] 0x00 Reserved [180:180] 0x00 PARTITION_CONFIG [179:179] 0x00 BOOT_CONFIG_PROT [178:178] 0x00 BOOT_BUS_CONDITIONS [177:177] 0x00 Reserved [176:176] 0x00 ERASE_GROUP_DEF [175:175] 0x00 BOOT_WP_STATUS [174:174] 0x00C - 4Field Byte Value BOOT_WP [173:173] 0x00 Reserved [172:172] 0x00 USER_WP [171:171] 0x00 Reserved [170:170] 0x00 FW_CONFIG [169:169] 0x00 RPMB_SIZE_MULT [168:168] 0x20 WR_REL_SET [167:167] 0x00 WR_REL_PARAM [166:166] 0x15 SANITIZE_START [165:165] 0x00 BKOPS_START [164:164] 0x00 BKOPS_EN [163:163] 0x00 RST_n_FUNCTION[162:162] 0x00 HPI_MGMT[161:161] 0x00 PARTITIONING_SUPPORT [160:160] 0x07 MAX_ENH_SIZE_MULT [159:157] 623(16G) 1246(32G) 2492(64G) PARTITIONS_ATTRIBUTE[156:156] 0x01 PARTITION_SETTING_COMPLETED[155:155] 0x01 GP_SIZE_MULT_4 [154:152] 0 GP_SIZE_MULT_3 [151:149] 0 GP_SIZE_MULT_2 [148:146] 0 GP_SIZE_MULT_1[145:143] 0 ENH_SIZE_MULT[142:140] 623(16G) 1246(32G) 2492(64G)ENH_START_ADDR[139:136] 0 Reserved[135:135] 0x00 SEC_BAD_BLK_MGMNT[134:134] 0x00 PRODUCTION_STATE_AWARENESS[133:133] 0x00 TCASE_SUPPORT [132:132] 0x00 PERIODIC_WAKEUP[131:131] 0x00 PROGRAM _CID_CSD_DDR_SUPPORT[130:130] 0x01 Reserved[129:128] 0 VENDOR_SPECIFIC_FIELD[127:67 ] 538968064ERROR_CODE [ 66:65 ] 0 ERROR_TYPE[ 64:64 ] 0x00 NATIVE_SECTOR_SIZE [ 63:63 ] 0x00 USE_NATIVE_SECTOR [ 62:62 ] 0x00 DATA_SECTOR_SIZE [ 61:61 ] 0x00 INI_TIMEOUT_EMU[ 60:60 ] 0x00C - 5FieldByte Value CLASS_6_CTRL [ 59:59 ] 0x00 DYNCAP_NEEDED[ 58:58 ] 0x00 EXCEPTION_EVENTS_CTRL [ 57:56 ] 0 EXCEPTION_EVENTS_STATUS [ 55:54 ] 0 EXT_PARTITIONS_ATTRIBUTE[ 53:52 ] 0 CONTEXT_CONF[ 51:37 ] 0 PACKED_COMMAND_STATUS [ 36:36 ] 0x00 PACKED_FAILURE_INDEX [ 35:35 ] 0x00 POWER_OFF_NOTIFICATION[ 34:34 ] 0x00 CACHE_CTRL [ 33:33 ] 0x00 FLUSH_CACHE [ 32:32 ] 0x00 BARRIER_CTRL [ 31:31 ] 0x00 MODE_CONFIG[ 30:30 ] 0x00 MODE_OPERATION_CODES[ 29:29 ] 0x00 Reserved [ 28:27 ] 0 FFU_STATUS[ 26:26 ] 0x00 PRE_LOADING_DATA_SIZE [ 25:22 ] 0MAX_PRE_LOADING_DATA_SIZE[ 21:18 ] 3304106(16G) 6608213(32G) 13216426(64G)PRODUCT_STATE_AWARENESS_ENABLEMENT[ 17:17 ] 0x01 SECURE_REMOVAL_TYPE[ 16:16 ] 0x01 CMDQ_MODE_EN[ 15:15 ] 0x00 Reserved[ 14:0 ]。
MICRO-STAR INTERNATIONAL MS-98E6 (v1.x) 工业级计算机板说明书
(v1.x) Industrial Computer Boardi1Thank you for choosing the MS-98E6, an excellent industrial computerboard.Based on the innovative Intel® Apollo Lake/ Apollo Lake-I Series SoCfor optimal system efficiency, the MS-98E6 supports up to 8GB ofonboard DDR3L 1600 / 1866MHz memory and allows connection to 3independent displays with HDMI, DisplayPort, LVDS and eDP outputs.The MS-98E6 is durable under extreme environments and suitable to beapplied in every industrial field, such as digital signage, kiosk, gaming,industrial control automation and POS.1-1-1USB2 0 Connector JNVM1/ JNVM2 Jumper DC Power ConnectorAudio/ Amplifier/ SMbus Connector Nano SIM-Holder Micro SD Card SlotTPM (LPC)ConnectorUSB2 0 Connector JNVM1/ JNVM2 JumperDC Power ConnectorAudio/ Amplifier/ SMbus ConnectorNano SIM-HolderMicro SD Card SlotTPM (LPC)ConnectorOption 1Option 2RJ45 GbE LAN PortsRJ45 GbE LAN PortsUSB3 0 PortsHDMI PortHDMI PortRJ45 GbE LAN PortsUSB3 0 PortsDisplayPortDisplayPort2This chapter provides you with the information about hardwaresetup procedures. While doing the installation, be careful in holdingthe components and follow the installation procedures. For somecomponents, if you install in the wrong orientation, the components willnot work properly.Use a grounded wrist strap before handling computer components. Staticelectricity may damage the components.2-2-1Rear Panel I/ORJ45 GbE LAN PortsUSB3 0 PortsHDMI PortDisplayPortDisplayPortDisplayPort is a digital display interface standard. This connector is used connect a monitor with DisplayPort inputs.HDMI PortThe High-Definition Multimedia Interface (HDMI) is an all-digital audio/video interface capable of transmitting uncompressed streams. HDMI supports all TV3This chapter provides information on the BIOS Setup program and allowsusers to configure the system for optimal use.Users may need to run the Setup program when:■An error message appears on the screen at system startup and requests users to run SETUP.■Users want to change the default settings for customized features.• Please note that BIOS update assumes technician-level experience.• As the system BIOS is under continuous update for better system performance, the illustrations in this chapter should be held forreference only.2-3-1MainUse this menu for basic system configurations, such as time, date, etc. AdvancedUse this menu to set up the items of special enhanced features.BootUse this menu to specify the priority of boot devices.SecurityUse this menu to set supervisor and user passwords.ChipsetThis menu controls the advanced features of the onboard chipsets.PowerUse this menu to specify your settings for power management.Save & ExitThis menu allows you to load the BIOS default values or factory default settings into the BIOS and exit the BIOS setup utility with or without changes.System DateThis setting allows you to set the system date. The date format is <Day>, <Month> <Date> <Year>.System Timesetting allows you to set the system time. The time format is <Hour> <Minute> <Second>.SATA Mode SelectionThis setting specifies the SATA controller mode.Full Screen Logo DisplayThis BIOS feature determines if the BIOS should hide the normal POST messages with the motherboard or system manufacturer’s full-screen logo.When it is enabled, the BIOS will display the full-screen logo during the boot-up sequence, hiding normal POST messages.When it is disabled, the BIOS will display the normal POST messages, instead of the full-screen logo.Please note that enabling this BIOS feature often adds 2-3 seconds of delay to the booting sequence. This delay ensures that the logo is displayed for a sufficient amount of time. Therefore, it is recommended that you disable this BIOS feature for a faster boot-up time.Bootup NumLock StateThis setting is to set the Num Lock status when the system is powered on. Setting to [On] will turn on the Num Lock key when the system is powered on. Setting to [Off] will allow users to use the arrow keys on the numeric keypad.Option ROM Messagesitem is used to determine the display mode when an optional ROM initialized during POST. When set to [Force BIOS], the display mode used AMI BIOS is used. Select [Keep Current] if you want to use the display mode ofSerial Port 1/ 2/ 3/ 4/ 5/ 6This setting enables/disables the specified serial port.Change SettingsThis setting is used to change the address & IRQ settings of the specified serial port.Mode SelectSelect an operation mode for the specified serial port.FIFO ModeThis setting controls the FIFO data transfer mode.Shared IRQ ModeThis setting provides the system with the ability to share interrupts among its Watch Dog TimerYou can enable the system watch-dog timer, a hardware timer that generates a reset when the software that it monitors does not respond as expected each time the watch dog polls it.Smart Fan ConfigurationSmart SYSFAN Targetsetting enables/disables the Smart Fan function. Smartexcellent feature which will adjust the CPU/system fan speed automatically depending on the current CPU/system temperature, avoiding the overheating to damage your system.Intel Virtualization TechnologyVirtualization enhanced by Intel Virtualization Technology will allow a platform to run multiple operating systems and applications in independent partitions.virtualization, one computer system can function as multiple(Enhanced Intel SpeedStep Technology) allows the systemadjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. When disabled, the processor will return the actual maximum CPUID input value of(PXE) from BIOS.PCI/PCIE Device ConfigurationLegacy USB SupportSet to [Enabled] if you need to use any USB 1.1/2.0 device in the operating system that does not support or have any USB 1.1/2.0 driver installed, such as DOS and SCO Unix.Audio ControllerThis setting enables/disables the onboard audio controller.Launch OnBoard LAN OpROMsettings enable/disable the initialization of the onboard/onchip Boot ROM during bootup. Selecting [Disabled] will speed up the boot process.GPO0 ~ GPO7These settings control the operation mode of the specified GPIO.CSM Supportsetting enables/disables the support for Compatibility Support Module, part of the Intel Platform Innovation Framework for EFI providing the capability to support legacy BIOS interfaces.OS SelectionThis setting allows users to select the Operating System.Boot Option Prioritiessetting allows users to set the sequence of boot devices where attempts to load the disk operating system.Administrator PasswordAdministrator Password controls access to the BIOS Setup utility.User PasswordPassword controls access to the system at boot and to the BIOSSecurity Device SupportThis setting enables/disables BIOS support for security device. When set to [Disable], the OS will not show security device. TCG EFI protocol and INT1A interface will not be available.Disable Block SidThis setting enables/disables Block SID support, the specification that covers and OS communication to handle freeze-locking selfencryptingSerial Port Console RedirectionConsole RedirectionRedirection operates in host systems that do not haveand keyboard attached. This setting enables/disables the operation of console redirection. When set to [Enabled], BIOS redirects and sends all contents that should be displayed on the screen to the serial COM port for display on the terminal screen. Besides, all data received from the serial port is interpreted as keystrokes from a local keyboard.Terminal TypeTo operate the system’s console redirection, you need a terminal supporting ANSI terminal protocol and a RS-232 null modem cable connected between the host system and terminal(s). This setting specifies the type of terminal device for console redirection.Bits per second, Data Bits, Parity, Stop Bitssetting specifies the transfer rate (bits per second, datastop bits) of Console Redirection.Flow Controlcontrol is the process of managing the rate of dataTXE FW Versionshows the firmware information of the Intel Trusted Engine (TXE).TXE HMRFPOsetting enables/disables TXE HMRFPO (Host ME Protection Override).TXE EOP Messagesetting determines whether or not to send EOP (Exchange Protection) message before entering OS.DVMT Pre-AllocatedThis setting defines the DVMT pre-allocated memory. Pre-allocated memory is the small amount of system memory made available at boot time by the system BIOS for video. Pre-allocated memory is also known as locked memory. This is because it is "locked" for video use only and as such, is invisible and unable to be used by the operating system.DVMT Total Gfx MemThis setting specifies the memory size for DVMT.LCD 1 / 2 Panel TypeThis setting specifies the LCD panel type.LVDSThis setting enables/disables LVDS.MIPI-CSIThis setting enables/disables MIPI-CSI.Restore AC Power Losssetting specifies whether your system will reboot after a power failure interrupt occurs. Available settings are:[Power Off]Leaves the computer in the power off state.[Power On]Leaves the computer in the power on state.[Last State]Restores the system to the previous statusbefore power failure or interrupt occurred.Deep Sleep Modesetting enables/disables the Deep S5 power saving mode. S5 is almost same as G3 Mechanical Off, except that the PSU still supplies power,a minimum, to the power button to allow return to S0. A full reboot is required. No previous content is retained. Other components may remain powered so the computer can “wake” on input from the keyboard, clock, modem, LAN, or USB device.** Advanced Resume Events Control **PCIE PMESave Changes and ResetSave changes to CMOS and reset the system.Discard Changes and ExitAbandon all changes and exit the Setup Utility.Discard ChangesAbandon all changes.Load Optimized DefaultsUse this menu to load the default values set by the motherboard manufacturer specifically for optimal performance of the motherboard.Save as User DefaultsSave changes as the user’s default profile.Restore User DefaultsRestore the user’s default profile.Launch EFI Shell from filesystem deviceThis setting helps to launch the EFI Shell application from one of the available file system devices.This appendix provides WDT (Watch Dog Timer), GPIO (General Pur-pose Input/ Output) and LVDS Backlight programming guide.2-A-1access IO ports and defined as following.2.Watchdog Timer – WDT。
三星Exynos 4 Quad (Exynos 4412) RISC微处理器用户手册
Samsung Exynos 4 Quad(Exynos 4412)RISC MicroprocessorRevision 1.00October 2012 U s e r's M a n u a l2012 Samsung Electronics Co., Ltd. All rights reserved.Important NoticeSamsung Electronics Co. Ltd. (“Samsung”) reserves the right to make changes to the information in this publication at any time without prior notice. All information provided is for reference purpose only. Samsung assumes no responsibility for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.This publication on its own does not convey any license, either express or implied, relating to any Samsung and/or third-party products, under the intellectual property rights of Samsung and/or any third parties.Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.Customers are responsible for their own products and applications. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.Samsung products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur. Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications using Samsung products notwithstanding any information provided in this publication. Customer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim (including but not limited to personal injury or death) thatmay be associated with such unintended, unauthorizedand/or illegal use.WARNING No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung. This publication is intended for use by designated recipients only. This publication contains confidential information (including trade secrets) of Samsung protectedby Competition Law, Trade Secrets Protection Act and other related laws, and therefore may not be, in part or in whole, directly or indirectly publicized, distributed, photocopied or used (including in a posting on the Internet where unspecified access is possible) by any unauthorized third party. Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung’s trade secrets and/or confidential information.警告本文件仅向经韩国三星电子株式会社授权的人员提供，其内容含有商业秘密保护相关法规规定并受其保护的三星电子株式会社商业秘密，任何直接或间接非法向第三人披露、传播、复制或允许第三人使用该文件全部或部分内容的行为（包括在互联网等公开媒介刊登该商业秘密而可能导致不特定第三人获取相关信息的行为）皆为法律严格禁止。
中微半导体CMS89F11x用户手册说明书
CMS89F11x用户手册AD型MCUV1.3请注意以下有关CMS知识产权政策＊中微半导体公司已申请了专利，享有绝对的合法权益。
与中微半导体公司MCU或其他产品有关的专利权并未被同意授权使用，任何经由不当手段侵害中微半导体公司专利权的公司、组织或个人，中微半导体公司将采取一切可能的法律行动，遏止侵权者不当的侵权行为，并追讨中微半导体公司因侵权行为所受的损失、或侵权者所得的不法利益。
＊中微半导体公司的名称和标识都是中微半导体公司的注册商标。
＊中微半导体公司保留对规格书中产品在可靠性、功能和设计方面的改进作进一步说明的权利。
然而中微半导体公司对于规格内容的使用不负责任。
文中提到的应用其目的仅仅是用来做说明，中微半导体公司不保证和不表示这些应用没有更深入的修改就能适用，也不推荐它的产品使用在会由于故障或其它原因可能会对人身造成危害的地方。
中微半导体公司的产品不授权适用于救生、维生器件或系统中作为关键器件。
中微半导体公司拥有不事先通知而修改产品的权利，对于最新的信息，请参考我们的网站目录使用注意事项 (1)1.产品概述 (2)1.1功能特性 (2)1.2系统结构框图 (3)1.3管脚分布 (4)1.4管脚描述 (6)1.5系统配置寄存器 (7)1.6在线串行编程 (8)2.中央处理器（CPU） (9)2.1内存 (9)2.1.1程序内存 (9)2.1.2数据存储器 (14)2.2寻址方式 (16)2.2.1直接寻址 (16)2.2.2立即寻址 (16)2.2.3间接寻址 (16)2.3堆栈 (18)2.4工作寄存器（ACC） (19)2.4.1概述 (19)2.4.2ACC应用 (19)2.5程序状态寄存器（STATUS） (20)2.6预分频器（OPTION_REG） (21)2.7程序计数器（PC） (23)2.8看门狗计数器（WDT） (24)2.8.1WDT周期 (24)3.系统时钟 (25)3.1概述 (25)3.2系统振荡器 (26)3.2.1内部RC振荡 (26)3.2.2外部XT振荡 (26)3.3起振时间 (26)4.复位 (27)4.1上电复位 (27)4.2掉电复位 (28)4.2.1掉电复位的改进办法 (29)4.3看门狗复位 (29)5.1休眠模式 (30)5.1.1休眠模式应用举例 (30)5.1.2休眠模式的唤醒 (31)5.1.3休眠模式唤醒时间 (31)6.I/O端口 (32)6.1I/O口结构图 (33)6.2I/O口模式及上、下拉电阻 (34)6.2.1P0口 (34)6.2.2P1口 (36)6.2.3P2口 (38)6.2.4写I/O口 (39)6.2.5读I/O口 (39)6.3I/O口使用注意事项 (40)7.中断 (41)7.1中断概述 (41)7.2中断控制寄存器 (42)7.3中断请求寄存器 (43)7.4总中断使能控制寄存器 (44)7.5中断现场的保护方法 (45)7.6外部中断 (46)7.6.1外部中断控制寄存器 (46)7.6.2外部中断0 (47)7.6.3外部中断1 (48)7.6.4外部中断2 (48)7.6.5外部中断的响应时间 (48)7.6.6外部中断的应用注意事项 (48)7.7P0电平变化中断 (49)7.8内部定时中断 (50)7.8.1TMR1中断 (50)7.8.2TMR2中断 (51)7.9ADC中断 (52)7.10中断的优先级，及多中断嵌套 (54)8.定时计数器TMR0 (56)8.1定时计数器TMR0概述 (56)8.2与TMR0相关寄存器 (58)8.3使用外部时钟作为TMR0的时钟源 (59)8.4TMR0做定时器的应用 (60)8.4.1TMR0的基本时间常数 (60)8.4.2TMR0操作流程 (60)9.1TMR1概述 (61)9.2TMR1相关寄存器 (62)9.3TMR1的时间常数 (63)9.3.1TMR1基本时间参数 (63)9.4TMR1的应用 (63)9.4.1TMR1作定时器使用 (63)9.4.2TMR1作计数器使用 (64)10.定时计数器TMR2 (65)10.1TMR2概述 (65)10.2TMR2相关的寄存器 (67)10.3TMR2的时间常数 (68)10.3.1TMR2基本时间参数 (68)10.3.2T2DATA初值计算方法 (68)10.4TMR2应用 (69)10.5T2OUT输出 (70)10.5.1T2OUT的周期 (70)10.5.2T2OUT基本时间参数 (70)10.5.3T2OUT应用 (70)11.模数转换（ADC） (71)11.1ADC概述 (71)11.2与ADC相关寄存器 (72)11.3内部电压基准 (74)11.4ADC应用 (75)11.4.1用查询模式做AD转换流程 (75)11.4.2AD中断模式流程 (76)12.LCD驱动模块 (78)12.1LCD功能使能 (78)12.2LCD相关设置 (78)13.内置比较器 (79)13.1内置比较器概述 (79)13.2与比较器相关的寄存器 (80)13.3比较器0应用 (81)13.4比较器1应用 (82)14.数据EEPROM控制 (83)14.1数据EEPROM概述 (83)14.2相关寄存器 (84)14.2.1EEADR寄存器 (84)14.2.2EECON1和EECON2寄存器 (84)14.3读数据EEPROM存储器 (86)14.4写数据EEPROM存储器 (87)14.5数据EEPROM操作注意事项 (88)14.5.1写校验 (88)14.5.2避免误写的保护 (88)15.8位PWM（PWM0） (89)15.18位PWM概述 (89)15.2与8位PWM相关寄存器 (90)15.38位PWM的周期 (91)15.3.18位PWM调制周期 (91)15.3.28位PWM输出周期 (91)15.48位PWM占空比算法 (92)15.4.16+2模式PWM占空比 (92)15.4.27+1模式PWM占空比 (93)15.58位PWM应用 (93)16.10位PWM（PWM1） (94)16.110位PWM概述 (94)16.2与10位PWM相关寄存器 (95)16.310位PWM调制周期 (96)16.3.110位PWM调制周期 (96)16.3.210位PWM输出周期 (96)16.410位PWM占空比算法 (97)16.510位PWM应用 (98)17.高频时钟（CLO）输出 (99)17.1高频时钟（CLO）输出概述 (99)17.2高频时钟（CLO）输出波形 (99)17.3高频时钟（CLO）应用 (100)18.蜂鸣器输出（BUZZER） (101)18.1BUZZER概述 (101)18.2与BUZZER相关的寄存器 (102)18.3BUZZER输出频率 (103)18.3.1BUZZER输出频率计算方法 (103)18.3.2BUZZER输出频率表 (103)18.4BUZZER应用 (103)19.电气参数 (104)19.1DC特性 (104)19.2AC特性 (105)20.指令 (106)20.1指令一览表 (106)20.2指令说明 (108)21.封装 (124)21.1SOP8 (124)21.2SOP14 (125)21.3SOP16 (126)21.4DIP20 (127)21.5SOP20 (128)22.版本修订说明 (129)使用注意事项振荡方式选择外部XT振荡时，P2.2口只能作为输入口；选择内部RC振荡时P2.2口可作为普通IO口。
商品展示作品
特点
• • • • • • • • • • 3G+WiFi融合技术 WLAN（802.11b/g/n）连接WiFi网络上网，支持 WLAN-AP功能 ZTE-T U880支持最新的Wifi802.11n（比802.11b/g更 快） 支持WLAN-AP功能，U880可以同时成为WiFi的客户 端和服务器端 支持自适应WLAN两种认证方式：Portal自动认证、 SIM统一认证 支持WLAN 直接连接：支持一对一连接、一对多组网 支持WLAN联网游戏：四国大战、斗地主等 办公功能 ZTE-T U880可轻松编辑多种格式文档，实现真正意 义的移动办公 ZTE-T U880内置的Office 软件支持Word、Excel、 PPT文件的浏览与编辑和PDF格式文件浏览，随时随地处 理各类办公文件。
基本功能
• 短信 短信(SMS)、彩信(MMS)、免提通话、情景 、彩信 、免提通话、 模式、待机图片、主题菜单、 模式、待机图片、主题菜单、来电铃声识 来电图片识别、日历功能、闹钟功能、 别、来电图片识别、日历功能、闹钟功能、 计算器、 计算器、单位换算 • 输入法 中文输入法，英文输入法，第三方 中文输入法，英文输入法， 输入法 • 输入方式 手写 • 通话记录 已接 已拨 未接电话 已接+已拨 已拨+未接电话 • 通讯录 名片式存储
特点
• Android2.2系统应用 Android2.2系统应用 • 中兴U880内置Android Market 电子市场，能下载各种应用资源， 包括最受用户欢迎的海豚浏览器、 新浪微博、安卓玩家必选的愤怒的 小鸟等资源。 • 显示屏 • 3.5英寸两点触控电容屏，分辨 率为480X800（WVGA），显示更多内 容，画面效果更加细腻，高抗反射 能力，强光下屏幕画面依然清晰可 鉴 。
中星微芯片
中星微芯片中星微（Sunway Micro）是中国的一家领先的芯片设计公司，专注于高性能处理器和AI芯片的开发和销售。
该公司成立于2011年，总部位于北京，并在上海、深圳等城市设有分支机构。
中星微的目标是成为全球领先的芯片设计公司，为中国和世界提供创新的芯片解决方案。
首先，中星微在高性能处理器领域取得了显著成就。
该公司的高性能处理器在计算机、服务器和数据中心等领域得到广泛应用。
中星微的处理器以其卓越的计算能力、能效和稳定性而闻名，能够满足各种复杂的计算需求。
同时，该公司还提供定制化的处理器设计服务，根据客户的特定需求，为其提供个性化的解决方案。
此外，中星微在人工智能（AI）芯片的研发和销售方面也非常活跃。
随着人工智能技术的迅猛发展，AI芯片已成为当今科技产业的热门领域。
中星微的AI芯片采用先进的人工智能算法和架构，以提供高性能、低功耗的解决方案。
这些芯片广泛应用于人脸识别、语音识别、图像处理等人工智能领域，为用户提供更好的体验。
除了在技术研发上的努力，中星微还注重与其他企业和学术界的合作。
该公司与国内外的大型科技公司和高校建立了紧密的合作关系，共同推动芯片技术的创新和发展。
中星微还积极参与国内外的芯片展览和技术研讨会，与业界专家和学者进行交流和合作，不断提升自身的研发能力和市场竞争力。
中星微还注重知识产权的保护和自主研发能力的提升。
该公司拥有多项自主知识产权，包括芯片设计和算法技术等领域。
中星微通过加强技术研发团队的建设和投入大量资源，提高了自主创新能力，为产品的推出和市场的开拓奠定了坚实的基础。
总而言之，中星微作为中国领先的芯片设计公司，通过在高性能处理器和AI芯片领域的创新研发和市场推广，取得了良好的成绩。
中星微将继续致力于芯片技术的创新和发展，为中国和世界的科技产业做出更大的贡献。
微芯片官网-室内GNSS主机定位系统1100i Release 3.0说明书
Indoor Integrated GNSS Master (IGM and IGM Plus) 1100i Release 3.0Easy-to-Deploy Small Indoor PTP Grandmaster for the EdgeNew Features Hardware - IGM Plus Model • SC-cut oscillator for enhanced time keeping holdover• GNSS receiver for additional Galileo and QZSS supportSoftware• IPv6 support for OAM/Management • Group configuration with Zero Touch Provisioning through DHCP• Individual device configuration and management through full CLI support Features• Small form factor with single 1 GbE RJ45 port• PTP profiles: ITU-T G.8265.1, ITU-TG.8275.1 (L2 multicast), ITU-T G.8275.2(L3 unicast), Telecom 2008, and Ethernet default• One-step and two-step clock• SyncE input, output• PTP input for GNSS back-up• APTS and asymmetry compensation • IPv4 and IPv6 including PTP traffic and OAM/Management• Up to 32 clients• License control• 802.1Q VLANs• GNSS receiver with assisted GNSS support• GPS, Glonass (Global Orbiting Navigation Satellite System; Russia), Beidou-ready,SBAS; IGM Plus model : Galileo andQZSS• Time to First Fix (TTFF) of ten minutes to less than one hour until system lock Benefits• Reduced installation costs and simplifiedcabling• Enhanced indoor GNSS performance• Receives GNSS signals when deployedindoors and/or in deep urban canyons• Best-in-class sync solution• Reliability (no external environmentalchallenges)• Deployment flexibility (small size, wallorceiling-mount, and indoor)Ceiling and Wall Mounted In-BuildingIGM UnitPrecise synchronization of indoor smallcells requires a GPS timing source,especially for phase applications.Installing a GPS antenna on the roof ofthe building or enabling each small cellwith GPS is complicated and expensive.The revolutionary Microchip IntegratedGNSS Master (IGM) solves this problemby bringing precise GNSS-based timeto indoor small cell deployments. TheIGM integrates a PTP grandmaster witha GNSS receiver and antenna in a small,fully-contained package designed to bemounted to an inside wall or ceiling.The Microchip IGM does not use anexternal antenna, significantly reducingthe expenses related to purchasing,installing, and maintaining the externalGNSS cable systems required for typicalGNSS timing receivers. Furthermore,the IGM uses Power over Ethernet (PoE)to further simplify the installation. Theunit will automatically self-configureusing Zero Touch Provisioning throughDHCP, lock to GNSS signals, and beginPTP grandmaster operations when itis mounted on a wall or ceiling (prefer-ably near a window). On-premise userconfiguration is not required.IGM-1100i UnitProblem to SolveLTE-TDD, LTE-A, and LTE-FDD requiretight coordination (eICIC, CoMP) andvery tight UTC-aligned phase synchroni-zation. The only cost effective solution toprovide this level of phase synchroniza-tion is to use GNSS PTP timing systemsrequire an antenna to pick up the satellitesignals. Due to the very low powerof these signals, an external GNSSantenna—often mounted on the roof forindoor small cells—has been the primarytechnique for signal acquisition. Theproblem is that indoor small cells thatrequire synchronization are by natureoften installed in areas of very low cellularand GNSS signal strength. As a result,the GNSS timing receiver must often runa very long and expensive cable to theroof of the building in order to providesupport for the few small cells within.In tall, multi-floor buildings, running an antenna cable to the roof is either very expensive or simply not feasible. The antenna installation costs—which often include expensive permits, labor, material, monthly roof rental fees, and more—can quickly exceed the cost of the GNSS PTP grandmaster and small cells alone. What is needed is a quick and simple solution to bring accurate PTP grandmaster timing closer to the small cells.Deployment AutomationCustomers need to deploy multiple units in an automated fashion to avoid individual configurations (which can beaccomplished through CLI). Zero Touch Provisioning can be accomplished with a configuration file that can be leveraged on a large number of devices through a DHCP server with Option 43 (IPv4) or Option 17 (IPv6).Solution: Integrated GNSS MasterThe Microchip indoor wall- or ceiling-mounted IEEE 1588 IGM grandmaster with integrated GNSS receiver and antenna entirely eliminates the external antenna along with its expen -sive related cabling costs. A single Ethernet connection is used for auto configuration management: a PoE connection for the IGM and PTP grandmaster operations to precisely synchronize the small cells in the building. The innovative and extremely sensitive GNSS receiver and patented Microchip timing algorithms result in a revolutionary indoor GNSS timing solution proven to work in many different indoor environments. IGM can also be managed with static IP and CLI over SSHv2. Once installed, the IGM locks to GNSS signals and provides the accurate and precise PTP grandmaster synchronization needed for optimum small cell operations.SpecificationsManagement and Interfaces• In-band using Ethernet port• IPv4 and IPv6 with up to 20 VLANs• TimePictra ® support through SNMP , fault only•Zero Touch Provisioning through DHCP Option 43 (IPv4) or Option 17 (IPv6)• Full CLI over SSHv2• SNMP v2/v3• Internal logOutputs• PTP grandmaster sync output • 1PPS test point• SyncE output with ESMC supportInputs• PTP client with APTS capability • SyncE inputDiagnostics• Alarms: SNMP traps• LEDs: Sync, Network, AlarmPlug and Play• Auto-configuration through DHCP Option 43 (IPv4) orOption 17 (IPv6)• Communicate with external servers (DHCP or static IP A-GNSS)• Minimal manual intervention with basic tools for deciding best placement of unitRedundancy • Achieved by deploying two or more IGM units at a site with clientfailover capabilitiesPower• PoE Class 3 input • Power: <12.95 WCapacity• Base model four unicast slaves at 128 pkt/sec. Upgrades bylicense to 8, 16, and 32 1588 PTP slaves.Mechanical • Size: Height: 7.766 in; Width: 6.638 in; Depth: 1.456 in • Weight: 1.65 lbsInstallation• Indoor mounting: Vertical wall-mount or ceiling-mount withsame unitThe Microchip name and logo, the Microchip logo and TimePictra are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies.© 2019, Microchip Technology Incorporated. All Rights Reserved. 12/19 900-00724-300 Rev B DS00002996BInformation contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THEINFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.。
中星九号接收机各常用芯片升级46台工具和bin文件使用教程
接收机各常用芯片升级46台工具和bin文件使用教程全集, 工具借这儿再声明一下：本人不算高手，本文也旨在抛砖引玉，真切希望那些高手多施舍点技艺。
引子：本人从事家电维修行业，近期接大量中9接收机升级，已成功“升级”大量上寨接收机，为了方便同行，故将成功经验整理发布，附全4类芯片：海尔（Hi2023，Hi2023E），华亚HTV903(F)，国芯（GX3001，GX6121 等），阿里（ALi M3330E）的刷机软件和各类芯片46台的成功数据，数据均为本版块收集亲测，首先感谢原作者！为了避免刷成砖头，请认真参考以下内容！硬件准备：万用电表。
串口刷机板（TTL转接板。
可以自制，现成的也需要自制各种联机插线），标准串口延长线（用于使用标准9芯串口的接收机）万用电表：世人皆知。
用于判断各类接收机升级数据接口各引脚功能。
与电脑连接硬件：如果是标准9芯串口插头，直接使用标准串口延长线。
如果是4线或5线插排，请使用TTL转接板接入电脑的串口。
串口刷机板：本人是自制的（成本6元左右，一个串口插头，max232集成电路，电解等），淘宝也有卖（大约12元钱+运费），自制电路图纸网上随便就可以找到，就是一个max232芯片以及一些辅助原件。
刷机板自身工作电源无法像图纸上那样从串口获得，可以从5线数据线的4脚得到14V然后经过78L05稳压供给。
但4线的数据接口标称3.3V（有些好像标5V的，未测），故本人从USB端口供电，直供5V，未使用耦合电路也是成功的，建议大家从USB端口直接供电。
只要找到一个退休的USB鼠标或摄像头剪下插头即可，非常实用。
该板连接接收机最终是3根线：公用地线，读数据，写数据。
用万用表判断4线或5线的数据接口：地线：不用说了吧？就是和高频头外壳直通的那根！呵呵！电源线：无论是多高的电压，电源相对于任何数据引脚都有相对较小的对地电阻，对地反向二极管导通性更明显。
数据读写线：两个引脚靠在一起，万用表实测电压为3.3V，而且紧靠接地脚。
中星微发布开放移动平台和移动多媒体处理器
抑 制器。它是行 业首次商业性推 出之
独 立ＤＰ Ｄ装 置 ，无 需 外 置 处 理 器 或支 援 线 路 ，且 无 需 任 何 算 法 编 程 。所 有
的 ｌ ×１ ｎ Ｇ Ｏ ０ｌ ｌ Ａ封 装 ，适 合 空 间 尺 业界 最 先 进 、最 有 效 的 ６ ｎ Ｆ ＧＡ ｌ Ｂ ｌ ５ ｍ Ｐ
ｘ ｉｘｃ ｍ ／ ｎ ｖｒ ｘ ｉ ．ｏ ｃ ／ ｉｅ ５ ｌ ｎ ｔ
器 。 为 了 在 １８ ．Ｖ电 压 下 维 持 所 需 的 性 能 ，Ｉ ／ Ｏ端 口还 包 含 了 可 通 过 软 件 来控 制的升压器 。
网 址 ：Ｗｃｗ．ｔ １ ｏ ￣ ａ ｍｅ ． ｍ ｃ
０ｐ ｉ ｈ ｏ 紧凑数 字式预 ｔ ｒｎ ｃ
Ｆ ＧＡ平 台 增 加 三 款 新 型 小 尺 寸 封 装 Ｐ
器件 ，以满足新兴市 场对可编程逻辑 器件 成 本和 密 度 的 要求 。其 中逻 辑
优 化 的Ｌ 平 台增 加 了Ｖｉ ｅ 一 Ｘ１５ Ｘ ｒ ｘ５Ｌ ５ ｔ 爱 特 梅 尔 公 司 （Ａ ｔｍ 器 件 ，Ｖｉｔ ｘ５ ＬＸＴ平 台 则 增 加 了 ｅ ｌ ｒｅ －
路 （Ｃ） ，用 以消除非 线性失 真 ，此 Ｉ
乃 用 于 无 线 基 础 设 备 及 其 他 信 号 处理
性能计算应用等领域 实现 更高 水平 的
系统的昂贵 功放器 （Ａ）之主要性 能 Ｐ
从 而 减 少 保 存 程 序 和 批 量 数 据 的 存 储 成本 优 化 。 器 的 数 量 。 芯 片 采用 球量推 出
０Ｐｔ ｈｒ 宣 布 ， 已 批 量 生 ｉ ｏｒ Ｃ ｌ
产 ０Ｐ ４ ０ １ Ｉ ４ ０ ． ＢＢＧ 及 ＯＰ ４ ０ ５ ４ ０ ．
《中星微电子》课件
中星微电子始终坚持自主创新，不断推出具有 核心竞争力的产品和技术，为全球数字多媒体 产业的发展做出了重要贡献。
产品与服务
02
产品类型
数字多媒体芯片
中星微电子推出的数字多媒体芯 片，广泛应用于安防监控、车载
电子、智能家居等领域。
《中星微电子》ppt课 件
目录
• 公司简介 • 产品与服务 • 技术与创新 • 市场与竞争 • 未来展望
公司简介
01
公司背景
中星微电子是中国第一家自主 设计并量产数字多媒体芯片的 半导体企业。
公司成立于1999年，由多位留 美归国专家创办，总部位于北 京，在上海、深圳、天津等地 设有分支机构。
低功耗
中星微电子的芯片在保证高性能的同时，采用低功耗设计，有效延 长了设备的续航时间。
易于集成
中星微电子的芯片具有标准化的接口和规范，易于与各种主流芯片 和系统集成。
服务介绍
技术支持
培训服务
中星微电子提供全面的技术支持，包 括芯片选型、原理图设计、PCB布局 等，帮助客户快速实现产品开发。
中星微电子为客户提供芯片应用培训 服务，帮助客户更好地掌握芯片的使 用和开发技巧。
定制服务
中星微电子可根据客户需求，提供定 制化的芯片设计和生产服务，满足客 户的特殊需求。
技术与创新
03
技术研发
01
02
03
自主研发
中星微电子致力于自主研 发，不断推出具有自主知 识产权的技术和产品。
持续投入
公司每年投入大量资金用 于技术研发，保持技术领 先地位。
合作与交流
中星微电子积极与国内外 知名企业和高校合作，共 同开展技术研发和交流。
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-VC0988
Mobile Audio Processor
Sept. 31 2007
Vimicro Corporation
Founded in 1999 Headquarter: Beijing, China R&D Centers & World Offices: Beijing, Shanghai, Shenzhen, Hong Kong Taipei, Mountain View, CA, USA Total employees: 600 Engineers 466
VC0988 •MP3 decoder •AAC decoder •AMR decoder •Storage Card •USB2.0HS •File System
H2 ……
H1 2006
H2
Q1 2007
Q2
Q3 2007
Q4
Q1 2008
8
Comparison Among VC0968/VC0978/VC0988
2
Vimicro Introduction
Worldwide market share #1 in PC camera controller
( NASDAQ: VIMC)
China market share #1 in Mobile Ringtone IC
3
System Requirement For The Music Phone
7
Roadmap For MP3 Player Chip
VC0968 •MP3 Player •SD Card •NandFlash •USB2.0HS •Audio Center •File System
VC0978 •MP3 Player •Storage Card •NandFlash •USB2.0HS •File System
Music Phone =
VC0968/978/988
Faked MP4 Phone= VC0968/978/988 + VC0528/VC0548 Real MP4 Phone =
VC0988 + VC0578
10
Vimcro Camera Chip Roadmap
•5M •JPEG •ISP •MPEG-4 codec(30fps@CIF) •SRAM 512KB •4x hardware interpolation
VC0578
3G
VC0588
•5M •JPEG •ISP •MPEG-4 codec(30fps@CIF) •TV Out •SRAM 512KB •4x hardware interpolation
2.5G
VC0568
•1.3M •JPEG •ISP •SRAM 384KB
VC0548
•1.3M •JPEG •SRAM 128KB •4x hardware interpolation
6
Key Feature For VC0988
MP3/AAC/AMR Decoder FAT 16/32 System USB2.0 HS/FS Device SD/MMC Controller Ten Bands Equalizer Stereo Audio DAC Stereo Headset PA Stereo Analog Input For FM 7x7 QFN Package For Easy Assembling
5
System Architecture For VC0988
GPIO I2S I/O
10-Band Equalizer
Stereo FM Radio
Analog Input
I2S
DAC
Headset Receiver
MP3/AAC/AMR Decoder
Headset PA
Stereo HeadSet
Audio Mixer
Analog Output
External Speaker PA
Baseband
Baseband I/F FAT File System
USB2.0HS Device Controller
PC
SD & MCC DMA Controller Storage Card I/F
T flash
Low Cost Low Power Music Quality Multi-format Music File High Efficiency File System High Speed PC Connection System Extension
4
What VC0988 could provide
Yes
Yes N/A
N/A
Yes N/A
N/A
N/A Yes
AMR Decoder
NandFlash Package
N/A
Yes BGA112pins 9x9
N/A
Yes
Yes
N/A
BGA100pins 8x8 QFN48pins 7x7 BGA112pins 9x9
9
Flexible System Extension
VC0558
•VGA •JPEG •ISP •ห้องสมุดไป่ตู้RAM 64KB
VC0528
P2P
•0.3M •JPEG •SRAM 128KB •4x hardware interpolation
……
05 Q1
Q2
Q3
Q4
06 Q1
Q2
Q3
Q4
07 Q1
Q2
11
Thank You
12
Features DAC ADC Speaker PA Analog Input VC0968 Stereo Stereo Yes Mono VC0978 Stereo N/A Yes Stereo VC0988 Stereo N/A N/A Stereo
MIC Bias
Midi AAC Decoder