SmartfusionAMBA指南

SmartFusion应用指南
MSS-AMBA相关文档阅读笔记
2010/12/15
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1 AHB BUS MATRIX---MSS的脊梁
1.1AHB BUS MATRIX简介
AHB BUS MATRIX 是多层AHB 矩阵。

允许一个主机操作A从机，另一个主机操作B从机。

当二者同时对C进行操作时，仲裁模块发挥作用，采用客户定制的方式或者乒乓方式对主机进行仲裁。

理论吞吐量为16Gbps.
通过上图，得知AHB MARTIX共拥有5个MASTER和8个SLAVE。

在AHB BUS MATRIX中实现的路径是理论路径的子集。

此外，CORTEX-M3的IBUS和DBUS在MATRIX内部被多路选择，因此公用一个MASTER PORT，二者无法同时激活。

1.2AHB BUS MATRIX连接关系
通过上表可以得知，AHB BUS MATRIX中各master与slave的连接权限。

一般来说，除了CORTEX-M3外的master 和slave在上电时都会被关掉，用户需要通过设置AHB_MATRIX_CR中的相关位来打开这些master和slave。

CORTEX-M3是系统中唯一可以是使能其他MASTER的MASTER,因为其PPB总线上挂了一个可以使能其他MASTER的控制寄存器。

注意，关于ENVM使用时，需要明确一点，在命令ENVM进行编程或者擦写时，其他MASTER不会自动得知ENVM是不可读取的。

因此，此时需要通过软件信号来控制其他MASTER的连接路径。

1.3仲裁简介：
仲裁器在slave的端口上。

通常仲裁方式分为两种:循环方式和权重循环方式。

通过设置AHB_MATRIX_CR中的COM_WEIGHTEDMODE位来切换。

循环方式
权重循环方式
2.AMBA BUS 简介：（结合ACTEL的IP Core）
2.1AHB Lite Core
AHB Lite Core 是AHB Lite 总线的一种多层实现，它包含2个Master，16个Slave和1第17个超大空间的slave。

Remap功能只针对master 0使用，用于切换slot 0和slot 1的映射地址。

引脚拉高代表使用,否则就拉低。

2.1.1拥有两种操作模式：
●固定地址空间16个SLAVE，每个256M（2的28次方，高四位用于选中1个SLAVE）
●固定地址空间15个SLAVE，每个64K，此外还有16个4k的Init/Config Client,额外的还
有一个极大的slave，为2G。

（建议使用此模式）
2.1.2 内存映射计算：
建议使用第二种配置方式，而且从机的挂靠最好从slot 5开始。

每个Slot 占用空如下：
2.2 AHB Lite 知识简介
AHB Lite 是一种支持单Master的高带宽的总线接口
其特性如下：
AHB Lite的Slave多为内部的存储设备，外部存储器接口，和高吞吐量的外设。

为了保证系统的性能，低吞吐量的外设都挂在AHB LITE的slave—APB Bridge上。

2.2.1 基本结构介绍
下图为一个简单的单Maste 三Slave系统连接图。

其中，总线内部互连结构包含了地址译码器和Slave To Master 的多路选择器。

保证合理的选通。

●Master
主机提供地址和控制信号用来实现读写操作。

●Slave
从机返回主机的信号如下:
从机接口信号如下：
●Decorder
译码器对每次传输的地址进行译码，提供选择信号。

此外，也对多路选择器提供控制信号。

●Multiplexor
多路选择器用于将读数据总线和响应进行多路选择。

主机通过驱动地址信号和控制信号来开始传输。

这些信号包含了地址，传输方向，传输宽度及确定是否是突发传输的一部分。

传输类型如下：
传输的过程包含以下两个部分：
从机无法要求主机延长地址周期，因此必须在所有从机必须在地址周期获取地址。

但是，从机可以要求主机延长数据周期，拉低HREADY信号来使主机插入等待周期，为从机提供足够的时间进行提供数据或扑捉数据。

2.2.3 多层AHB Lite
由于AHB Lite是单主机系统，所以要实现多主机系统，必须引入多层互联模块来隔离各个主机，同时实现共享对从机的通道，此外，此模块还要提供对从机的仲裁。

多层互联模块包含以下两个部分：
当多层都打算持续读写同一个从机时，此时，多层互联中的仲裁发挥作用决定哪层获得权力，未获得的使用HREADY使其等待，直至轮到其传输。

每个从机都有自己的仲裁机制：
具体实现形式：
随着层数的增加，内部互联模块的资源占用会快速增加。

采用以下方案降低面积：
➢局部从机方案：由于部分从机只会被某主机使用，因此，可以采用此种方案。

➢多从机映射为一个从机口,适合多个低吞吐量的从机，例如APB Bridge。

➢多主机公用一层,多用于测试端口
➢分立的主从系统,可以共用一个SLAVE作为BUFFER
2.2.4 信号列表
代指信号由谁产生
全局信号：
主机信号：
从机信号：
译码信号：
2.2.5 传输介绍：
●基本传输：包含一个地址周期，一个数据周期。

1.主机在HCLK的上升沿后，驱动地址和控制信号。

2.从机在下一个HCLK的上升沿，采用地址和控制信号。

3.从机采样地址和控制信号后，它开始驱动HREADY信号，此信号在第三个HCLK被采样。

●传输类型：
2.2.6 HCLK 和HRESET_N
A.每一个AHB Lite组件拥有单独的HCLK，输入数据在HCLK的上升沿采集，输出数据在HCLK的上
升沿后发生变化。

B.HRESETN用于复位总线上的所有组件。

一般来说，异步复位，同步释放。

C.复位时，主机的控制和地址信号必须为可知的状态，而且HTRANS必须为IDLE。

D.复位时，从机的HREADYOUT必须为高，保证传输可以进行。

2.2.7 Slave Response Signals
主机开始传输后，从机便开始控制传输的进度。

主机一旦开始一个传输，便无法结束此传输。

从机在连通后，通过HREADY和HRESP来反映状态。

从机可以通过以下三种方式结束传输：
补充：ERROR响应
⏹错误响应需要两个周期：
◆第一个周期：从机将HRESP置高，用于显示错误，同时将HREADY拉低，用于延长一个
周期。

◆第二个周期：从机将HREADY置高，结束传输；HRESP保持高电平，表示ERROR发生。

⏹两个周期的原因：在从机进行提示有错误发生时，主机已经在向总线发送下一个传输的地址。

采用两个周期的操作，可以给予主机足够的时间结束下一个传输，并且将HTRANS置为IDLE
状态。

2.2.8Bus Interconnection
2.2.8.1地址译码：
中央地址译码提供一个HSELX信号，为总线上的每一个从机提供选择信号
从机必须只能在HREADY为高时，采样HSEL,地址和控制信号，表示当前传输已经结束。

每个从机分配的地址空间至少为1KB，与之相对应，主机设计的递增型传输不能超过1KB。

从而保证不会超越寻址边界。

✧补充：
总线互联
2.3APB Bridge Core
2.3.1使用规则
只能有一个APB3主机挂到此桥上，通过主机的PSEL和PADDR信号进行译码确定指向从机的PSEL 信号，从而，一个时刻只能沟通一个从机。

直接寻址：所有的16个APB从机节点拥有相同的地址空间。

间接寻址：第一个节点拥有4GB（2^32）的寻址空间，第二个节点不用，而作为第一个节点的地址寄存器，其他的同直接寻址。

间接寻址时，PCLK才有作用，而且地址端口宽度为32；直接寻址时，地址宽度为24.
2.3.3资源占用
APB3的资源占用量为38 Tile。

2.4APB 接口
APB接口是一种为低速外设提供的低功耗和低复杂度的接口。

一般来说，连接的外设都为低带宽，而且不要求很高性能，不支持流水线操作。

Key Feature:为外设的可编程的控制寄存器提供接口。

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2024特发性膀胱过度活动症诊断和治疗：AUASUFU指南

2024特发性膀胱过度活动症诊断和治疗：AUA/SUFU指南本次美国泌尿外科协会（AUA）/女性尿动力学，盆腔医学及尿路重建学会（SUFU）指南修订的目的是进一步为所有泌尿专业临床医生提供特发性膀胱过度活动症（OAB）相关的评估、管理和治疗循证指导，该指南近期发表于The Journal of Urology杂志，其中，对OAB评估和诊断、共同决策流程、侵入性/非侵入性疗法、药物治疗、微创手术等方面进行了更新。

评估和诊断1.在对有OAB症状的患者进行初步诊断评估时，临床医生应：①获取病史并全面评估膀胱症状；②进行体格检查；③进行尿液分析以排除轻微血尿（镜下血尿）和感染。

（临床原则）2.临床医生可在未进行体格检查前提下，为有OAB症状的患者提供远程医疗服务进行初步评估，但患者应提供当地实验室所进行的尿液分析检查结果（或最近复查的实验室结果，如果有的话）。

（专家意见）3.临床医生可对有OAB症状的患者进行残余尿量（PVR）检查，以排除排空不全或尿潴留，尤其是对于同时伴有储尿期和排尿期症状的患者。

（临床原则）4.临床医生可对有OAB症状的患者进行症状调查问卷和/或排尿日记评估，以协助诊断OAB、排除其他疾病、确定症状困扰程度和/或评估疗效。

（临床原则）5.临床医生不应在OAB患者的初步评估中常规进行尿动力学、膀胱镜或尿路造影检查。

（临床原则）6.若诊断不明确，临床医生可在OAB患者的初步评估中行尿动力学、膀胱镜或尿路造影等进一步检查。

（临床原则）7.临床医生应评估OAB患者可能导致尿频、尿急和/或急迫性尿失禁的合并症，并提供患者教育使其了解管理这些疾病对膀胱症状的作用。

（专家意见）8.医生可使用远程医疗对OAB患者进行随访。

（专家意见）共同决策9.临床医生应与OAB患者共同决策，考虑患者表达的价值观、偏好和治疗目标，以帮助他们就不同的治疗模式做出知情的决定或探讨仅观察的治疗选择。

（临床原则）非侵入性疗法10.临床医生应与所有急迫性尿失禁（UUI）患者探讨尿失禁的管理策略（如尿垫、尿布、护肤霜等）。

美国缺血性脑卒中的指南解读_手把手教你急诊处理

美国缺血性脑卒中指南解读：手把手教你急诊处理导读：2018年，美国心脏学会（AHA和美国卒中学会（ASA根据急性缺血性脑卒中（AIS）的最新研究成果，继2013指南之后又联合制定了“ 2018急性缺血性脑卒中早期管理指南”，主要变化内容为急性期影像学检查、静脉溶栓治疗和机械取栓治疗等方面。

通过对2018指南全面解读，希望为相关医疗工作人员提供参考以改善AIS患者的诊疗及预后。

本文摘录了急诊处理部分的内容，供大家参考。

静脉阿替普酶治疗1. 阿替普酶的治疗剂量及适应证2013指南和2018指南都肯定了阿替普酶静脉溶栓治疗对AIS的重要性，而且治疗效果具有时间依赖性，应尽早开始。

由于低血糖和高血糖的患者都有可能出现类似脑卒中的症状，所以在治疗前需测定血糖，并且阿替普酶对非血管性疾病没有使用指征。

除此之外，从发病到接受阿替普酶治疗的时间对患者预后也较为关键，故不能因患者症状有所改善而延误静脉阿替普酶治疗。

2018指南细化及修改了静脉阿替普酶溶栓治疗的原则，指出需根据标准来决定静脉阿替普酶治疗的实施。

根据大量RCT证据，2018指南推荐在发病3.0 h内进行静脉溶栓治疗，治疗剂量为0.9 mg/kg，最大剂量为90 mg 1 min内静脉推注10%剩余90%隹持静脉滴注〉60 min （I /A）。

2013指南也提出，对于发病3.0〜4.5 h内的患者可按上述方法治疗，但应增加排除标准，即年龄〉80岁、口服抗凝剂且不考虑国际标准化比值（INR）、美国国立卫生研究院卒中量表（NIHSS评分基线〉25分、影像学显示大脑中动脉供血区损伤超过1/3、或有卒中史和糖尿病史。

但根据AHA/美国卒中学会（ASA总结的数据分析得出上述排除标准，在临床实践应用中可能不合理，故2018指南在此条推荐中剔除了上述排除标准（I /B-R ）。

在权重风险与获益的情况下，2018指南推荐对于符合其他标准的轻度脑卒中，在发病3.0〜4.5 h内行静脉阿替普酶治疗可能合理（H b/B-NR ）。

Ambra Health 用户指南说明书

Ambra – User GuideHealth Images has provided a list of your site’s personnel that need access to Ambra Health.You will receive an email with a link to login and set your pass-word. As soon as you click the link, you will be required to enter your email and choose a password that is 8 characters or longer , containing 2 numbers and 2 letters. The link in this email will expire in 5 days.If the link expires, please navigate to the URL below and click the ‘Forgot your password?’ link. This will require that you enter your email and then set a password.https:///If you have your username and password already, click on the link above. Enter your username (email address) and password.If you need helpAmbra Support888 315 0790 (any time)***********************In the ‘Actions’ column ...The ViewerThe first series will display in the Viewer. To view another series, click or drag-and-drop from the thumbnails at the bottom of the screen.The active series is highlighted in blue in the thumbnail bar. Right-click anywhere on the image to display a list of favorite tools:To close the Viewer and return to the studies list, click the ‘X’ button in the upper right corner.Viewer Main ToolbarThe full toolset is available in the toolbar. Click the ‘Layout’ button to display multiple series simultaneously.ViewToggles the View sub-toolbar visible/hid-den. See sub-toolbar button descriptions on next page.ScrollScrolls through a study’s images. Use mouse wheel to scroll.Window LevelSets image’s window width (contrast) and window level (the number at the center of the window).Mouse: Window width: hold left click, move mouse left-right. Window level: hold left click, scroll up-down. Touch pad: Window width: one finger tap, drag left-right. Window level: one finger tap, drag up-down. See win- dow width/level description on a subsequent page.AnnotateToggles Annotation sub-toolbar visible/ hidden. See annotation sub-toolbar but-ton descriptions on a subsequent page. ProbeThis toolbar button appears only when view- ing CTs. Click and drag on an im-age to read Hounsfield values.ResetReturns series to original state while remaining on current image. Resets window level, invert tone, rotation, zoom, free draw and line mea- sure annota-tions.3DToggles 3D sub-toolbar visible/youtChoose number of images to displayfrom the grid. ‘Maximize’ opens theselected series in a one- up full screenview. ‘New’ opens the study in a newbrowser tab.PrintOpens a page in a new browser windowwith a hyperlinked list of all availableimages in the study(s) being viewed.See a subsequent page for how-to-useinstructions.InfoToggle to show/hide study information.Annotations visible/hiddenToggle to show/hide annotations.InvertInverts image colors.ExportExport png, create a secondary capture,view the study meta data in a new tab.CineView images as a movie. US (multi-frame) studies are displayed with HTML5video in actual frames per second. SeeCine Sub-Toolbar in Clinical ViewerGuide.KeyMakes the visible study image ( high-lighted with a blue bounding box ), aKey image. A study’s key images can beviewed by selecting ‘View Key Images’ inthe view options menu in the studies list.ThumbsToggles study thumbnails visible/hidden.MeetStart a live collaborative meeting withother DG users.Actions‘Share’ shortcuts. See sub-toolbar de-scription in Clinical Viewer Guide.DeleteDelete images or series. See sub-toolbardescription in Clinical Viewer Guide.SettingsOpens the viewer settings editor whichallows you to set a default layout, defaultmouse tool, thumbnails position, toolbarbuttons by modality, default cine speedby modality, Window Level presets bymodality, text display by modality, andhanging protocols by modality.EnhanceLocally enhance the contrast of an im-age. This filter provides an alternative tothe window/level filter for global contrastenhancement.Record ( Audio )Opens the audio recorder in a new win-dow. Audio recordings are saved to thestudy as WAV file attachments.Record ( Script )Captures screen activity in the viewer (video ), and microphone input ( audio). Movie files are automatically savedas study attachments, and available forreplay from the attachments list at thebottom of the study thumbnails column.Upload Outside StudiesTo upload studies, click the ‘Add Study’ dropdown and selectThis page will appear.Click ‘Choose File’.Select the folder where your filesare located.The system will scan the selectedfiles.After the file scan, select (check)the study(s) to upload and click‘Upload Selected Studies’After the study has beenuploaded, you will receive asuccess message.Share Studies to Health ImagesTo share a study with Health Images, locate the study you wouldlike to share and check the box next to the patient name.Then, in the ‘Actions’ dropdown menu, select ‘Share’.A window will appear.Click the ‘Organization’ tab.Check the box next to Health Images.Click ‘Share Studies’.!。

2022年美国麻醉医师协会《困难气道管理实践指南》解读

2022年美国麻醉医师协会《困难气道管理实践指南》解读2022年美国麻醉医师协会《困难气道管理实践指南》解读随着医学的不断发展，麻醉医师在手术过程中起到了至关重要的作用。

而在麻醉过程中，气道管理是关键环节之一。

为了进一步提高麻醉医师的专业水平，美国麻醉医师协会近日发布了《困难气道管理实践指南》。

本文将对这一指南进行解读，帮助读者更好地理解困难气道管理的重要性以及指南所提供的实践指导。

首先，我们需要明确什么是困难气道。

困难气道是指在麻醉过程中，无法简单、顺利、安全地实施通气和插管操作的情况。

这可能由于气道解剖异常、炎症性水肿、肿瘤等原因导致的气道狭窄或阻塞。

困难气道的管理是麻醉医师必须掌握的重要技术之一。

指南首先介绍了识别困难气道的方法。

麻醉医师需要在患者评估的早期阶段就有效地评估气道的难易程度。

指南指出，通过全面的患者询问、体格检查和影像学辅助等手段，可以获得更准确的诊断。

此外，指南还强调了诊断技术的改进。

例如，引入了红外线成像技术、声音诊断设备等新技术，以帮助麻醉医师准确判断气道状况。

在识别困难气道后，指南详细介绍了不同级别的治疗策略。

根据气道控制难度的不同，将困难气道分为简单、中等和复杂三个级别。

对于简单的困难气道，可以采用非侵入性的措施，如抬高头部、气道辅助装置等。

对于中等和复杂级别的困难气道，需要更加积极地采取侵入性治疗方法，如气道导管插入、急救气道设备使用等。

指南还提及了特殊情况下的应对策略，如儿童、孕妇、老年人等患者的特殊处理。

除了治疗策略，指南还强调了预防困难气道的重要性。

麻醉医师需要在麻醉前进行充分的准备工作，包括详细了解患者的病史、进行充分的诊断、选择适当的麻醉方法等。

此外，指南还提出了麻醉医师培训和技术更新的建议，以提高麻醉医师的专业水平，提升气道管理的质量。

最后，指南强调了团队合作的重要性。

困难气道的管理需要多学科的合作，包括麻醉师、外科医生、呼吸治疗师等。

团队合作可以提高气道管理的效率和安全性，避免潜在的风险。

2020 AHA心肺复苏指南解读(七)——成人基础和高级生命支持主要推荐意见总结

2020 AHA心肺复苏指南解读(七)——成人基础和高级生命支持主要推荐意见总结2020 AHA心肺复苏指南解读(七)——成人基础和高级生命支持主要推荐意见总结2020年，美国心脏协会（AHA）发布了最新的心肺复苏指南，以指导临床实践中的成人基础生命支持（BLS）和高级生命支持（ALS）。

这篇文章将对这份指南的主要推荐意见进行总结和解读。

一、基础生命支持（BLS）1. 早期识别与早期要求呼叫急救：在遇到危机情况时，早期的识别和呼叫急救是关键。

推荐公众普及心脏病突发的症状和应急措施，提高大众对危机状况的识别能力。

2. 胸外按压（CPR）：推荐在胸外按压中使用手掌推压，并保持至少5厘米的深度。

在按压和换气之间的比例上，推荐30:2的频率。

3. 器械辅助按压：对于经过专业训练和有经验的医护人员，推荐使用器械辅助按压装置，以提供稳定且连贯的按压，增加胸外按压的质量。

4. 自动体外除颤器（AED）的使用：对于基础生命支持者来说，遇到心脏骤停的情况时，及时使用AED进行除颤是至关重要的。

二、高级生命支持（ALS）1. 早期高质量CPR：ALS提供者需要在提供早期高质量的CPR方面做到更好。

按压深度应达到至少5厘米，按压频率应保持在至少100次/分钟。

同时，避免无效的压力暂停，迅速进行质量评估和调整。

2. 药物治疗：除颤药物推荐使用肌内注射，而不是静脉注射。

并强调使用只有药物推荐作用的剂量，在心脏骤停后尽快进行除颤。

3. 除颤：对于室颤和无脉搏性室速，推荐尽快实施除颤。

尽量减少除颤时间，以提高患者的存活率。

4. 有选择性地使用复苏氧：在心肺复苏过程中，建议使用目标氧饱和度（SpO2）94％至99％的低浓度供氧策略。

只有当患者的SpO2低于94％时，才给予额外的氧气。

5. 血液循环药理学：在推荐的抗心律失常治疗过程中，强调评估胸外按压中的循环状态。

及时补液，维持有效的循环。

通过解读以上推荐意见，我们可以看到2020 AHA的心肺复苏指南在成人基础生命支持和高级生命支持方面给出了一系列具体的指导。

智能融合2多模式系统（MSS）外设DMA（PDMA）配置指南说明书

SmartFusion2 MSS Peripheral DMA (PDMA) ConfigurationSmartFusion2 MSS Peripheral DMA (PDMA) Configuration Table of ContentsConfiguration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A Product Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Configuration OptionsThe Peripheral DMA (PDMA) engine offloads the ARM® Cortex™-M3 processor from data movementtasks. The PDMA allows data transfer from various MSS peripherals to memory, memory to variousperipherals, and memory to memory. The data transfers can also be targeted to user logic/RAM in theFPGA fabric. For complete details please refer to the Microsemi SmartFusion2 User's Guide.Configuration OptionsUse Fabric to MSS DMAREADY_FIC_0 and/or DMAREADY_FIC_1 - The DMAREADY_FIC_0 andDMAREADY_FIC_1 signals correspond to the ready signals from a soft peripheral in the FPGA fabric -accessed respectively through the Fabric Interface Controller (FIC) 0 and 1. If the channel is configuredfor peripheral DMA and the direction is from the soft peripheral to memory, this signal indicates that datais available within the soft peripheral to be read out.If the channel is configured for peripheral DMA and the direction is from memory to the soft peripheral,this signal indicates that there is space within the soft peripheral for data to be written to it. Refer to theMicrosemi SmartFusion2 User's Guide for more details.You can enable the DMAREADY_FIC_0 and DMAREADY_FIC_1 signals in this configurator. The signalsare then available to be used in the design (Figure1).Figure 1 • MSS PDMA ConfiguratorA – Product SupportMicrosemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.Technical SupportVisit the Customer Support website (/soc/support/search/default.aspx) for moreinformation and support. Many answers available on the searchable web resource include diagrams,illustrations, and links to other resources on the website.WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at/soc.Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.The technical support email address is **********************.© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email (**********************) or contact a local sales office. Sales office listings can be found at /soc/company/contact/default.aspx.ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via ***************************. Alternatively, within My Cases , select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the I TAR web page.。

amba协议手册

AMBA协议手册一、AMBA概况AMBA（Advanced Microcontroller Bus Architecture）协议，又被称为AMBA 2.0，是一种针对高性能、高吞吐量嵌入式系统设计的总线协议。

它定义了在一个或多个嵌入式处理器和多个外设之间的高效通信方式，广泛应用于各类芯片和集成电路中。

AMBA为微控制器、数字信号处理器（DSP）以及通信和消费电子等多种应用提供了优秀的性能表现。

二、AMBA版本历史AMBA的发展经历了几个重要的版本，每个版本都增加了新的特性和功能。

1.AMBA 1.0：这个版本主要定义了简单的主从设备间的通信方式，包括数据传输和地址协议。

2.AMBA 2.0：在AMBA 2.0中，引入了更复杂的特性，如猝发传输和更高级的地址和数据传输控制。

3.AMBA 3.0：这个版本引入了新的特性，如外部总线的对齐和分区、扩展的地址空间和数据字节宽度的动态调整。

4.AMBA 4.0：随着芯片设计的不断发展和系统性能的持续提高，AMBA 4.0为高带宽总线传输和高频率时钟提供了支持。

三、AMBA组成部分AMBA协议主要包括以下组成部分：1.AXI（Advanced eXtensible Interface）：AXI是一种高性能、高吞吐量的总线接口，用于连接主设备和从设备。

它支持多个通道的数据传输，每个通道都有数据写和数据读两个通道。

2.ACE（Advanced Coherency Enhanced）：ACE是AMBA的一种扩展，提供了更高级的内存一致性保证，确保在多处理器系统中数据的一致性。

3.APB（Advanced Peripheral Bus）：APB是一种简单、低速的总线接口，主要用于连接低速外设。

它基于传统的Peripheral Bus，但提供了更高的性能和更小的芯片面积。

4.AHB（Advanced High-performance Bus）：AHB是一种高性能的总线接口，主要用于连接高性能的处理器和高速存储器。

Futaba SBS-01S Servo Sensor 说明书

LED IndicationConnection ExampleThank you for purchasing Futaba's SBS-01S Servo Sensor. Please read this manual thoroughly to ensure proper servo sensor performance. We also encourage you to retain the manual for future reference.OKTelemetry ReceiverS.BUS2 ServoThe SBS-01S can monitor and display the in-flight current, operating angle, and internal temperature of up to two S.BUS2 servos.●Servo connection alarm：If you forget to connect the servo wiring during fuselage assembly, or the servo was disconnected, an alarm can be activated at the transmitter.(The “Servo connection alarm” function of the transmitter must be enabled.)●Servo alarm：If you forget to turn off the receiver power, you are informed by the sounding of an alarm from the servo. This servo alarm sound is also useful when searching for lost aircraft.(The “buzzer” function of the S.BUS2 s e r v o c o n n e c te d t o th e SB S-01S is automatically turned on.)Telemetry LogA log file for each servo, as well as data acquired by the SBS-01S, can be created when the transmitter has a telemetry function. The log file can be converted to a CSV file by using the “Telemetry log converter”. The “Telemetry log converter” must be downloaded from the web. Check the Futaba website .The data of servo 1 and servo 2 is Incompatible with servos other than the S-BUS2.The SBS-01S cannot be used with S-BUS2 760µs neutral servos.*The SBS-01S cannot be used with a servo connected to a gyro. Do not connect it to a servo connected to a gyro.*The temperature on some S.BUS2 servos can not be checked. Check the Futaba website for details.。

智能融合2多核系统控制器时钟配置指南说明书

SmartFusion2 MSS Clocks ConfigurationTable of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51System Clocks Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MSS CCC Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Cortex-M3 and MSS Main Clock (M3_CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MDDR Clocks (MDDR_CLK and DDR_SMC_FIC_CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MSS APB_0 and APB_1 Sub-busses Clocks (APB_0_PCLK and APB_1_PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 7 FPGA Fabric Interface Clocks (FIC_0_CLK and FIC_1_CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PLL Lock(s) Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9A Product Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IntroductionThe MSS Clock Conditioning Circuitry (MSS CCC) provides a single place where all clocks related to the MSS and the communication between the MSS and the FPGA fabric can be configured.The MSS_CCC configurator is organized into tabs: System Clocks and Advanced Options (Figure 1).System ClocksThe System Clocks tab (Figure 2) enables you to configure/view:•The MSS CCC clock source CLK_BASE. The Configurator computes the frequency for you based on how the other clocks are configured.•The main MSS clock M3_CLK–Enter a value below 167 MHz to drive the Cortex-M3 Processor.–This is a limitation of the Cortex-M3.•The MDDR related clocks (MDDR_CLK and DDR_SMC_FIC_CLK)–MDDR_CLK and DDR_SMC_FIC_CLK must be between 20 MHz and 334 MHz.•The MSS APB_0 and APB_1 Peripheral clocks (APB_0_CLK and APB_1_CLK)–Choose a divisor of 1, 2, 4 or 8 to divide into the M3_CLK frequency to get the APB_0_CLK and APB_1_CLK frequency you want.•The two Fabric Interface (FIC) clocks (FIC_0_CLK and FIC_1_CLK)–Choose a divisor of 1, 2, 4, 8, 16 or 32 to divide into the M3_CLK frequency to get theFIC_0_CLK and FIC_1_CLK frequency you want.Figure 1 •MSS CCC ConfiguratorOnly the clocks used in your design are editable for configuration in the MSS CCC configurator. Make sure to enable and correctly configure all the MSS sub-blocks you intend to use in your design beforeconfiguring the MSS CCC sub-block. What can be configured and how (rules) depends on what is being used; see "System Clocks Configuration" on page 6 for details.The System Clocks tab displays a high level block diagram of your design displayed based on what you have enabled/disabled/configured in the MSS configurator. The block diagram shows the different clock domains (each clock domain is a different color) within the MSS as well as the clock domains that cross into the FPGA fabric. If you click any of the clocks (blue labels) you will see that particular clock domainFigure 2 •System Clocks Tabhighlighted on the block diagram Figure 3 shows the M3_CLK clock domain highlighted. It shows what components this clock is driving.Advanced OptionsYou can also configure more advanced options related to the PLL LOCKs using the Advanced tab. See "Advanced Options" on page 9 for a summary.Figure 3 •M3_CLK Domain Highlighted1 – System Clocks ConfigurationThe System Clocks tab (Figure 1-1) enables you to configure:•The MSS CCC clock source CLK_BASE •The main MSS clock M3_CLK •The MDDR related clocks (MDDR_CLK and DDR_SMC_FIC_CLK)•The MSS APB_0 and APB_1 Peripheral clocks (APB_0_CLK and APB_1_CLK)•The two Fabric Interface (FIC) clocks (FIC_0_CLK and FIC_1_CLK)MSS CCC Clock SourceIn normal operating mode (non Flash*Freeze) the MSS CCC is configured to be sourced from the FPGA fabric via the CLK_BASE port.If you use any of the FIC clocks (DDR_SMC_FIC_CLK, FIC_0_CLK and FIC_1_CLK), CLK_BASE is automatically set at the lowest frequency of any of the used FIC clocks and is not editable. In this case, when MSS outputs and inputs are to/from the fabric, the MSS I/Os are synchronous to CLK_BASE. For a more comprehensive system level view of the clocking methodology for interfacing the MSS and the FPGA fabric through the MSS FICs, refer to the SmartFusion2 MSS Creating a Design using MSS Fabric Interfaces document.If none of the FIC clocks are used, the CLK_BASE frequency is editable and you can select a clock frequency between 1 MHz and 200 MHz. In this case, the MSS I/Os are asynchronous.If CLK_BASE is sourced by a PLL in the FPGA fabric, you should connect the PLL LOCK signal from that fabric CCC to the MSS CLK_BASE_PLL_LOCK. When the chip system controller boots the device (atFigure 1-1 •System Clocks Configuration TabPoR or when the external pin DEVRST_N has been asserted/de-asserted) it monitors the external PLLLOCK as well as the internal MPLL LOCK and only switches to the clock configurations defined in thisconfigurator when the PLL have a stable lock.Cortex-M3 and MSS Main Clock (M3_CLK)The main clock for the Cortex-M3 and the MSS is M3_CLK; you must define its frequency.The following rules must be satisfied and are checked by the MSS_CCC configurator as you enter afrequency for M3_CLK:1.The M3_CLK frequency must be less than or equal to 167 MHz.2.The MDDR_CLK frequency must be less than or equal to 333 MHz.3.If the CAN peripheral is used M3_CLK must be a multiple of 8 MHz.4.If the USB peripheral is used M3_CLK must be greater than 30.1 MHZ.MDDR Clocks (MDDR_CLK and DDR_SMC_FIC_CLK)When the MDDR sub-block is configured as a DDR interface:•The MDDR_CLK drives the DDR controller and the DDR Bridge in the MSS. You can select this clock to be a multiple - 1, 2, 3, 4, 6 or 8 - of the main MSS clock M3_CLK.•The DDR_SMC_FIC_CLK drives the DDR FIC slave interface and defines the frequency at which the FPGA fabric sub-system connected to this interface is intended to run. You can select thisclock to be a ratio - 1, 2, 3, 4, 6, 8, 12, or 16 - of MDDR_CLK. To enable this, you need to enableFabric Interface Settings (i.e., FIC64) in the MDDR configurator.•If MDDR_CLK ratio to M3_CLK is a multiple of 3, DDR_SMC_FIC_CLK's ratio to MDDR_CLK must also be a multiple of 3, and vice versa. The configurator issues an error if this requirement isnot met. This limitation is imposed by the internal implementation of the MSS CCC.When the MDDR sub-block is configured as a Soft Memory Controller (SMC) interface:•The MDDR_CLK drives the DDR Bridge in the MSS. It is automatically set by the configurator to be equal to M3_CLK and is not editable.•The DDR_SMC_FIC_CLK drives the SMC master fabric interface. It is automatically set by the configurator to be equal to M3_CLK and is not editable.MSS APB_0 and APB_1 Sub-busses Clocks (APB_0_PCLK and APB_1_PCLK)There are two internal APB sub-busses in the MSS: APB_0 and APB_1. Each of these sub-bussesperipheral is clocked by APB_0_CLK and APB_1_CLK, respectively. These clocks are derived from themain MSS clock M3_CLK. Each APB clock can be programmed individually as M3_CLK divided by 1, 2,4 or 8.Note:Some peripherals may require a slower Peripheral clock (PCLK) to achieve certain configurations.Changing the APB sub-bus PCLK affects all peripherals present on that bus.FPGA Fabric Interface Clocks (FIC_0_CLK and FIC_1_CLK) For applications where the AMBA fabric Interface is used to connect to a soft AMBA sub-system (softbus/bridge/peripheral cores), the FIC sub-system clocks (FIC_0_CLK and FIC_1_CLK) must beconfigured such that the generated frequencies meet the timing requirements of the FPGA logicimplemented in the fabric for each FIC sub-system.The FPGA fabric clocks, when used, can only be the MSS clock divided by 1, 2, 4, 8, 16 or 32. You mustverify that the FPGA fabric timing for each FIC sub-system meets the selected fabric clock frequency byperforming timing analysis of your design using SmartTime.For a more comprehensive system level view of the clocking methodology for interfacing the MSS and the FPGA fabric through the MSS FICs, refer to the SmartFusion2 MSS Creating a Design Using MSSFabric Interfaces document.2 – Advanced OptionsThe Advanced Options tab enables you to configure Advanced PLL Lock Options:PLL Lock(s) Advanced OptionsLock Count (Delay) - Sets the number of CLK_BASE (reference clock) clock cycles by which the lock is delayed after the MPLL has reached the lock condition. The default value is 32.Lock Window (ppm) - Configures the maximum phase error allowed for the MPLL to indicate it has locked. The lock window is expressed as parts per million (ppm) of the reference frequency. The default value is 8,000.You can enable interrupts to the Cortex-M3 to monitor assertions and de-assertions of the MPLL lock.You can expose the MPLL LOCK signal to the FPGA fabric and use it as part of your design to monitor the health of the MPLL (loss or lock may require special handling by your application).You can enable interrupts to the Cortex-M3 to monitor assertions and de-assertions of the CLK_BASE PLL lock if you are monitoring this signal by checking the Monitor FPGA Fabric PLL Lock (CLK_BASE_PLL_LOCK) checkbox (Figure 3).Figure 2-1 •Advanced Options Configuration TabA – Product SupportMicrosemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 650.318.8044Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.Technical SupportFor Microsemi SoC Products Support, visit /products/fpga-soc/design-support/fpga-soc-support.WebsiteYou can browse a variety of technical and non-technical information on the Microsemi SoC ProductsGroup home page, at /soc.Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.The technical support email address is **********************.5-02-00338-2.0/03.19Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.About Microsemi Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; Enterprise Storage and Communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 4,800employees globally. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail:***************************©2019 Microsemi Corporation. All rightsreserved. Microsemi and the Microsemilogo are trademarks of MicrosemiCorporation. All other trademarks andservice marks are the property of theirrespective owners.My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email (**********************) or contact a local sales office.Visit About Us for sales office listings and corporate contacts .Sales office listings can be found at /soc/company/contact/default.aspx.ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via ***************************. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.。