Cadenc版图验证Assura使用

Assura DRC – Assura DRC (Design Rule Checking) checks the layout against geometric spacing, width, and other rules. Typical checks include material spacing, enclosure, coverage, and overlap. Assura DRC displays design rule violations graphically as an additional graphics layer on the layout,and lists them in text files.
Assura RCX – Assura RCX (Resistance, Capacitance and Inductance Extraction) extracts parasitic resistance, capacitance, and inductance from the layout for analysis and input to post-layout simulators.
The Assura RSF contains a mandatory avParameters section that specifies the input layout and rules file associated with the Assura run, plus various global RSF options. Below is an example of an avParameters section.
Cadence 后端实验系列19_版图验证_ Assura
Introduction to Assura Physical Verification
• Assura Physical Verification Tool Suite • Assura Task and Data Flow • Assura Input Files • Running Assura
• Alternatively you can create your own RSF. You can specify the RSF file name in the GUI run form, or you can specify the RSF file name on the command line if you run an Assura tool in batch mode.
The RSF contains one or more avCompareRules sections if the RSF is for an Assura LVS run. The avCompareRules section Specifies the input schematic, an optional binding file for mapping layout device and net names to schematic names, and other rules and options.
avParameters( ?workingDirectory "/usr1/drc/“ ?runName "peakDetect" ?inputLayout ( "df2" "design" ) ?cellName "peakDetect" ?technology “gold“ ?techLib "/usr1/amancuso/rcx/assura_tech.lib“ )
?subNodeChar "#" ?outputNetNameSpace "schematic" ?parasiticCapModels "yes" ?capModels "no" ?hierarchyDelimiter "/" ?resModels "no" )
You can place optional statements in the RSF outside an avParameters, avCompareRules or rcxParameters section. These statements include several Assura rules that can optionally be placed in an RSF, usersupplied SKILL functions, and Assura tool invocation commands.
• When you use the Assura Graphical User Interface (GUI), the GUI creates the RSF for you using the settings you specified in the forms, and invokes an Assura tool using this RSF.
RCX Graphical User Interface Run Guide
Demonstration
The Assura verification suite is optimized for large, hierarchical, repetitive designs such as memory, microprocessor, and mixed-signal circuits. The software upholds the Cadence verification tradition of accuracy established by its Dracula® and Diva® products. The Assura tools ensure accuracy and leverage the layout hierarchy of leading-edge designs to provide faster physical verification runtimes.
• Assura Physical Verification Tool Suite • Assura Task and Data Flow • Assura Input Files • Running Assura
DRC Graphical User Interface Run Guide
LVS Graphical User Interface Run Guide
The Assura RSF consists of several sections: • A mandatory avParameters section • One or more avCompareRules sections for an LVS run • An rcxParameters section for an RCX run • Optional statements outside the above sections • One or more mandatory Assura tool invocation commands
Schematic Netlists
Layout Geometry
Data
RunSpecific File (RSF)
Rule File
• The Assura RSF is a required control file in text format that directs the Assura DRC, LVS, or RCX run. It specifies input data files, rule files, run-specific options, and commands to invoke the tool. The Assura RSF follows Cadence SKILL language syntax. Options in an RSF are specified as parameters, which begin with a “?” followed by a keyword.
The Assura RSF must end with one or more Assura tool invocation commands that launch the appropriate verification tasks.
When an Assura tool is run from the GUI, the appropriate invocation command is placed at the end of the RSF.
avCompareRules( schematic( netlist( dfII “netlist.dfII” )) bindingFile(“bindings”) mergeSplitGate( mergeAll ) showErrorNetwork() compareParameter(MOS percent(“w” 5 “l” 5)) compareParameter("res_poly" percent("r" 5)) compareParameter("res_nwell" percent("r"10)) )
Assura LVS – Assura LVS (Layout Versus Schematic) comparison extracts devices and connectivity from the layout according to device extraction rules, then creates a layout netlist according to netlist rules, then finally compares the layout netlist to the schematic netlist according to comparison rules. Assura LVS displays mismatches between the layout and the schematic both textually and graphically.