多核课件

Dynamic Scheduling
Dynamic scheduling provides a means for independent instructions to circumvent previous stalled instructions and, therefore, execute outof-order. Out-of-order execution allows useful work to be overlapped with the load-use stalls
Dynamic Scheduling
The key mechanism for out-of-order execution is a pool of instruction buffers that decouples the instruction fetch/decode stages from later execution stages These instruction buffers, collectively called the scheduling window or instruction window, provide a staging area in which instructions wait for their source operands to become available.
Multi-Core
第二节 共享存储器多处理机系统
多核处理器系统
系统中包含一个多核的处理器芯片 每个处理器核能够独立运行程序
单核多处理器系统
多个单核的处理器构成的系统 处理器之间的通信延迟时间较长
多核多处理器系统
多个多核处理器构成的并行系统 两个并行处理的层次
多处理机系统的结构分类
按程序特征
MIMD SPMD
Dynamic Scheduling
The benefit of dynamic scheduling is evident by comparing in-order and outof-order execution in the presence of a cache miss, as shown in Figures
Deeper Pipelining
Deeper Pipelining
However, in practice, doubling pipeline depth does not double performance because there are relatively more stall cycles that need to be tolerated. A larger instruction window is needed to hide lengthier stalls due to data hazards (for example, data cache misses take more cycles to resolve since memory access time in nanoseconds is unchanged). A more accurate branch predictor is needed because the branch misprediction penalty is larger (more stages between IF and EX).
MutliMutli-core Memory Hierarchy
多核处理器的分类
CU
EU
CU
EU Cache
CU
Cache
单核单线程处理器
单核多线程处理器
CU
EU
CU
EU
CU
EU Cache
CU
CU
EU Cache
CU
Cache
Cache
多核处理器
多核多线程处理器
CU: CPU state + Interrupt logic
Dynamic Scheduling
Dynamic scheduling adds another stage to the pipeline between decode (ID) and execute (EX), here called IS for instruction schedule.
early forms of hardware multithreading
instructions are fetched from a different thread each cycle
Simultaneous multithreading
Simultaneous multithreading (SMT) is even more flexible: a single pipeline stage may mix instructions from multiple threads during the same cycle
多核处理机
CU
EU
CU
EU
CU
EU
CU
EU
Cache
共享存储器
单核多处理机系统
CU
EU
CU
EULeabharlann CUEUCache
Cache
Cache
互连网络
共享存储器
多核多处理机系统
CU EU CU EU CU EU CU EU CU EU CU EU CU EU CU EU CU EU Cache CU EU CU EU CU EU CU EU Cache CU EU CU EU CU EU Cache Cache
superscalar processing
An alternative to deeper pipelining is to fetch, issue, and execute multiple instructions in parallel each cycle, exceeding the scalar bottleneck explicitly. This approach is called, appropriately, superscalar processing. A dual-issue superscalar processor doubles the peak execution rate with respect to the original scalar pipeline
superscalar processing
Hardware multithreading
Hardware multithreading is a means for improving pipeline utilization when bottlenecks prevent further speedup of single-threaded programs. It enables the simultaneous execution of multiple independent programs on the same pipeline. Independent programs are an abundant source of instruction-level parallelism, since there are no dependences between instructions from different threads. Hardware multithreading improves pipeline utilization by converting thread-level parallelism to instruction-level parallelism
互连网络
共享存储器
Deeper Pipelining
One way to improve performance further is to deepen the scalar pipeline. a pipeline twice as deep as the original pipeline is capable of twice the peak execution rate. Once the deep pipeline is filled, two new instructions are completed every original cycle.
多核处理器
Evolvement of computer architecture
scalar seque nce I/E overlap Multi fun Pseudo-vector m-m SIMD Ledgend processor Multiprocessing array Multicomputer Preexe Fun parallel Pipe line Obvious vector r-r MIMD multiprocesin g
代替SIMD
CPU CPU
… CPU
按处理机特征
同构homogenius 异构heterogenius
互连网络 M M … M
核
独立的指令执行和控制单元
独立的功能部件 独立的控制器
完整的指令流水线
多核处理器分类
单核多线程处理器
单核CPU构成
多核处理器
多核芯片构成
多核多线程处理器
每个核都是多线程的