USB_3_1连接器协会规范

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USB3.0协会标准

USB3.0相关技术规范1：USB3.0标准技术规范于2008年11月12日正式发行，版本为1.0，起草单位主要有惠普、因特尔、微软、NEC、ST-NXP半导体、德州仪器等公司。

2：USB3.0架构综述，Superspeed USB与USB2.0对比：特性 Superspeed USB USB2.0数据速率 Superspeed(5.0 Gb/s) Low-speed(1.5Mb/s),full-speed(12Mb/s), and high-speed(480 Mb/s)数据界面双向-单一，四线差动信号从USB2.0信号分离单工传输，整体成全双工传输。

半双工双线差动信号单向数据传输（越过定向总线转移）。

Cable信号计算 6根:Superspeed 数据路径4根；Non-Superspeed 数据路径2根。

2根:low-speed/full-speed/high-speed数据路径。

总线传输协议由主机指向，异步通信流向压缩包通信是被明确程序规定的。

由主机指向，polled通信流向压缩包通信被传送到所有的驱动设备里。

负载管控多级别链接负载管控支持空转，睡眠及延缓状态；链接-，驱动设备-，功能级别级别负载管控。

端口级别随着输入/输出两种级别潜在而延缓；驱动设备-级别负载管控。

总线负载与USB2.0相同，无限制负载提升50%，而限制负载提升80%。

为低速/高速总线-负载驱动设备和低负载限制(无限制和延缓型驱动设备)提供支持。

端口状况端口硬件探测连接活动且带动端口进入工作状态做准备(为超速数据交换)。

端口硬件探测连接活动,系统软件利用端口命令跃迁使端口进入激活状态。

数据传输类型 USB2.0类型高速压缩，四种数据传输类型：控制，Bulk,中断，同步3：USB3.0具备以下主要优势：① 支持5Gb/s的传输速率；② 向上全面兼容USB2.0；③ 连接器形式变异因素降到最小；④ 为电磁干扰（EMI）提供保护；⑤ 支持OTG（On-The-Go）；⑥ 成本低。

USB3.0协会标准

半双工双线差动信号单向数据传输（越过定向总线转移）。

Cable信号计算 6根:Superspeed 数据路径4根；Non-Superspeed 数据路径2根。

2根:low-speed/full-speed/high-speed数据路径。

总线传输协议由主机指向，异步通信流向压缩包通信是被明确程序规定的。

由主机指向，polled通信流向压缩包通信被传送到所有的驱动设备里。

负载管控多级别链接负载管控支持空转，睡眠及延缓状态；链接-，驱动设备-，功能级别级别负载管控。

端口级别随着输入/输出两种级别潜在而延缓；驱动设备-级别负载管控。

总线负载与USB2.0相同，无限制负载提升50%，而限制负载提升80%。

为低速/高速总线-负载驱动设备和低负载限制(无限制和延缓型驱动设备)提供支持。

端口状况端口硬件探测连接活动且带动端口进入工作状态做准备(为超速数据交换)。

端口硬件探测连接活动,系统软件利用端口命令跃迁使端口进入激活状态。

(仅供参考)USB Type-C 3.1协会规范

Figure 3-1 USB Type-C Receptacle Interface DimensionsFigure 3-1 USB Type-C Receptacle Interface Dimensions, cont.Figure 3-2 Reference Design USB Type-C Plug External EMC Spring Contact ZonesFigure 3-3 USB Full-Featured Type-C Plug Interface DimensionsFigure 3-4 Reference Footprint for a USB Type-C Vertical Mount Receptacle(Informative)Figure 3-5 Reference Footprint for a USB Type-C Dual-Row SMT Right AngleReceptacle (Informative)Figure 3-6 Reference Footprint for a USB Type-C Hybrid Right-Angle Receptacle(Informative)Figure 3-7 Reference Footprint for a USB Type-C Mid-Mount Dual-Row SMT Receptacle(Informative)Figure 3-8 Reference Footprint for a USB Type-C Mid-Mount Hybrid Receptacle(Informative)This specification requires that all contacts be present in the mating interface of the USB Type-C receptacle connector, but allows the plug to include only the contacts required for USB PD and USB 2.0 functionality for applications that only support USB 2.0. The USB 2.0 Type-C plug is shown in Figure 3-9. The following design simplifications may be made when only USB 2.0 is supported:∙Only the contacts necessary to support USB PD and USB 2.0 are required in the plug.All other pin locations may be unpopulated. See Table 3-5. All contacts are required to be present in the mating interface of the USB Type-C receptacle connector.∙Unlike the USB Full-Featured Type-C plug, the internal EMC springs may be formed from the same strip as the signal, power, and ground contacts. The internal EMC springs contact the inner surface of the plug shell and mate with the receptacle EMC pads when the plug is seated in the receptacle.∙ A paddle card inside the plug may not be necessary if wires are directly attac hed to the contact pins.Figure 3-9 USB 2.0 Type-C Plug Interface Dimensions3.2.2Reference DesignsThis section provides reference designs for a few key features of the USB Type-C connector. The reference designs are provided as acceptable design examples. They are not normative.3.2.2.1Receptacle Mid-Plate (Informative)The signals between the top and bottom of the receptacle tongue are isolated by a mid-plate inside the tongue. Figure 3-10 shows a reference design of the mid-plate. It is important to pay attention to the following features of the middle plate:∙The distance between the signal contacts and the mid-plate should be accurately controlled since the variation of this distance may significantly impact impedance of the connector.∙The mid-plate in this particular design protrudes slightly beyond the front surface of the tongue. This is to protect the tongue front surface from damage caused by miss-insertion of small objects into the receptacle.∙The mid-plate is required to be directly connected to the PCB ground with at least two grounding points.∙The sides of the mid-plate mate with the plug side latches, making ground connections to reduce EMC. Proper surface finishes are necessary in the areaswhere the side latches and mid-plate connections occur.Figure 3-10 Reference Design of Receptacle Mid-Plate3.2.2.2Side Latch (informative)The side latches (retention latches) are located in the plug. Figure 3-11 shows a reference design of a blanked side latch. The plug side latches should contact the receptacle mid-plate to provide an additional ground return path.Figure 3-11 Reference Design of the Retention LatchFigure 3-12 Illustration of the Latch Soldered to the Paddle Card Ground3.2.2.3Internal EMI Springs and Pads (Informative)Figure 3-13 is a reference design of the internal EMC spring located inside the USB Full-Featured Type-C plug. Figure 3-14 is a reference design of the internal EMC spring located inside the USB 2.0 Type-C plug.Figure 3-13 Reference Design of the USB Full-Featured Type-C Plug Internal EMCSpringFigure 3-14 Reference Design of the USB 2.0 Type-C Plug Internal EMC SpringIt is critical that the internal EMC spring contacts the plug shell as close to the EMC spring mating interface as possible to minimize the length of the return path.The internal EMC pad (i.e., ground plate) shown in Figure 3-15 is inside the receptacle. It mates with the EMC spring in the plug. To provide an effective ground return, the EMC pads should have multiple connections with the receptacle shell.Figure 3-15 Reference Design of Internal EMC Pad3.2.2.4Optional External Receptacle EMC Springs (Informative)Some applications may use receptacles with EMC springs that contact the outside of the plug shell. Figure 3-16 shows a reference receptacle design with external EMC springs. The EMC spring contact landing zones for the fully mated condition are normative and defined in Section 3.2.1.Figure 3-16 Reference Design of a USB Type-C Receptacle with External EMC Springs。

usb,type,c,协会规范

竭诚为您提供优质文档/双击可除usb,type,c,协会规范篇一：usb3.1type-c公对公接点图usb3.1（type-c）接点图usb3.1type-c公对公接点图pin的四种类型：1、usb3.1中Rx、tx为高速pin；2、usb2.0数据pin；3、边频带信号pin；4、电源及地线pin.图表中a6，a7为usb2.0的数据pin；a8，b8为预留pin；a5，b5为配置通道或有源器件电源；配置通道的功能：1、探测usbtypec连接器端口是否插配，从而决定如何配置电源的供应；2、探测usbtypec公头连接器的方向性，从而决定采用哪侧的高速信号pin组传输信号；3、建立连接的主从关系；4、探测连接的额电流水平/大小，控制或配置电源的供应水平；5、usbpd通讯；6、给有源器件供应电源；7、功能延伸。

usbtypec连接器-公头设计指南：使用高性能的pcb基板材料。

推荐pcb厚度应该有一个公差小于或等于±10%的usb插针间距；篇二：typec数据线规格书typec数据线规格书V1.0关键词：typec、数据线摘要：本文介绍了数据线的规格，性能及测试规范。

缩略语：1范围标准适用于typeatoc数据线需求规格书，未尽规格描述以typec协会规范V1.1为准。

2编写依据3数据线正常工作和存储条件3.1数据线应能在下列条件下正常工作：3.1.1工作环境温度：-20℃～+55℃；（仅作单体验证目的，与整机匹配时以整机试验环境为准）；3.1.2相对湿度：5%～95%；3.1.3大气压力：86kpa～106kpa;3.1.4数据线的存储温度：-40℃～+85℃；4数据线主要参数4.1数据线连线规格详细尺寸以及工艺要求以3d图档为准1、typec金属插头，要求必须是整体拉伸成型，不能是折弯成型，不接受接缝；2、金属插头部分，要求做不锈钢原色，表面喷砂处理:50u”~150u”mattnickelplatingoVeRall3、保证至少3a通流能力整条线缆产品详细规格（bom清单,包括端子图纸2d&可拆解版本的3d）要有确认才能认可(认证时必须提供以上文件)。

USB全规范详细分析(技术篇)

USB全规范详细分析（技术篇）USB规格设计上面说的那些只是很表面的东西，接下来的就是技术知识深一点的了，大家做好心理准备喔。

USB规格的规范化建立USB规格的厂商们，共同设立了一个称为"USB应用者论坛（USB Implementers Forum Inc，USB-IF）"的非营利组织。

USB-IF是一个技术支持组织，也是接受各界对USB研发与应用建议的论坛。

这个论坛促进了高品质并具兼容性USB设备的研发，以及通过规格测试的产品的推广。

符合USB 1.1规范的标志符合USB 2.0规范的标志和其它业界规格（像是IEEE 1394、DTS、WiFi、Dolby或是DVD等）一样，USB 1.0和USB 2.0都有正式的标示。

厂商将这些标示印在产品与包装上，以代表他们的产品是遵照这些规格设计的。

这些标示确保了兼容性，并且代表产品经过测试。

产品上高速USB 2.0规格的标示，代表它能够与其它同样有高速USB 2.0规格标示的外设一起正常使用。

如果一项产品没有这项标示，却还是声称具有兼容性，那就不能保证能和其它USB 2.0一起使用了。

为了顾及到兼容性，建议您只购买通过认证的USB设备。

一家厂商的产品要能够标上高速USB 2.0规格的标示，那得先成为USB-IF的付费会员（年费2500美元），而且该产品也需要通过由USB-IF所制定的全速与低速测试程序才行。

测试的目的，是要来检验在全速与低速模式下，这些准备出货的产品的USB功能是否能够正常运作。

详细的测试步骤分成三大项，每一大项的产品都需要分别通过属于该大项的测试步骤.接口卡、主板和计算机系统o 电源提供测试（Power Provider testing）o 传出信号品质（Downstream Signal Quality）o 互通性（Interoperability）" 全速与低速集线器（不含高速支持）o 电源提供测试（Power Provider testing）o 传出信号品质（Downstream Signal Quality）o 回传信号品质（Upstream Signal Quality）o 设备架构测试（Device Framework Testing）o 互通性（Interoperability）o 平均电流消费（Average Current Consumption）" 全速与低速外设o 回传信号品质（Upstream Signal Quality）o 设备架构测试（Device Framework Testing）o 互通性（Interoperability）o 平均电流消费（Average Current Consumption）在设计USB 2.0这样高速的设备时，设计者尤其要注意到设备封装（Device Packaging）、电路板设计（Board Layout）、机身接地（Chassis Grounding）、布线设计（Trace Layout），防治电磁干扰（EMI Remediation）、以及资料信号衰减噪声（Data Signal Attenuation/ Jitter）等问题。

usb规范

usb规范USB (Universal Serial Bus)是一种常见的数据传输和电源连接接口，被广泛应用于个人电脑、移动设备和其他电子产品中。

USB规范定义了USB接口的物理和电气特性，以确保不同设备之间的兼容性和互操作性。

下面将详细介绍USB规范的特点和应用。

首先，USB规范包括了多个版本，常见的有USB1.0、USB2.0、USB3.0和USB4.0等。

每个版本都有不同的传输速度和功能特性。

USB1.0提供了最初的传输速度，USB2.0提供了更快的传输速度和更多的功能，USB3.0则具有更高的传输速度和更好的能源管理能力，USB4.0进一步提升了传输速度和可用带宽。

不同版本的USB接口可以向下兼容，这意味着使用较新版本的USB设备可以与较旧版本的USB主机和设备进行通信。

其次，USB规范定义了USB接口的物理特性，包括连接器形状和尺寸。

常见的USB连接器有Type-A、Type-B、Micro-USB和USB-C等。

USB Type-A连接器用于主机和大多数外部设备，Type-B连接器用于一些较大外部设备和打印机等设备。

Micro-USB连接器用于一些移动设备和无线耳机等小型设备，而USB-C连接器则是一种通用连接器，广泛应用于个人电脑、手机和平板电脑等设备。

其次，USB规范还定义了USB接口的电气特性，包括电压和电流等参数。

USB接口通常以5伏特的直流电供电，提供最高500毫安的电流。

此外，USB接口还支持热插拔功能，这意味着可以在设备工作时插拔USB设备而无需重新启动系统。

此外，USB规范还定义了USB接口的数据传输方式，即通过USB传输的数据帧格式和协议。

USB接口支持全双工通信，即可以同时进行发送和接收数据。

USB的传输速度是根据其版本和传输模式来确定的。

例如，USB3.0支持超高速传输模式，最高传输速度可达到5 Gbps，而USB4.0的传输速度进一步提升到20 Gbps。

USB接口的应用非常广泛。

USB接口规范(含USB3.0和OTG)

USBUSB ,是英文Universal Serial BUS（通用串行总线）的缩写，而其中文简称为“通串线，是一个外部总线标准，用于规范电脑与外部设备的连接和通讯.是应用在PC领域的接口技术。

USB接口支持设备的即插即用和热插拔功能.USB是在1994年底由英特尔、康柏、IB M、Microsoft等多家公司联合提出的。

简述不过直到近期，它才得到广泛地应用。

从1994年11月11日发表了USB V0。

7版本以后,USB版本经历了多年的发展，到现在已经发展为3.0版本,成为目前电脑中的标准扩展接口.目前主板中主要是采用USB1.1和USB2。

0,各USB版本间能很好的兼容。

USB用一个4针（USB3.0标准为8针）插头作为标准插头，采用菊花链形式可以把所有的外设连接起来，最多可以连接127个外部设备，并且不会损失带宽。

USB需要主机硬件、操作系统和外设三个方面的支持才能工作。

目前的主板一般都采用支持USB功能的控制芯片组，主板上也安装有USB接口插座，而且除了背板的插座之外，主板上还预留有USB插针,可以通过连线接到机箱前面作为前置USB接口以方便使用（注意，在接线时要仔细阅读主板说明书并按图连接,千万不可接错而使设备损坏）。

而且USB接口还可以通过专门的USB连机线实现双机互连，并可以通过Hub扩展出更多的接口.USB具有传输速度快（USB1。

1是12Mbps,USB2。

0是480Mbps，USB3。

0是5 Gbps），使用方便，支持热插拔,连接灵活，独立供电等优点，可以连接鼠标、键盘、打印机、扫描仪、摄像头、闪存盘、MP3机、手机、数码相机、移动硬盘、外置光软驱、USB网卡、ADSL Modem、Cable Modem等，几乎所有的外部设备。

USB接口可用于连接多达127个外设，如鼠标、调制解调器和键盘等。

USB自从1996年推出后，已成功替代串口和并口,并成为当今个人电脑和大量智能设备的必配的接口之一。

USB 协会标准

半双工双线差动信号单向数据传输（越过定向总线转移）。

Cable信号计算 6根:Superspeed 数据路径4根；Non-Superspeed 数据路径2根。

2根:low-speed/full-speed/high-speed数据路径。

总线传输协议由主机指向，异步通信流向压缩包通信是被明确程序规定的。

由主机指向，polled通信流向压缩包通信被传送到所有的驱动设备里。

负载管控多级别链接负载管控支持空转，睡眠及延缓状态；链接-，驱动设备-，功能级别级别负载管控。

端口级别随着输入/输出两种级别潜在而延缓；驱动设备-级别负载管控。

总线负载与USB2.0相同，无限制负载提升50%，而限制负载提升80%。

为低速/高速总线-负载驱动设备和低负载限制(无限制和延缓型驱动设备)提供支持。

端口状况端口硬件探测连接活动且带动端口进入工作状态做准备(为超速数据交换)。

端口硬件探测连接活动,系统软件利用端口命令跃迁使端口进入激活状态。

USB3.1 Type C 认证规范 USB-Port Controller Specification R1.0 [21051020] (1)

Universal Serial Bus Type-C TM Port Controller Interface SpecificationRevision 1.0October 20, 2015Copyright © 2015, USB 3.0 Promoter Group:Hewlett-Packard Company, Intel Corporation, Microsoft Corporation, Renesas, STMicroelectronics, and Texas InstrumentsAll rights reserved.LIMITED COPYRIGHT LICENSE: The USB 3.0 Promoters grant a conditional copyright license under the copyrights embodied in the USB Type-C Cable and Connector Specification to use and reproduce the Specification for the sole purpose of, and solely to the extent necessary for, evaluating whether to implement the Specification in products that would comply with the specification. Without limiting the foregoing, use of the Specification for the purpose of filing or modifying any patent application to target the Specification or USB compliant products is not authorized. Except for this express copyright license, no other rights or licenses are granted, including without limitation any patent licenses. In order to obtain any additional intellectual property licenses or licensing commitments associated with the Specification a party must execute the USB 3.0 Adopters Agreement. NOTE: By using the Specification, you accept these license terms on your own behalf and, in the case where you are doing this as an employee, on behalf of your employer.INTELLECTUAL PROPERTY DISCLAIMERTHIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.All implementation examples and reference designs contained within this Specification are included as part of the limited patent license for those companies that execute the USB 3.0 Adopters Agreement.All product names are trademarks, registered trademarks, or service marks of their respective owners.CONTENTSSpecification Work Group Chairs / Specification Editors (7)Specification Work Group Contributors (7)Revision History (9)1Introduction (10)1.1Purpose (10)1.2Scope (10)1.3Related Documents (11)1.4Conventions (11)1.4.1Precedence (11)1.4.2Keywords (11)1.4.3Numbering (12)1.5Terms and Abbreviations (12)2Overview (13)2.1Introduction (13)2.2USB Type-C Port Controller (TCPC) Interface (13)3Type-C Port Controller Requirements (14)3.1Port Power Control for VBUS and VCONN (14)3.2USB CC Logic (14)3.3USB-PD Message Delivery (14)3.4Debug Accessory Detection (15)3.5TCPC State-Machines (16)3.6USB Type-C Port Controller Requirements for Source, Sink, and DRP (18)3.6.1Source Requirements (18)3.6.2Sink Requirements: (19)3.6.3Sink with Accessory Support (20)3.6.4DRP Requirements (21)4USB Type-C Port Controller Interface (22)4.1Register Map (23)4.2TCPC SMBus Optional Normative Requirements (25)4.3Writing and Reading TCPC Registers (25)4.3.1Writing Single Byte Registers (25)4.3.2Reading Single Byte Registers (26)4.3.3Writing Multiple-Byte Registers (26)4.3.4Reading Multiple-Byte Registers (27)4.3.5Writing the TRANSMIT_BUFFER (27)4.3.6Reading the RECEIVE_BUFFER (28)4.4Register Definition (29)4.4.1Identification Registers (29)4.4.2ALERT Register (Required) (31)4.4.3Mask Registers (33)4.4.4CONFIGURE STANDARD OUTPUT (Optional Normative) (36)4.4.5Control and Configuration Registers (37)4.4.6Status Registers (43)4.4.7COMMAND (Required) (49)4.4.8Capability Registers (52)4.4.9MESSAGE_HEADER_INFO (Required) (56)4.4.10RECEIVE_DETECT (Required) (56)4.4.11RECEIVE_BUFFER (Required) (57)4.4.12TRANSMIT (Required) (59)4.4.13TRANSMIT_BUFFER (Required) (60)4.4.14VBUS_VOLTAGE (Optional Normative) (61)4.4.15Voltage Thresholds (62)4.4.16VENDOR_DEFINED Registers (64)4.5STANDARD IO SIGNALS (65)4.5.1STANDARD INPUT SIGNALS (Optional Normative) (65)4.5.2STANDARD OUTPUT SIGNALS (Optional Normative exceptAlert#) (65)4.6TCPC Connection State Machine and Flows (67)4.7PD Communication Operational Model (73)4.7.1Transmitting an SOP* Message (73)4.7.2Transmitting a Hard Reset Message (73)4.7.3Receiving an SOP* message (73)4.7.4Receiving a Hard Reset message (74)4.8Power Management (75)4.8.1I2C Interface (75)4.8.2PD Messaging (75)4.8.3CC Status Reporting (75)4.8.4V BUS Reporting (76)4.8.5Fault Status Reporting (76)4.9TCPC Timing Constraints (78)4.10I2C Physical Interface Specifications (78)A Informative TCPM State-Machine Diagrams (81)FIGURESFigure 1-1. USB Type-C Port Manager to USB Type-C Port Controller Interface (10)Figure 2-1. TCPC Interface (13)Figure 3-1. Rx State-Machine Implemented in TCPC (16)Figure 3-2. Tx State-Machine Implemented in TCPC (17)Figure 3-3. Hard Reset Transmission State-Machine implemented in the TCPC (17)Figure 4-1. Writing Consecutive Registers with or without the SMBUS Protocol (25)Figure 4-2. Reading Consecutive Registers with or without the SMBus Protocol (26)Figure 4-3. Writing a 2-Byte Register with or without the SMBus Protocol (26)Figure 4-4. Reading a 2-Byte Register with or without the SMBus Protocol (27)Figure 4-5. Writing the TRANSMIT_BUFFER with or without the SMBus Protocol (27)Figure 4-6. Reading the RECEIVE_BUFFER with or without the SMBus Protocol (28)Figure 4-7. Automatic V BUS Sink Discharge by the TCPC after a Disconnect (43)Figure 4-8. Transition from vSafe5V to High Voltage (51)Figure 4-9. Transition from High Voltage to vSafe5V (51)Figure 4-10. TCPC Power-On State Machine (67)Figure 4-11. TCPC State Machine before a Connection (68)Figure 4-12. TCPC State Machine After a Connection (69)Figure 4-13. TCPC State Machine Debug Accessory (69)Figure 4-14. DRP Initialization and Connection Detection (70)Figure 4-15. Source Disconnect (71)Figure 4-16. Sink Disconnect (72)Figure A-1. Rx State Machine Implemented in TCPM (81)Figure A-2. Tx State Machine Implemented in TCPM (81)Figure A-3. Hard Reset State Machine Implemented in TCPM (82)TABLESTable 4-1. Register Map (23)Table 4-2. VENDOR_ID Register Definition (29)Table 4-3. PRODUCT_ID Register Definition (29)Table 4-4. DEVICE_ID Register Definition (29)Table 4-5. USBTYPEC_REV Register Definition (Required) (29)Table 4-6. USBPD_REV_VER Register Description (30)Table 4-7. PD_INTERFACE_REV Register Description (30)Table 4-8. ALERT Register Definition (31)Table 4-9. ALERT_MASK Register Definition (33)Table 4-10. POWER_STATUS_MASK Register Definition (34)Table 4-11. FAULT_STATUS_MASK Register Definition (35)Table 4-12. CONFIG_STANDARD_OUTPUT Register Definition (36)Table 4-13. TCPC_Control Register Definition (37)Table 4-14. ROLE_CONTROL Register Definition (38)Table 4-15. Power on Default Conditions (39)Table 4-16. FAULT_CONTROL Register Definition (39)Table 4-17. POWER_CONTROL Register Definition (40)Table 4-18. Discharge Timing Parameters (41)Table 4-19. Debounce requirements (44)Table 4-20. CC_STATUS Register Definition (44)Table 4-21. POWER_STATUS Register Definition (46)Table 4-22. FAULT_STATUS Register Definition (47)Table 4-23. COMMAND Register Definition (50)Table 4-24. DEVICE_CAPABILITIES_1 Register Definition (52)Table 4-25. DEVICE_CAPABILITIES_2 Register Definition (53)Table 4-26. STANDARD_INPUT_CAPABILITIES Register Definition (54)Table 4-27. STANDARD_OUTPUT_CAPABILITIES Register Definition (54)Table 4-28. MESSAGE_HEADER_INFO Register Definition (56)Table 4-29. RECEIVE_DETECT Register Definition (56)Table 4-30. RECEIVE_BYTE_COUNT Definition (57)Table 4-31. RX_BUF_FRAME_TYPE Definition (57)Table 4-32. RX_BUF_HEADER Definition (58)Table 4-33. RX_BUFFER_DATA_OBJECTS Definition (58)Table 4-34. TRANSMIT Register Definition (59)Table 4-35. TRANSMIT_BYTE_COUNT Definition (60)Table 4-36. TX_BUF_HEADER Definition (60)Table 4-37. TX_BUFFER_DATA_OBJECTS Definition (60)Table 4-38. VBUS_VOLTAGE Register Definition (61)Table 4-39. VBUS_SINK_DISCONNECT_THRESHOLD Register Description (62)Table 4-40. VBUS_STOP_DISCHARGE_THRESHOLD Register Description (62)Table 4-41. VBUS_VOLTAGE_ALARM_HI_CFG Register Description (63)Table 4-42. VBUS_VOLTAGE_ALARM_LO_CFG Register Description (63)Table 4-43. Standard Input Signals (65)Table 4-44. Standard Output Signals (65)Table 4-45. TCPC Timing Constraints (78)Table 4-46. I2C Static Characteristics (79)Table 4-47. I2C Dynamic Characteristics (79)Specification Work Group Chairs / Specification EditorsIntel Corporation (USB 3.0 Promoter company) Christine Krause – Subgroup WG co-chair, Specification Co-author Chee Lim Nge – Subgroup WG co-chair, Specification Co-authorSpecification Work Group ContributorsAdvanced Micro Devices Will HarrisJason Hawken Joseph ScanlonPeter TengKen XueAnalogix Semiconductor,Inc.Greg StewartApple Sree AnantharamanWilliam FerryArulchandran Paramasivam Reese SchreiberDavid SekowskiSascha TietzHsiao-Ping Jennifer TsaiCadence Design Systems, Inc. Jacek DudaPawel EichlerWojciech Kloska Michal StaworkoCanova Tech Matteo Casalin Davide Ghedin Nicola ScantamburloCypress Semiconductor Anup NayakJagadeesan Raj Subu Sankaran Ganesh SubramaniamDell Inc. Mohammed hijaziMarcin Nowak Siddhartha Reddy Merle WoodDisplayLink (UK) Ltd. Pete BurgersDan Ellis Kevin JacobsRichard PetrieJason YoungEllisys Mario Pasquali Chuck TreftsEtron Technology, Inc. Shihmin Hsu Chien-Cheng KuoFairchild Semiconductor Oscar Freitas Christian Klein Erik Maier Fresco Logic Inc. Tim Barilovits Bob McVay Jeffrey YangGoogle Inc. Alec BergJim GuerinMark Hayter Sameer NandaVincent PalatinDavid SchneiderScott CollyerGranite River Labs Mike EngbretsonHewlett Packard Roger Benson Robin CastellIntel Corporation Bob DunstanAbdul IsmailSanjeev Jahagirdar Vijaykumar KadgiHenrik LeegaardTim McKeeBrad SaundersKarthi VadiveluKeysight Technologies Inc. Jit LimLattice SemiconductorCorpYoung Il Kim Thomas WatzkaMCCI Corporation Terry Moore Sherri Russo Chris YokumMicrochip Technology Inc. Josh AverytMark BohmShannon Cash Brian MarleySantosh shetttyJohn SistoRichard WahlerNeil WinchesterMicrosoft Corporation Randy AullAnthony ChenVivek GuptaDavid Hargrove Robbie HarrisTeemu HeleniusKai InhaJayson KastensIsmo ManninenRahul RamadasNathan ShermanTatu TomppoMQP Electronics Ltd. Sten Carlsen Pat CroweNXP Semiconductors Ken JaramilloAbhijeet Kulkarni Vijendra KuroodiKrishnan TNBart VertentenON Semiconductor Bryan McCoyParade Technologies, Inc. Jian ChenCraig Wiley Paul Xu Alan YuenQualcomm, Inc Craig Aiken Shadi HawawiniRealtek Semiconductor Corp. Charlie HsuRay LeeRyan LinTerry LinChanghung WuRenesas Electronics Corp. Kiichi Muto Hajime NozakiRichtek Technology Corporation Kenny ChanHM ChangPatrick ChangeBryan HuangSpice HuangChunan KuoTony LaiHeinz WeiScott WuAlex YangMing-Shih YuRicoh Company Ltd. Yasuyuki HayashiTatsuya Irisawa Satoshi Oie Yuuji TsutsuiROHM Co., Ltd. Kris BaharRuben Balbuena Nobutaka ItakuraYoshinori OhwakiTakashi SatoSTMicroelectronics Jérôme BachNathalie BallotChristophe lorin Meriem MerselFederico MusarraRichard O'ConnorLegrand PascalSynopsys, Inc. Zongyao WenTexas Instruments Felipe Balbi Scott Jackson Deric Waters VIA Technologies, Inc. Jay Tseng Fong-Jim WangRevision HistoryOctober 20, 2015Interface Specification1 IntroductionWith the continued success of USB Power Delivery, there exists a need to define a commoninterface from a USB Type-C TM Port Manager to a Simple USB Type-C Port Controller. This specification defines this interface.Figure 1-1 shows the interconnection between the USB Type-C Port Manager, TCPM, and three USB Type-C Port Controllers, TCPCs. One TCPM may be used to drive multiple TCPCs subjectbetween theFigure 1-1. USB Type-C Port Manager to USB Type-C Port Controller Interface1.1 PurposeThe USB Type-C Port Controller Interface, TCPCI, is the interface between a USB Type-C Port Manager and a USB Type-C Port Controller. This specification standardizes the communication between the USB Type-C Port Manager (TCPM) and the USB Type-C Port Controller (TCPC) while meeting the USB Type-C Power Delivery requirements.The goal of the USB Type-C Port Controller Interface (TCPCI) is to provide a defined interface between a TCPC and a TCPM in order to standardize and simplify USB Type-C Port Manager implementations.The TCPC is a functional block which encapsulates V BUS and V CONN power controls, USB Type-C CC logic, and the USB PD BMC physical layer and protocol layer other than the message creation.1.2 ScopeThis specification is intended as a supplement to USB 3.1, USB Type-C , and USB PDspecifications. It addresses only the elements required to implement and support the USB Type-C Port Controller.Normative information is provided to allow interoperability of components designed to this specification. Informative information, when provided, may illustrate possible design implementations.Platform Policy ManagerOS Policy ManagerPPM InterfacePD System Policy Manager(optional)PD Device Policy Manager(for PD-capable ports)1.3Related DocumentsUSB 3.1 Universal Serial Bus Revision 3.1 SpecificationThis includes the entire document release package./developers/docsUSB PD USB Power Delivery Specification, Revision 2.0, August 11, 2014 /developers/docsUSB Type-C USB Type-C Connector Specification, Revision 1.0, August 11, 2014 /developers/docs1.4Conventions1.4.1PrecedenceIf there is a conflict between text, figures, and tables, the precedence shall be tables, figures, and then text.1.4.2KeywordsThe following keywords differentiate between the levels of requirements and options.1.4.2.1InformativeInformative is a keyword that describes information within this specification that intends to discuss and clarify requirements and features as opposed to mandating them.1.4.2.2MayMay is a keyword that indicates a choice with no implied preference.1.4.2.3N/AN/A is a keyword that indicates a field or value is not applicable and has no defined value and shall not be checked or used by the recipient.1.4.2.4NormativeNormative is a keyword that describes features mandated by this specification.1.4.2.5OptionalOptional is a keyword that describes features not mandated by this specification. However, if an optional feature is implemented, the feature shall be implemented as defined by this specification (optional normative).1.4.2.6ReservedReserved is a keyword indicating reserved bits, bytes, words, fields, and code values that are set-aside for future standardization. Their use and interpretation may be specified by future extensions to this specification and, unless otherwise stated, shall not be utilized or adapted by vendor implementation. A reserved bit, byte, word, or field shall be set to zero by the sender and shall be ignored by the receiver. Reserved field values shall not be sent by the sender, and if received, shall be ignored by the receiver.1.4.2.7ShallShall is a keyword indicating a mandatory (normative) requirement. Designers are mandated to implement all such requirements to ensure interoperability with other compliant Devices.1.4.2.8ShouldShould is a keyword indicating flexibility of choice with a preferred alternative equivalent to the phrase “it is recommended that”.1.4.3NumberingNumbers immediately followed by a lowercase “b” (e.g., 01b) are binary values. Numbers immediately followed by an uppercase “B” are byte values. Numbers immediately followed by a lowercase “h” (e.g., 3Ah) are hexadecimal values. Numbers not immediately followed by either a “b”, “B”, or “h” are decimal values.1.5Terms and Abbreviations2Overview2.1Introduction2.2USB Type-C Port Controller (TCPC) InterfaceFigure 2-1. TCPC InterfaceThe USB Type-C Port Controller Interface, TCPCI, is the interface between a USB Type-C Port Manager and a USB Type-C Port Controller. The goal of the USB Type-C Port Controller Interface (TCPCI) is to provide a defined interface between a TCPC and a TCPM in order to standardize and simplify USB Type-C Port Manager implementations.The TCPC is a functional block which encapsulates V BUS and V CONN power controls, USB Type-C CC logic, and the USB PD BMC physical layer and protocol layer other than the message creation. The TCPC shall NOT include support for USB PD BFSK.3Type-C Port Controller RequirementsThis chapter describes the requirements of a USB Type-C Port Controller. The TCPC has three functions:∙USB Type-C Port Power Control for V BUS and V CONN (required)∙USB Type-C CC Control and sensing (required)∙USB PD Message delivery (required)∙Standard Inputs and Outputs are defined for simplified external interfacing (optional)The TCPC uses I2C to communicate with the TCPM. The TCPC is an I2C slave with Alert# signal for requesting attention.3.1Port Power Control for VBUS and VCONNA Source capable TCPC shall provide a register which allows the TCPM to control V BUS Sourcing. A Sink capable TCPC shall provide a register which allows the TCPM to ControlV BUS Sinking.To ensure safety in case the I2C interface fails, the TCPC that is sourcing V BUS higher than 5V shall autonomously stop sourcing V BUS if the Sink is detached.The TCPC shall implement a force discharge circuit. A low current bleed discharge may also be implemented. The force discharge is a larger current discharge used to discharge to below vSafe0V upon detecting a Disconnect per USB Type-C (exiting the Attached.SRC state). The discharge shall be available for both Source and Sink.A TCPC shall include monitoring for the presence of V BUS (VSafe5V, VSafe0V). The TCPC shall implement high and low voltage alarms if it Sinks or Sources voltage greater tha n VSafe5V.A Source or DRP TCPC shall include control for V CONN sourcing. A Sink TCPC shall include control for V CONN sourcing if V CONN Swap or Sink w/Accessory is supported. V CONN sourcing shall meet the tV CONN ON and tV CONN OFF timing requirement per USB Type-C.A TCPC shall implement low power states as defined in this specification.3.2USB CC LogicThe TCPC shall implement logic for controlling the CC pins on the USB Type-C Connector. The TCPC shall implement a method to control the Port Power Role and to report the state of the CC lines, Rp/Rd control, and CC sense/debounce/interrupt.3.3USB-PD Message DeliveryThe TCPC shall implement BMC encoding. The TCPC shall NOT include support for USB PD BFSK. The TCPC shall implement the portion of the Protocol layer in the USB PD specification as shown in Figure 3-2, and 3-3. The TCPC is opaque from a USB PD point of view. The TCPC sends and receives messages constructed in the TCPM and places them on the CC connections. The TCPC does not interpret the USB PD messages.The TCPC shall implement the entire USB PD PHY layer with BMC encoding. The TCPC shall implement a portion of the Transmit state machine.∙CRCReceiveTimer (PRL_Tx_wait_for_Phy_Response_state)∙RetryCounter (PRL_Tx_Check_RetryCounter State)∙MessageID is not checked in the TCPC when a non-GoodCRC message is received.Retried messages that are received are passed to the TCPM via I2C ∙Received GoodCRC must match the transmitted MessageID and SOP type before it is considered valid∙Two things allow the TCPM to track the MessageID even when asynchronous messages are receivedo If ALERT.ReceiveSOP*MessageStatus is not cleared when the TCPM requestsa TRANSMIT then the I2C command is NAK’d orTransmitSOP*MessageDiscarded bit in the ALERT register is asserted.o If a message is received before the TCPC has processed a transmit request, it asserts the TransmitSOP*MessageDiscarded bit in the ALERT register.∙BIST handling shall be as follows: Each incoming BIST message may be passed up to the policy engine as is any other incoming USB PD Message, or responded to with a GoodCRC without passing to the policy engine. The TCPC shall provide a mechanism to allow the policy engine to send a BIST Continuous Carrier Mode 2 message fortBistContMode.3.4Debug Accessory DetectionThe TCPC may implement autonomous detection of the Debug Accessory State (vRd/vRd) per USB Type-C. This allows the TCPC to indicate a vRd/vRd connection without TCPM involvement, and indicates this via the DebugAccessoryConnected# output andPOWER_STATUS.DebugAccessoryConnected. The TCPC performs autonomous detection of the Debug Accessory state if TCPC_CONTROL.DebugAccessoryControl=0b.The TCPM may control entry to the Debug Accessory Detected state by settingTCPC_CONTROL.DebugAccessoryControl=1b.The behavior in the Debug Accessory state is defined in USB Type-C in Appendix B.3.5 TCPC State-MachinesThis section describes the normative State-Machines for the TCPC. The informative TCPM State-Machines can be found in Appendix A.Figure 3-1. Rx State-Machine Implemented in TCPC1becomes idle again (see USB-PD specification). Two alternate allowable transitions are shown.2Messages do not include Hard Reset or Cable Reset signals or expected GoodCRC messages (GoodCRC messages are only expected after the TCPC PHY has received the tx message and the TCPC Tx state-machine is in the PRL_Tx_Wait_for_PHY_response state).3The TCPC may not discard the transmission if the received message is a Ping message.1The CRCReceiveTimer is only started after the PHY has sent the message. If the message is not sent due to a busy channel then the CRCReceiveTimer will not be started (see USB-PD Rev2.0 v1.1 Section 6.5.1).2This indication is sent by the PHY Layer when a message has been discarded due to V BUS or CC being busy, and after V BUS or CC becomes idle again (see USB-PD REv2.0 v1.1 Section 5.8). The CRCReceiveTimer is not running in this case since no message has been sent.Figure 3-2. Tx State-Machine Implemented in TCPCFigure 3-3. Hard Reset Transmission State-Machine implemented in the TCPC3.6USB Type-C Port Controller Requirements for Source, Sink, and DRP3.6.1Source RequirementsA TCPC, which supports Source port operation, is defined as follow:1. A Source TCPC shall provide control of V BUS source path (see Table 4-23. COMMANDRegister Definition).2. A Source TCPC may provide over voltage protection and over current protectioncircuitry for the V BUS source path (see FAULT_STATUS.OCP/OVP andFAULT_CONTROL.OCP/OVP).3. A Source TCPC shall provide control of a V CONN switch (seePOWER_CONTROL.V CONN PowerSupported and POWER_CONTROL.EnableVconn).4. A Source TCPC may include monitoring for the presence of V CONN (seePOWER_STATUS.V CONN Present).3.6.2Sink Requirements:A TCPC, which supports Sink port operation, is defined as follow:1. A Sink TCPC shall contain CC logic that implements a mechanism to present Rd in adead battery condition (see Table 4-15. Power on Default Conditions).2. A Sink TCPC may include the monitoring of the presence of V CONN (seePOWER_CONTROL.V CONN PowerSupported and POWER_STATUS.V CONN Present).3. A Sink TCPC shall provide control of V BUS sink path (see COMMAND).4. A Sink TCPC shall provide a mechanism for detecting a Disconnect if it is capable ofsinking a voltage greater than vSafe5V (see Section 4.4.15.1).5. A Sink TCPC shall provide a mechanism for detecting vSafe0V.3.6.3Sink with Accessory SupportA TCPC, which supports Sink with Accessory Support operation, is defined as follow:1. A Sink TCPC shall contain CC logic that implements a mechanism to present Rd in adead battery condition (see Table 4-15. Power on Default Conditions).2. A Sink TCPC shall provide control of V CONN source path (seePOWER_CONTROL.V CONN PowerSupported and POWER_CONTROL.EnableV CONN).3. A Sink TCPC may include the monitoring of the presence of V CONN (seePOWER_STATUS.V CONN Present).4. A Sink TCPC shall provide control of V BUS sink path (see COMMAND).5. A Sink TCPC shall provide a mechanism for detecting a Disconnect if it is capable ofsinking a voltage greater than vSafe5V (see Section 4.4.15.1).6. A Sink TCPC shall provide a mechanism for detecting vSafe0V.Sink with Accessory support is optional, but if implemented shall follow the table below.3.6.4DRP RequirementsA TCPC, which supports Dual Role Port operation, is defined as follow:1. A Dual Role TCPC shall contain CC logic to detect the insertion of a Source, Sink, andAudio and debug accessory (see ROLE_CONTROL).2. A Dual Role TCPC shall contain CC logic that implements a mechanism to present Rdin a dead battery condition (see CC_STATUS).3. A Dual Role TCPC shall provide control of V BUS source path (see COMMAND).4. A Dual Role TCPC shall provide control for a Vconn switch (seePOWER_CONTROL.V CONN PowerSupported and POWER_CONTROL.EnableV CONN)5.The TCPC shall include the monitoring of the presence of V CONN (seePOWER_STATUS.V CONN Present).6. A DRP TCPC shall provide a mechanism for detecting a Disconnect if it is capable ofsinking a voltage greater the vSafe5V (see Section 4.4.15.1).7. A DRP TCPC shall provide a mechanism for detecting vSafe0V.4USB Type-C Port Controller InterfaceThe USB Type-C Port Controller Interface (TCPCI) is a low level interface which handles V BUS and V CONN power connections, CC communication and USB-PD message delivery through a simple register interface. Communication between the TCPC and the USB Type-C Port Manager (TCPM) is over an I2C bus.The TCPCI uses the I2C protocol with the following behaviors:1.The TCPM is the only master on the I2C bus.2.The TCPC is a slave device on the I2C bus.3.The TCPM designer must meet the I2C bus loading requirements when determiningthe maximum number of devices on the I2C bus.4.Each USB Type-C port has its own unique I2C slave address. The TCPC may supportmultiple USB Type-C ports. In case the TCPC supports multiple ports, each USB Type-C port shall have a unique I2C slave address.5.The TCPC shall support Fast-mode (Fm+) bus speed. It may also support other busspeeds.6.The TCPC shall have an open drain output, active low Alert# Pin. This pin is used toindicate a change of state, where Alert# pin is asserted when any Alert Bits are set.7.The TCPCI shall support an I/O voltage range from 1.8V to 3.6V.8.The TCPC as a slave device shall be accessible through I2C communication protocolscompliant with “I2C-bus specification and user manual Rev.6” (4th April 2014)/documents/user_manual/UM10204.pdf9.The TCPC should auto-increment the I2C internal register address of the last bytetransferred during a read independent of an ACK/NAK from the master.10.The TCPC may implement the SMBus version 3 bus protocol (Section 6.5 of theSMBus Specification, version 3.0 available at /specs/).11.The TCPC shall allow reads to every register even when defined as Write only. TheTCPM should assume the register information returned from a Write only register is not valid.12.The TCPC shall not NAK if the TCPM writes to a register or bit that is notimplemented or reserved.。

USB3.1 Type-C接口定义

USB Type-C是什么？感谢把我给崩了的投递时间：2015-03-14 来源：三联北京时间3月10日凌晨，苹果在美国旧金山芳草地艺术中心发布了新款Macbook，它的轻薄给无数消费者留下了深刻的印象。

再一次，追求极致的苹果对 Macbook 12上的各种接口挥起了屠刀，在砍掉原有全部接口的情况下，向我们介绍了一种如 Lightning 接口般轻薄小巧的新型 USB 接口：USB Type-C。

那么问题来了，USB Type-C是什么?为什么苹果会选择 USB 而不是力推多年的Thunderbolt，USB Type-C是何方神圣?下面百事网小编为大家详细介绍下下。

USB Type-C是什么?USB Type-C简称为USB-C，它的诞生并不久远，早在13年12月，USB 3.0推广团队就已经公布了下一代USB Type-C连接器的渲染图，在2014年8月发布的USB 3.1标准中才刚刚定稿。

它是一种新型 USB 线缆及连接器的规范，定义了包括连接器、端口、容器和线缆等在内的一整套全新的USB物理规格。

USB Type-C是一种和iPhone手机中Lightning接口般轻薄小巧的新型USB接口，可以扩展成电源/USB传输/VGA或HDMI三个接口，通过适配器，还可以兼容USB3.0、USB2.0等上一代接口。

USB Type-C具有全新的接口尺寸和略显酷炫的名称，非常容易使第一次听到这个名词的消费者以为这是一种全新的USB标准，但实际上并不是。

USB Type-C 只是 USB 3.1 标准的一部分，而不是一个新的标准。

另外，需要说明的是，与常见的 USB 2.0 类似，USB 3.1 标准仍有Type-A(常见于电脑主机)和 Micro-B(常见于安卓手机)等接口，Type-C 并不是消费者享受 USB 3.1 高速数据传输的唯一选择。

苹果Mac 12单USB-C接口揭秘为什么USB组织需要推出一种新的物理接口规范呢?随着越来越多新型设备对于轻量化小型化的追求，传统 USB 接口的“庞大”尺寸已经很难满足设备生产厂商和消费者的需求。

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5.3 Connector Mating InterfacesThis section defines the connector mating interfaces, including the connector interface drawings, pin assignments, and descriptions.5.3.1 USB 3.1 Standard-A Connector5.3.1.1 Interface DefinitionFigure 5-1 and Figure 5-2 show the USB 3.1 Standard-A receptacle and required ground springmating areas, respectively. Figure 5-4 shows the Standard-A plug interface dimensions forUSB 3.1. Only the dimensions that govern the mating interoperability are specified. All REFdimensions are informative.The Universal Serial Bus Power Delivery Specifiation defines the mechanical and electricalrequirements for the Insertion Detect feature to support cold socket capability. It may beimplemented in a Standard-A receptacle or a PD Standard-A receptacle. Implementation is vendor-specific. The Insertion Detect feature shall be implemented for cold socket Standard-A applications and is optional for all other Standard-A implementations. See the Universal Serial Bus PowerDelivery Specifiation for complete Insertion Detect requirements. Example connectorconfigurations including Insertion Detect features are shown in Figure 5-3.Although the USB 3.1 Standard-A connector has basically the same form factor as the USB 2.0Standard-A connector, it has significant differences inside. Below are the key features and design areas that need attention:•In addition to the Vbus, D-, D+, and GND pins that are required for USB 2.0, the USB 3.1 Standard-A connector includes five more pins: two differential signal pairs plus one ground(GND_DRAIN). The two added differential signal pairs are for SuperSpeed data transfer,supporting dual simplex SuperSpeed signaling. The added GND_DRAIN pin is for drain wiretermination and managing EMI, RFI, and signal integrity.•The contact areas of the five SuperSpeed pins are located towards the front of the receptacle as blades, while the four USB 2.0 pins towards the back of the receptacle as beams or springs.Accordingly, in the plug, the SuperSpeed contacts are beams located behind the USB 2.0blades. In other words, the USB 3.1 Standard-A connector has a two-tier contact system.•The tiered-contact approach within the Standard-A connector form factor results in less contact area as compared to the USB 2.0 Standard-A connector. The connector interface dimensionstake into consideration contact mating requirements between the USB 3.1 Standard-Areceptacle and USB 3.1 Standard-A plug, the USB 3.1 Standard-A receptacle and USB 2.0Standard-A plugs, and the USB 2.0 Standard-A receptacles and USB 3.1 Standard-A plug.•The connector interface definition avoids shorting between the SuperSpeed and USB 2.0 pins during insertion when plugging a USB 2.0 Standard-A plug into a USB 3.1 Standard-Areceptacle or a USB 3.1 Standard-A plug into a USB 2.0 Standard-A receptacle.•There may be some increase in the USB 3.1 Standard-A receptacle connector depth (into a system board) to support the two-tiered-contacts as compared to the USB 2.0 Standard-Areceptacle.•Drawings for stacked USB 3.1 Standard-A receptacles are not shown in this specification.They are allowed as long as they meet all the electrical and mechanical requirements defined inthis specification. When designing a stacked USB 3.1 Standard-A receptacle, efforts need to bemade to minimize impedance discontinuity of the top connector in the stack because of its long electrical path. Attention to the high speed electrical design of USB 3.1 Standard-A connectors is required. In addition to minimizing the connector impedance discontinuities, crosstalkbetween the SuperSpeed differential signal pairs and USB 2.0 D+/D- pair should also beminimized.•The receptacle connector should have a back-shield to ensure that the receptacle connector is fully enclosed. The USB 3.1 receptacle should also make good contact to the PCB ground by providing sufficient number of ground tabs to ensure a low impedance path to PCB ground.The USB 3.1 receptacle connector should have a robust mating interface to the shield of the USB 3.1 plug when it is inserted. Previous versions of this specification required providing a grounding spring tab in the middle of the side closest to the USB SuperSpeed signal contacts and grounding springs on both sides of the shell for USB 3.0 Standard-A receptacles. New designs shall have three grounding spring tabs on the side closest to the USB SuperSpeed signal contacts, two grounding spring tabs on the side opposite the USB SuperSpeed signal contacts, and a grounding spring on both sides of the shell of the USB 3.1 Standard-A receptacle. See Figure 5-2.Continued on next pageContinued on next pageFigure 5-1. USB 3.1 Standard-A Receptacle Interface DimensionsContinued on next page TOP VIEW (SIDE NEAREST SUPERSPEED CONTACTS)Figure 5-2. Example USB 3.1 Standard-A Receptacle with Grounding Springs and Requiredcontact zones on the Standard-A Plug.EMI contact zones BOTTOM VIEW (SIDE OPPOSITE SUPERSPEED CONTACTS)Insertion detect pinsDetect circuit is closed after amating part is insertedDetect circuitSpring fingers on the side ofreceptacle shell are EMI functionalFigure 5-3. Example USB 3.1 Standard-A Mid-Mount Receptacles with Insertion DetectContinued on next pageContinued on next pageFigure 5-4. USB 3.1 Standard-A Plug Interface Dimensions5.3.1.2 USB 3.1 Standard-A Reference FootprintsThis specification does not define standard footprints. Any footprint may be used as long as all mechanical and electrical requirements are met. Example footprints are provided for reference only.Figure 5-5 shows through-hole example footprints for the USB 3.1 Standard-A receptacle with a back-shield. Pin numbers are marked.Figure 5-6 shows an example footprint for a mid-mount standard mount (mounted on the top of the PCB) Standard-A receptacle that includes Insertion Detect.Figure 5-7 shows an example mid-mount reverse mount (mounted on the bottom of the PCB) with Insertion Detect. The reverse mount configuration locates the SuperSpeed signals between the USB 2.0 signals and the PCB edge, making the SuperSpeed signal routing more challenging.See Section 5.6.1.2 for target characteristic impedance.Continued on next page5-14Continued on next page5-15Back-Shield5-165-17Figure 5-6. Example Footprint for the USB 3.1 Standard-A Receptacle - Mid-Mount StandardMount Through-Hole with Insertion Detect5-18Figure 5-7. Example Footprint for the USB 3.1 Standard-A Receptacle - Mid-Mount ReverseMount Through-Hole with Insertion Detect5.3.1.3 Pin Assignments and DescriptionThe usage and assignments of the nine pins in the USB 3.1 Standard-A connector are defined in Table 5-2.Table 5-2. USB 3.1 Standard-A Connector Pin AssignmentsPin Number1Signal Name2Description Mating Sequence31 VBUS Power Third2 D- USB 2.0 differential pair Fourth3 D+4 GND Ground for power return Third5 StdA_SSRX- SuperSpeed receiver differentialpair Last6 StdA_SSRX+7 GND_DRAIN Ground for signal return8 StdA_SSTX- SuperSpeed transmitterdifferential pair9 StdA_SSTX+124, 13 INSERTIONDETECT Receptacle only. Detectsinsertion of a plug into thereceptacle. Optional except forcold socket applications. See the Universal Serial Bus PowerDelivery Specifiation for details.SecondShell Shield Connector metal shell FirstNote 1: Note 1: Pin numbers not included in this table do not have contacts present.Note 2: Tx and Rx are defined from the host perspective.Note 3: The mating sequence assumes support of INSERTION DETECT.Note 4: Pin 12, if present, shall be connected to Shield.The physical location of the pins in the connector is illustrated in Figure 5-1 to Figure 5-7. Pins 1 to 4 are referred to as the USB 2.0 pins, while pins 5 to 9 are referred to as the SuperSpeed pins. See the Universal Serial Bus Power Delivery Specifiation for location of pins 12 and 13.5-195-205.3.1.4 USB 3.1 Standard-A Connector Color CodingSince both the USB 2.0 Standard-A and USB 3.1 Standard-A receptacles may co-exist on a host, color coding is recommended for the USB 3.1 Standard-A connector (receptacle and plug) housings to help users distinguish it from the USB 2.0 Standard-A connector.Blue (Pantone 300C) is the recommended color for the USB 3.1 Standard-A receptacle and plug plastic housings. When the recommended color is used, connector manufacturers and systemintegrators should make sure that the blue-colored receptacle housing is visible to users. Figure 5-8 illustrates the color coding recommendation for the USB 3.1 Standard-A connector.Figure 5-8. Illustration of Color Coding Recommendation for USB 3.1Standard-A Connector5.3.2USB 3.1 Standard-B Connector5.3.2.1Interface DefinitionFigure 5-9, Figure 5-10, and Figure 5-11 show the USB Standard-B receptacle dimensions, the USB Standard-B plug dimensions, and a USB Standard-B receptacle reference footprint, respectively. See Section 5.6.1.2 for target characteristic impedance.5-21Continued on next page5-22Figure 5-9. USB 3.1 Standard-B Receptacle Interface Dimensions5-23Figure 5-10. USB 3.1 Standard-B Plug Interface DimensionsFigure 5-11. Reference Footprint for the USB 3.1 Standard-B ReceptacleThe USB 3.1 Standard-B receptacle interfaces have two portions: the USB 2.0 interface and the SuperSpeed interface. The USB 2.0 interface consists of pins 1 to 4, while the SuperSpeed interface consists of pins 5 to 9.When a USB 2.0 Standard-B plug is inserted into the USB 3.1 Standard-B receptacle, only the USB 2.0 interface is engaged and the link will not take advantage of the Enhanced SuperSpeed capability. Since the USB 3.1 SuperSpeed portion is visibly not mated when a USB 2.0 Standard-B plug is inserted in the USB 3.1 Standard-B receptacle, users have the visual feedback that the cable plug is not matched with the receptacle. Only when a USB 3.1 Standard-B plug is inserted into the USB 3.1 Standard-B receptacle, is the interface completely visibly engaged.5.3.2.2 Pin Assignments and DescriptionThe usage and assignments of the nine pins in the USB 3.1 Standard-B connector are defined in Table 5-3.Table 5-3. USB 3.1 Standard-B Connector Pin AssignmentsPin Number Signal Name Description Mating Sequence1 VBUS Power Second2 D- USB 2.0 differential pair Third or beyond3 D+4 GND Ground for power return Second5 StdB_SSTX- SuperSpeed transmitterdifferential pair Third or beyond6 StdB_SSTX+7 GND_DRAIN Ground for signal return8 StdB_SSRX- SuperSpeed receiver differentialpair9 StdB_SSRX+Shell Shield Connector metal shell FirstNote: Tx and Rx are defined from the device perspective.The physical location of the pins in the connector is illustrated in Figure 5-9 to Figure 5-11.5.3.3 USB 3.1 Micro Connector Family5.3.3.1 Interfaces DefinitionThe USB 3.1 Micro connector family consists of the USB 3.1 Micro-B receptacle, USB 3.1Micro-AB receptacle, USB 3.1 Micro-B plug, and USB 3.1 Micro-A plug. Figure 5-12 and Figure 5-13 show the USB 3.1 Micro family receptacle and plug interface dimensions, respectively. Only dimensions that govern the mating interoperability are specified.The USB 3.1 Micro connector family has the following characteristics:•The USB 3.1 Micro-B connector may be considered a combination of USB 2.0 Micro-B interface and the USB 3.1 SuperSpeed contacts. The USB 3.1 Micro-B receptacle accepts aUSB 2.0 Micro-B plug, maintaining backward compatibility.•The USB 3.1 Micro-B connector maintains the same connector height and contact pitch as the USB 2.0 Micro-B connector.•The USB 3.1 Micro-B connector uses the same latch design as the USB 2.0 Micro-B connector.•The USB 3.1 Micro-AB receptacle is identical to the USB 3.1 Micro-B receptacle except for a keying difference in the connector shell outline.•The USB 3.1 Micro-A plug is similar to the USB 3.1 Micro-B plug with different keying and ID pin connections. The Universal Serial Bus Power Delivery Specifiation discusses the ID pin connections.There is no required footprint for the USB 3.1 Micro connector family. Figure 5-14 showsreference Micro-B and -AB connector footprints.Continued on next pageFigure 5-12. USB 3.1 Micro-B and -AB Receptacles Interface DimensionsContinued on next pageContinued on next pageFigure 5-13. USB 3.1 Micro-B and Micro-A Plug Interface DimensionsContinued on next pageFigure 5-14. Reference Footprint for the USB 3.1 Micro-B or Micro-AB Receptacle5.3.3.2 Pin Assignments and DescriptionTable 5-4 and Table 5-5 show the pin assignments for the USB 3.1 Micro connector family.Table 5-4. USB 3.1 Micro-B Connector Pin AssignmentsPin Number Signal Name Description Mating Sequence1 VBUS Power Second2 D- USB 2.0 differential pair Last3 D+4 ID OTG identification5 GND Ground for power return Second6 MicB_SSTX- SuperSpeed transmitterdifferential pair Last7 MicB_SSTX+8 GND_DRAIN Ground for SuperSpeed signalreturnSecond9 MicB_SSRX- SuperSpeed receiver differentialpair Last10 MicB_SSRX+Shell Shield Connector metal shell FirstNote: Tx and Rx are defined from the device perspective.Table 5-5. USB 3.1 Micro-AB/-A Connector Pin AssignmentsPin Number Signal Name Description Mating Sequence1 VBUS Power Second2 D- USB 2.0 differential pair Last3 D+4 ID OTG identification5 GND Ground for power return Second6 MicA_SSTX- SuperSpeed receiver differentialpair Last7 MicA_SSTX+8 GND_DRAIN Ground for SuperSpeed signalreturnSecond9 MicA_SSRX- SuperSpeed transmitterdifferential pair Last10 MicA_SSRX+Shell Shield Connector metal shell FirstNote: Tx and Rx are defined when an OTG device serves as a host.The physical location of the pins in the connector is illustrated in Figure 5-12 to Figure 5-14.5.4 Cable Construction and Wire AssignmentsThis section discusses the USB 3.1 cables, including cable construction, wire assignments, and wire gauges. The performance requirements are specified in Section 5.6.1.5.4.1 Cable ConstructionFigure 5-15 illustrates a USB 3.1 cable cross-section. There are three groups of wires: D+/D-signal pair (typically unshielded twisted pair (UTP)), Enhanced SuperSpeed signal pairs (typically Shielded Differential Pair (SDP), twisted, twinax, or coaxial signal pairs), and power and ground wires.Figure 5-15. Illustration of a USB 3.1 Cable Cross-Section The D+/D- signal pair is intended to transmit the USB 2.0 signaling while the EnhancedSuperSpeed signal pairs are used for SuperSpeed; the shield is needed for the SuperSpeeddifferential pairs for signal integrity and EMI performance. Each Enhanced SuperSpeed drain wire is connected to the system ground through the GND_DRAIN pin(s) in the connector.A metal braid is required to enclose all the wires in the USB 3.1 cable. The braid shall beterminated to the plug metal shells, as close to 360° as possible, to reduce EMI.5.4.2 Wire AssignmentsTable 5-6 defines the wire number, signal assignments of the wires.Table 5-6. Cable Wire AssignmentsWire Number Signal Name Description1 PWR Power2 D- Unshielded twist pair, negative3 D+ Unshielded twist pair, positive4 GND_PWRrt Ground for power return5 P1- Shielded differential pair 1, negative6 P1+ Shielded differential pair 1, positive7 P1_Drain Drain wire for SDP18 P2- Shielded differential pair 2, negative9 P2+ Shielded differential pair 2, positive10 P2_Drain Drain wire for SDP2Braid Shield Cable external braid to be 360°terminated on to plug metal shell5.4.3 Wire Gauges and Cable DiametersThis specification does not specify wire gauges. Table 5-7 lists typical wire gauges for reference purposes only. A large gauge wire incurs less loss, but at the cost of cable flexibility. It isrecommended to use the smallest possible wire gauges that meet the cable assembly electrical requirements.To maximize cable flexibility, all wires should be stranded and the cable outer diameter should be minimized as much as possible. A typical non-USB 3.1 Power Delivery capable cable outerdiameter may range from 3 mm to 6 mm.Table 5-7. Reference Wire GaugesWire Number Signal Name Wire Gauge (AWG)1 PWR 20-282 D- 28-343 D+ 28-344 GND_PWRrt 20-285 P1- 26-346 SP1+ 26-347 P1_Drain 28-348 P2- 26-349 P2+ 26-3410 P2_Drain 28-345.5 Cable Assemblies5.5.1 USB 3.1 Standard-A to USB 3.1 Standard-B CableAssemblyFigure 5-16 shows a USB 3.1 Standard-A to USB 3.1 Standard-B cable assembly. Due to increased wire sizes required for some PD cable implementations, the overmold dimensions for PD cables have larger maximum dimensions than the non-PD cables specified. See the Universal Serial Bus Power Delivery Specifiation for the maximum overmold dimensions of PD cable assemblies.Figure 5-16. USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly Table 5-8 defines the wire connections for the USB 3.1 Standard-A to USB 3.1 Standard-B cable assembly.Table 5-8. USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly Wiring USB 3.1 Standard-A Plug Wire USB 3.1 Standard-B Plug Pin Number Signal Name Wire Number Signal Name Pin Number Signal Name1 VBUS 1 PWR 1 VBUS2 D- 2 D- 2 D-3 D+ 3 D+ 3 D+4 GND 4 GND_PWRrt 4 GND5 StdA_SSRX- 5 P1- 5 StdB_SSTX-6 StdA_SSRX+ 6 P1+ 6 StdB_SSTX+7 GND_DRAIN 7 and 10 P1_Drain7 GND_DRAINP2_Drain8 StdA_SSTX- 8 P2- 8 StdB_SSRX-9 StdA_SSTX+ 9 P2+ 9 StdB_SSRX+Shell Shield Braid Shield Shell Shield5.5.2 USB 3.1 Standard-A to USB 3.1 Standard-A Cable AssemblyThe USB 3.1 Standard-A to USB 3.1 Standard-A cable assembly is defined for operating system debugging and other host-to-host connection applications. Table 5-9 shows wire connections for such a cable assembly. Refer to Figure 5-16 for the USB 3.1 Standard-A plug cable overmolddimensions.Table 5-9. USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly Wiring USB 3.1 Standard-A Plug #1 Wire USB 3.1 Standard-A Plug #2 Pin Number Signal Name Wire Number Signal Name Pin Number Signal Name1 VBUS No connect 1 VBUS2 D- No connect 2 D-3 D+ No connect 3 D+4 GND 4 GND_PWRrt 4 GND5 StdA_SSRX- 5 P1- 8 StdA_SSTX-6 StdA_SSRX+ 6 P1+ 9 StdA_SSTX+7 GND_DRAIN7 GND_DRAIN 7 & 10 P1_DrainP2_Drain8 StdA_SSTX- 8 P2- 5 StdA_SSRX-9 StdA_SSTX+ 9 P2+ 6 StdA_SSRX+Shell Shield Braid Shield Shell Shield5.5.3 USB 3.1 Standard-A to USB 3.1 Micro-B Cable AssemblyFigure 5-17 shows the USB 3.1 Micro-B plug overmold dimensions for a USB 3.1 Standard-A to USB 3.1 Micro-B cable assembly. The USB 3.1 Standard-A plug overmold dimensions are found in Figure 5-16. Due to increased wire sizes required for some PD cable implementations, theovermold dimensions for PD cables have larger maximum dimensions than the non-PD cables specified. See the Universal Serial Bus Power Delivery Specifiation for the maximum overmold dimensions of PD cable assemblies.Notes:1. Any surface may have texturing up to 0.3 mm below the surface.2. A square area around the letter B may be lowered as much as 0.5 mm.3. USB authorized icon, connector type letter designation (i.e., B),color of the insulator body, and maximum dimensions are mandatory.Overmold outer configuration, color, and final shape are reference.4. Pin 4 is not connected to pin 5 inside the plug.Figure 5-17. USB 3.1 Micro-B Plug Cable Overmold DimensionsTable 5-10 shows the wire connections for the USB 3.1 Standard-A to USB 3.1 Micro-B cable assembly. Note that the ID pin in the USB 3.1 Micro-B plug shall not be connected, but left in the open condition.Table 5-10. USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly Wiring USB 3.1 Standard-A Plug Wire USB 3.1 Micro-B PlugPin Number Signal Name Wire Number Signal Name Pin Number Signal Name1 VBUS 1 PWR 1 VBUS2 D- 2 D- 2 D-3 D+ 3 D+ 3 D+4 GND 4 GND_PWRrt5 GND5 StdA_SSRX- 5 P1-6 MicB_SSTX-6 StdA_SSRX+ 6 P1+7 MicB_SSTX+8 GND_DRAIN7 GND_DRAIN 7 and 10 P1_DrainP2_Drain8 StdA_SSTX- 8 P2- 9 MicB_SSRX-9 StdA_SSTX+ 9 P2+ 10 MicB_SSRX+4 IDShell Shield Braid Shield Shell Shield5.5.4 USB 3.1 Micro-A to USB 3.1 Micro-B Cable AssemblyFigure 5-18 shows the USB 3.1 Micro-A plug cable overmold dimensions in a USB 3.1 Micro-A to USB 3.1 Micro-B cable assembly. The USB 3.1 Micro-B plug cable overmold dimensions areshown in Figure 5-17. Due to increased wire sizes required for some PD cable implementations, the overmold dimensions for PD cables have larger maximum dimensions than the non-PD cables specified. See the Universal Serial Bus Power Delivery Specifiation for the maximum overmold dimensions of PD cable assemblies.Notes:1. Any surface may have texturing up to 0.3 mm below the surface.2. A square area around the letter A may be lowered as much as 0.5 mm.3. USB authorized icon, connector type letter designation (i.e., A),color of the insulator body, and maximum dimensions are mandatory.Overmold outer configuration, color, and final shape are reference.4. Pin 4 is connected to pin 5 inside the plug.Figure 5-18. USB 3.1 Micro-A Cable Overmold DimensionsTable 5-11 shows the wire connections for the USB 3.1 Micro-A to USB 3.1 Micro-B cable assembly. The ID pin on a USB 3.1 Micro-A plug shall be connected to the GND pin. The ID pin on a USB 3.1 Micro-B plug shall be a no-connect or connected to ground by a resistance of greater than Rb_PLUG_ID (1 MΩ minimum). See the Universal Serial Bus Power Delivery Specification for additional details regarding electrical connections to ID pins. An OTG device is required to be able to detect whether a USB 3.1 Micro-A or USB 3.1 Micro-B plug is inserted by determining if the ID pin resistance to ground is less than Ra_PLUG_ID (10 Ω maximum) or if the resistance to ground is greater than Rb_PLUG_ID. Any ID resistance less than Ra_PLUG_ID shall be treated as ID = FALSE and any resistance greater than Rb_PLUG_ID shall be treated as ID = TRUE.Table 5-11. USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly WiringUSB 3.1 Micro-A Plug Wire USB 3.1 Micro-B PlugPin Number Signal Name Wire Number Signal Name Pin Number Signal Name1 VBUS 1 PWR 1 VBUS2 D- 2 D- 2 D-3 D+ 3 D+ 3 D+4 ID (see Note 1) No Connect 4 ID (see Note 2)5 GND 4 GND_PWRrt 5 GND6 MicA_SSTX- 5 P1- 9 MicB_SSRX-7 MicA_SSTX+ 6 P1+ 10 MicB_SSRX+8 GND_DRAIN8 GND_DRAIN 7 and 10 P1_DrainP2_Drain9 MicA_SSRX- 8 P2- 6 MicB_SSTX-10 MicA_SSRX+ 9 P2+ 7 MicB_SSTX+ Shell Shield Braid Shield Shell ShieldNotes:1. Connect to the GND.2. No connect or connect to ground by a resistance greater than 1 MΩ minimum.5.5.5 USB 3.1 Micro-A to USB 3.1 Standard-B Cable AssemblyA USB 3.1 Micro-A to USB 3.1 Standard-B cable assembly is also allowed. Figure 5-18 andFigure 5-16 show, respectively, the USB 3.1 Micro-A cable overmold and the USB 3.1 Standard-B cable overmold dimensions.Table 5-12 shows the wire connections for the USB 3.1 Micro-A to USB 3.1 Standard-B cableassembly.Table 5-12. USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly WiringUSB 3.1 Micro-A Plug Wire USB 3.1 Standard-B Plug Pin Number Signal Name Wire Number Signal Name Pin Number Signal Name1 VBUS 1 PWR 1 VBUS2 D- 2 D- 2 D-3 D+ 3 D+ 3 D+4 ID (see Note 1) No Connect5 GND 4 GND_PWRrt 4 GND6 MicA_SSTX- 5 P1- 8 StdB_SSRX-7 MicA_SSTX+ 6 P1+ 9 StdB_SSRX+7 GND_DRAIN8 GND_DRAIN 7 and 10 P1_DrainP2_Drain9 MicA_SSRX- 8 P2- 5 StdB_SSTX-10 MicA_SSRX+ 9 P2+ 6 StdB_SSTX+Shell Shield Braid Shield Shell ShieldNotes:1. Connect to the GND5.5.6 USB 3.1 Icon LocationUSB 3.1 cable assemblies compliant with the USB 3.1 Connectors and Cable AssembliesCompliance Specification shall display the appropriate USB 3.1 Icon. A dimensioned drawing and allowable usage of the icon are supplied with the license from the USB-IF.The USB 3.1 Icon is embossed in a recessed area on the side of the USB 3.1 plug. This provides easy user recognition and facilitates alignment during the mating process. The USB Icon andManufacturer’s logo should not project beyond the overmold surface. The USB 3.1 compliantcable assembly is required to have the USB 3.1 Icons on the plugs at both ends, while themanufacturer’s logo is recommended. USB 3.1 receptacles should be orientated to allow the Icon on the plug to be visible during the mating process. Figure 5-19 shows a typical plug orientation.Figure 5-19. Typical Plug Orientation5.5.7 Cable Assembly LengthThis specification does not specify cable assembly lengths. A USB 3.1 cable assembly may be of any length as long as it meets all the requirements defined in this specification. The cable assembly voltage drop budget defined in Section 11.4.2 and the cable assembly loss budget defined inSection 5.6.1.3.2, limit the cable assembly length.5.6 Electrical RequirementsThis section covers the electrical requirements for USB 3.1 raw cables, mated connectors, andmated cable assemblies. USB 3.1 signals, known as Enhanced SuperSpeed are governed by this specification. The USB 2.0 signals are governed by the USB 2.0 specification, unless otherwise specified.Compliance to the USB 3.1 specification is established through normative requirements of mated connectors and mated cable assemblies.Enhanced SuperSpeed requirements supporting Gen 2 speed are specified in the frequency domain.Components and assemblies meeting Enhanced SuperSpeed Gen 2 speed electrical requirements do not require separate qualification testing for Gen 1 speed compliance.DC requirements, such as contact resistance and current carrying capability, are also specified in this section.Any informative specification for cable and connector products is for the purpose of designguidelines and manufacturing control.In conjunction with performance requirements, the required test method is referenced for theparameter stated. A list of the industry standards for DC requirements is found in the Section 5.6.2.Additional supporting test procedures are found in the USB 3.1 Connectors and Cable Assemblies Compliance Document.The requirements in the section apply to all USB 3.1 connectors and/or cable assemblies unlessspecified otherwise.5.6.1 Enhanced SuperSpeed Electrical RequirementsThe following sections outline the requirements for SuperSpeed signals.5.6.1.1 Raw CableInformative raw cable electrical performance targets are provided to help cable assemblymanufacturers manage raw cable suppliers. These targets are not part of the USB 3.1 compliance requirements. The mandatory requirements are that the mated cable assembly performancespecified in Section 5.6.1.3 and other tests specified in the USB 3.1 Connectors and CableAssemblies Compliance Document.5.6.1.1.1 Characteristic ImpedanceThe differential characteristic impedance for the SDP pairs is recommended to be90 Ω +/- 5 Ω. The single-ended characteristic impedance of coaxial Enhanced SuperSpeed signalwires is recommended to be 45 Ω +/- 3 Ω. It should be measured with a TDR in a differentialmode using a 200 ps (10%-90%) rise time.5.6.1.1.2 Intra-Pair SkewThe intra-pair skew for the SDP pairs is recommended to be less than 15 ps/m. It should bemeasured with a Time Domain Transmission (TDT) in a differential mode using a 200 ps (10%-90%) rise time with a crossing at 50% of the input voltage.5.6.1.1.3 Differential Insertion LossCable loss depends on wire gauges, plating and dielectric materials. Table 5-13 and Table 5-14show examples of average differential insertion loss for the SDP pairs for Enhanced SuperSpeed Gen 2 speed. To meet the cable assembly differential insertion loss target, support of the Gen 2 speed requires better performance from the raw cable than required for support of the Gen 1 speed.Table 5-13. SDP Differential Insertion Loss Examples for Gen 2 speedFrequency 34AWG 32AWG 30AWG 28AWG0.625 GHz -1.8 dB/m -1.4 dB/m -1.2 dB/m -1.0 dB/m1.25 GHz -2.5 dB/m -2.0 dB/m -1.7 dB/m -1.4 dB/m2.50 GHz -3.7 dB/m -2.9 dB/m -2.5 dB/m -2.1 dB/m5.00 GHz -5.5 dB/m -4.5 dB/m -3.9 dB/m -3.1 dB/m7.50 GHz -7.0 dB/m -5.9 dB/m -5.0 dB/m -4.1 dB/mTable 5-14. SDP Differential Insertion Loss Examples for Gen 2 speed with CoaxialConstructionFrequency 34AWG 32AWG 30AWG 28AWG0.625 GHz -1.6 dB/m -1.3 dB/m -1.1 dB/m -1.0 dB/m1.25 GHz -2.3 dB/m -1.8 dB/m -1.5 dB/m -1.3 dB/m2.50 GHz -3.5 dB/m -2.7 dB/m -2.3 dB/m -1.9 dB/m5.00 GHz -5.3 dB/m -4.2 dB/m -3.5 dB/m -3.1 dB/m7.50 GHz -7.2 dB/m -5.5 dB/m -4.9 dB/m -4.2 dB/m5.6.1.2 Mated Connector ImpedanceSuperSpeed signal routing on the PCB should minimize the stub length and minimize impedance discontinuities in the signal path. It is recommended that the SuperSpeed signals be routed on the opposite side of the PCB from the side the lead is inserted for through-hole implementations. It is recommended that the SuperSpeed signals be routed on the same side of the PCB as the solder pads for SMT implementations.For Enhanced SuperSpeed Gen 2 speed applications, electrical optimization is required to achieve the best performance. The PCB stack up, lead geometry, and solder pad geometry should bemodeled in three dimensions. Example ground voids under pads shown in Figure 5-20 are based on pad geometry, mounting type, and PCB stack up.。