几个常用的Verilog小程序

几个常用的Verilog小程序(1) 8位串并转换module haidaoqi(clk,rst,din,dout);input clk,rst,din;output [7:0] dout;reg[7:0] data,dout;reg[2:0] cnt;always@(posedge clk or posedge rst)if(rst) //复位高有效data <=8'b0;elsedata<= {data[7:0],din};//din是输入串行数据，假设输入数据高位在前//这是一个移位寄存器always@(posedge clk or posedge rst)if(rst)cnt <= 3'b0;elseif(cnt == 3'b111)cnt <= 3'b0;elsecnt <= cnt +1;//计数器，用来计算移位次数，移位8次在以后产生一个有效数据always@(posedge clk or posedge rst)if(rst)dout <= 8'b0;elseif(cnt == 3'b111)dout <= data;//如果计数器记到7，那么输出一个有效的8位数据elsedout <= 0;endmodule(2) 8 位数据寄存器module reg8(out_data,in_data,clk,clr);output[7:0] out_data;input[7:0] in_data;input clk,clr;reg[7:0] out_data;always @(posedge clk or posedge clr)beginif(clr) out_data <=0;else out_data <=in_data;endendmodule(3) 8位数据锁存器module haidaoqi(data_out,data_in,clk,rst); output[7:0] data_out;input[7:0] data_in;input clk,rst;reg[7:0] data_out;always @(rst or clk or data_in)beginif (rst) data_out<=8'b0;else if (clk) data_out<=data_in;else data_out<=8'b0;endendmodule(4) 8位并串转换module haidaoqi(rst,clk,tem,D1);input rst,clk;input [7:0] tem;output D1;reg D1;wire [7:0] tem;reg [2:0] counter;always @(posedge clk or posedge rst) beginif (rst)begincounter<=3'b0;D1<=0;endelse if(counter==7)begincounter<=3'b0;D1<=0;endelsebegincounter<=counter+1;D1=tem[counter];endendendmodule(5) clk一分四/八频module haidaoqi(clk1,clk2,clk,rst);output clk1,clk2;input clk,rst;reg clk1,clk2;reg[7:0] state;parameter S0=8'b00000000,S1=8'b00000001,S2=8'b00000010,S3=8'b00000100,S4=8'b00001000,S5=8'b00010000,S6=8'b00100000,S7=8'b01000000,S8=8'b10000000;always@(posedge clk)if(rst)beginclk1<=0;clk2<=0;state<=S0;endelsebegincase(state)S0:state<=S1;S1:state<=S2;S2:beginclk1<=~clk1;state<=S3;endS3:state<=S4;S4:beginclk1<=~clk1;clk2=~clk2;state<=S5;endS5:state<=S6;S6:beginclk1<=~clk1;state<=S7;endS7:state<=S8;S8:beginclk1<=~clk1;clk2=~clk2;state<=S0;enddefault:state<=S0;endcaseendendmodule(6) 8位比较器module haidaoqi(a,b,en,y);input[width-1:0] a,b;input en;output y;reg y;parameter width=8;always@(a or b)if(en)beginif(a==b)y<=1;elsey<=0;endelsey<=0;endmodule(7)带使能端的rammodule haidaoqi(dataout,datain,ena,read,write); output[7:0] dataout;input[7:0] datain;input ena,read,write;reg[7:0] ram[1:0];parameter addr=1'b0;assign dataout=(read && ena)?ram[addr]:8'hzz;always@(posedge write)beginram[addr]<=datain;endendmodule(8) 译码器module haidaoqi(ma,a,b,c,d,e);input[2:0] ma;output a,b,c,d,e;reg a,b,c,d,e;always@(ma)case(ma)3'b001:{a,b,c,d,e}<=5'b10000;3'b010:{a,b,c,d,e}<=5'b01000;3'b011:{a,b,c,d,e}<=5'b00100;3'b100:{a,b,c,d,e}<=5'b00010;3'b101:{a,b,c,d,e}<=5'b00001;default:{a,b,c,d,e}<=5'bzzzzz;endcaseendmodule(9) 带清0/置1端的T触发器module T-trigger(clk,T,R,S,Q,Q1);input clk,T,R,S;output Q,Q1;reg Q,Q1;always @(posedge clk or negedge R or negedge S) beginif(!R)beginQ <= 1'b0;Q1<=1'b1;endelse if(!S)beginQ <=1'b1;Q1<=1'b0;endelse if(T)beginQ<=~Q;Q1<=~Q1;endendendmodule(10)带起始位识别的串并转换（存8位有效数据）module SIM(din,clk,rst,dout,ok);input din,clk,rst;output ok;output[7:0] dout;reg[7:0] indata_buf,dout;reg[3:0] counter;reg[2:0] state;reg[1:0] cnt;reg tag,ok;integer bitpos=7;parameter s0=0,s1=1,s2=2,s3=3,s4=4;always@(posedge clk or posedge rst)if(rst)beginstate<=0;counter<=0;tag<=0;indata_buf<=8'bz;cnt<=0;bitpos=7;endelse case(state)s0:begintag=0;ok<=tag;if(din)begincnt<=cnt+1;state<=s0;if(cnt==3)beginstate<=s1;cnt<=0;endendelse begincounter<=0;state<=s0;endends1:beginif(counter==7)beginstate<=s2;counter<=0;endelsebegincounter<=counter+1;state<=s0;endends2:if(!din)state<=s3;elsestate<=s0;s3:beginif(bitpos==-1)beginbitpos=7;state<=s4;endelsebeginindata_buf[bitpos]<=din;bitpos<=bitpos-1;state<=s3;endends4:begintag=1'b1;ok<=tag;dout<=indata_buf;state<=s0;endendcaseendmodul(11)移位寄存器（9位有效数据输出）module ywjc(din,clk,rst,dout,ok);input din,clk,rst;output ok;output[8:0] dout;reg[8:0] indata_buf,dout;reg[3:0] counter;reg[2:0] state;reg[1:0] cnt;reg tag,ok;integer bitpos=8;parameter s0=0,s1=1,s2=2,s3=3,s4=4;always@(posedge clk or posedge rst) if(rst)beginstate<=0;counter<=0;tag<=0;indata_buf<=9'bz;cnt<=0;bitpos=8;endelse case(state)s0:begintag=0;ok<=tag;begincnt<=cnt+1;state<=s0;if(cnt==3)beginstate<=s1;cnt<=0;endendelse begincounter<=0;state<=s0;endends1:beginif(counter==8)beginstate<=s2;counter<=0;endelsecounter<=counter+1;state<=s0;endends2:if(!din)state<=s3;elsestate<=s0;s3:beginif(bitpos==-1)beginbitpos=8;state<=s4;endelsebeginindata_buf[bitpos]<=din;bitpos<=bitpos-1;state<=s3;endends4:begintag=1'b1;ok<=tag;dout<=indata_buf;state<=s0;endendcaseendmodule。