序列检测器的设计 实验报告
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EDA实验报告书
END CASE ;
END PROCESS;
REG: PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN ST<=s0;
ELS IF ( CLK'EVENT AND CLK='1') THEN ST<=NST;
END IF;
END PROCESS REG;
SOUT<='1'WHEN ST=s8 ELSE '0' ;
END behav;
仿真波形
图
实验结果LIBRARY ieee;
USE ieee、std_logic_1164、all;
ENTITY SM1 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
input1 : IN STD_LOGIC := '0';
input2 : IN STD_LOGIC := '0';
output1 : OUT STD_LOGIC
);
END SM1;
ARCHITECTURE BEHA VIOR OF SM1 IS
TYPE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,st0);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
BEGIN
PROCESS (clock,reset,reg_fstate)
BEGIN
IF (reset='1') THEN
fstate <= st1;
ELSIF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
END PROCESS;
PROCESS (fstate,input1,input2)
BEGIN
output1 <= '0';
CASE fstate IS
WHEN st1 =>
IF (((input1 = '1') AND (input2 = '1'))) THEN
reg_fstate <= st2;
ELSE
reg_fstate <= st0;
END IF;