dc compact model

DC Compact Model for SOI TunnelField-Effect TransistorsBharat Bhushan,Member,IEEE,Kaushik Nayak,and V.Ramgopal Rao,Senior Member,IEEEAbstract—A physics-based dc compact model for SOI tunnel field-effect transistors(TFETs)has been developed in this paper utilizing Landauer approach.The important transistor electrical parameters,i.e.,threshold voltage V th,charge in the channel Q, gate capacitance C G,drain current I DS,subthreshold swing S, transconductance g m,and output conductance g DS,have been modeled.The model predicts the low subthreshold swing values (less than60mV/dec)observed in TFETs and shows a good match with the technology computer aided design(TCAD)results.Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions,i.e.,40-nm Si nTFET and pTFET,a0.4-μm Si nTFET,and a40-nm Ge nTFET.The compact model predictions are in good agreement with the TCAD simulation results.Index Terms—Band-to-band(BTB)tunneling,compact model, complementary metal–oxide–semiconductor(CMOS),low standby power(LSTP),metal–oxide–semiconductorfield-effect transistor(MOSFET),modeling,TCAD,tunnelfield-effect transistor(TFET),Wentzel,Kramers,and Brillouin(WKB).I.I NTRODUCTIONA S ADV ANCED CMOS technologies are scaled followingMoore’s law,a variety of challenges needs to be overcome to achieve high performance from these technologies.One of these challenges is minimizing the standby power dissipa-tion.As a result,several alternative device structures such as tunnelfield-effect transistors(TFETs)[1],impact ionization MOSFETs[2],MOSFETs with a ferroelectric insulator as a gate oxide[3],green transistors[4],and sandwich tunnel barrier FETs[5]have been proposed in the literature.The TFET is a promising device to replace the traditional MOSFET for low standby power(LSTP)applications[6],[7].While low ON-state current is a significant problem facing these devices,the lack of a good compact model is hampering the circuit simulation activity involving the TFETs,which is the focus of this paper. The analytical modeling has been carried out for a stan-dard silicon-on-insulator(SOI)TFET device structure,which resembles that of a gated p-i-n diode.The Landauer approach has been incorporated to evaluate the transistor current.The structure that we have used for modeling purposes is shown in Fig.1(a)and(b)(nTFET and pTFET).The structure isManuscript received August26,2011;revised May24,2012,June27,2012, and July13,2012;accepted July13,2012.Date of publication July30,2012; date of current version September18,2012.The review of this paper was arranged by Editor H.Shang.B.Bhushan is with the Silicon Systems Group,Chief Technology Officer’s Group,Applied Materials,Singapore506906(e-mail:bharat_ bhushan@).K.Nayak and V.R.Rao are with the Centre of Excellence in Nanoelectron-ics,Department of Electrical Engineering,Indian Institute of Technology Bom-bay,Mumbai400076,India(e-mail:knayak@ee.iitb.ac.in;rrao@ee.iitb.ac.in). Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TED.2012.2209180Fig.1.Structure of TFET(a)NTFET and(b)PTFET.Fig.2.Band-diagrams of NTFET(a)V GS=0and(b)V GS=V DD.a silicon-on-insulator(SOI)nTFET(pTFET)with a heavilydoped degenerate p-type(n-type)source and n-type(p-type)drain,an intrinsic channel,and SiO2as a gate insulator.Thebasic operation of the device can be understood using Figs.2and3.When the applied gate voltage is zero,there is nodirect band-to-band(BTB)tunneling,and the device is in theOFF-state as evident in Figs.2(a)and3(a).There may beindirect trap-assisted tunneling due to existence of traps in theforbidden region of the source,which leads to subthresholdconduction in the device.When we increase the gate voltage,there is a shift in theenergy bands of the channel.After crossing a threshold point 0018-9383/$31.00©2012IEEEFig.3.Band-diagrams of PTFET (a)V GS =0and (b)V GS =−V DD.Fig.4.Band diagrams at (a)V GS =0and (b)V GS =V th .(i.e.,when conduction-band energy of the channel gets aligned with Fermi energy of the source),there is direct BTB tunneling at the source–channel junction,which is shown in Figs.2(b)and 3(b),that causes the device to turn on.Unlike the MOSFET,TFET current is ambipolar in nature.II.T HRESHOLD V OLTAGEConsidering the SOI nTFET structure shown in Fig.1(a),the threshold voltage is defined as the gate voltage at which tunneling starts to occur at the source–channel junction.In other words,threshold voltage is the value of the gate voltage at which the Fermi energy level in the source region (E FS )aligns with the conduction-band energy level in the channel (E CC ).The band diagram between the source and channel regions at different gate bias values is shown in Fig.4.When the appliedgate voltage is equal to the threshold voltage of MOS (V MOSth ),there is an inversion in the channel.The threshold voltage of MOS can be written as [8],[9]V MOSth =Φms −Q ox C ox +4qNiεS ΦB C ox +2ΦB (1)where Φms is the metal-to-semiconductor work function differ-ence,Q ox is the oxide charge,C ox is the oxide capacitance,N iis the doping in the intrinsic region,and ΦB is the difference between the Fermi potential and the intrinsic Fermi potential of the semiconductor.Since,in nTFETs,the source is p +(electrons are minority carriers),a sufficient number of electrons are not presentinFig.5.Band diagram illustrating the phenomena of direct band to band tunneling of electrons at source-channel junction of NTFET due to shift in the bands of the channel at V GS >V th .the source.Therefore,the device is in the OFF -state at V GS =V MOSth.If we further increase the gate voltage beyond the threshold voltage of MOS,there is a downward shift in the bands of channel.At some point,the conduction-band energy of channel gets aligned with the Fermi energy of the source [see Fig.4(b)].This point defines the threshold voltage of TFET.The energy required to shift the bands from the zero gate bias [see Fig.4(a)]to threshold point [see Fig.4(b)]is almost equal to half of the band-gap energy E g .Therefore,the threshold voltage of nTFET can be written asV th =Φms −Q ox C ox +4qN i εS ΦB C ox +2ΦB +E g2q (2)where ΦB =(KT/q )ln(N i /n i ).The overlap of the Fermi level in the source is considered as the onset instead of the valence band of the source because we have taken the degenerate source with the Fermi energy less than or equal to the valence-band energy.Since the difference between the Fermi energy and the valence-band energy of source is almost negligible for the doping levels that we have taken,the onset is meaningful for a wide range of temperatures.In short-channel devices,there is a V th rolloff [8]due to charge sharing with the source–drain.Therefore,the threshold voltage V SCthfor short-channel devices can be written as [8]V SCth =V th −24t oxqN i Ψbi (Ψbi +V DS )4εS ΦBe−πb 2 3t ox + 4εS ΦBqN i (3)where V th is the threshold voltage of the long-channel TFET,t ox is the oxide thickness,Ψbi is a built-in potential between source or drain-to-channel junction.V DS is the drain–source voltage,and L is the channel length of short-channel devices.If we increase the gate voltage beyond the threshold point,there is a further downward shift in the bands of the channel,which is shown in Fig.5.If we define E FS −E CC =qΔφ,then the gate voltage can be written as V GS =V th +ΔΦ(4)where Δφ⎧⎨⎩>0,for V GS >V th =0,for V GS =V th <0,for V GS <V th⎫⎬⎭.III.C HARGE IN THE C HANNELIn this section,we calculate charge in the channel for su-perthreshold and subthreshold regions using tunneling current equations given in [10]–[12].BHUSHAN et al.:DC COMPACT MODEL FOR SOI TFETs2637 Case I—Superthreshold Region(V GS>V th):The currentthrough the device structure is calculated using Kane’s model[10]and the Landauer approach[11].In this case,directBTB tunneling of electrons is possible at the source–channeljunction.The tunneling current of electrons through thesource–channel junction of the nTFET shown in Fig.5can bewritten asI tun=qfW E FSE CCT(E)D2−d(E)v(E)(f s(E)−f c(E))dE.(5)In the given equation,the channel carriers are treated quan-tum mechanically as2-D gas as the carrier motion is confined in the direction normal to the surface.In addition,due to small Si body thickness,we will have high normal electricfield in the channel.Here,q is the electronic charge,and W is the gate width of the device.In literature[10]–[12],the BTB tunneling models take into account1-D density of states D1−d(E),which is a function of energy.In our model[see(5)],the2-D density of states D2−d(E)has been considered,accounting for2-D electron gas in the channel of TFET.The parameter f takes care of the error introduced with this formulation,and its value can be adjusted for different gate and drain biases.The parameter f can be expressed asf=a0+b0+a1V gs+b1V ds(6)where a0,b0,a1,and b1are constants.There are two groups of energy subbands/valleys in the inversion-layer quantum well. The lower valley has twofold degeneracy,and the higher valley has fourfold degeneracy.At room temperature(300K),several subbands in both the valleys are occupied near V th.However, majority of the electrons populate the lowest subband of energy E0,which is the ground state energy in the lower energy valley.Hence,carrier transmission across thefirst energy is considered.Assuming a triangular potential barrier(see Fig.5)at the source–channel junction,the tunneling probability T(E)using Wentzel,Kramers,and Brillouin(WKB)approximation can beexpressed asT(E)=e−βλ(V GS−V MOSth+ΦS)(7)whereβ=4√2m∗E3/2g/3q andλ=2ΦSqN S(Φbi−ΔΦ)−2kTq(8)is the tunneling barrier width or average tunneling thickness.Φbi is the built-in potential barrier at the source–channel junc-tion,and N s is the source doping concentration.Positive values of gate voltage above the threshold voltage causeλto decrease and increases the BTB tunneling of carriers asΔΦ>0.The density of states in two dimensions can be written asD2−d(E)=m∗π 2(9)where m∗is the effective mass of carriers and is the reduced Planck’s constant.The Fermi–Dirac distribution functionof Fig.6.Indirect trap assisted tunneling of electrons at source-channel junction at V GS≤V th.source(f s(E))and channel(f c(E))can be expressed as[9]f s(E)=11+e(E−E FS)KTf s(E)=11+e(E−E FC)KT.(10)Since E CC≤E≤E FSfc(E)≈0.(11) Assume that an average tunneling velocity v(E)of electrons to be constant.The charge in the channel for a superthreshold region can be written asQ=−I tunλv=−q2λm∗π 2W fV t e−βλ(V GS−V MOSth+Φs)ln1+e(V GS−V th)V t2.(12) Case II—Subthreshold Region(V GS≤V th):In this case, direct BTB tunneling of electrons is not possible at the source–channel junction,but there will be indirect trap-assisted tunneling due to existence of traps in the forbidden region of source.Here,if the thermal energy V t=KT/q is greater than or equal to energy barrier E b=E CC−E FS,then electrons jump to the existing traps in the forbidden region,followed by tunneling at the source–channel junction(see Fig.6).The probability of existence of traps in the forbidden region of the source is given as[12]P trap=e(V GS−V th)V∗t(13) where V∗t=nV t=n(KT/q),with n being a positive real number.The probability that the electron will be able to overcome the energy barrier E b is given as[12]P thermal=e(V GS−V th)V t.(14) Multiplying(13)and(14)gives the total probability P of existence of electrons in the forbidden region of source as follows:P=P trap P thermal=e(V GS−V th)V teq(15) where V teq=V t V∗t/(V t+V∗t)=(n/(n+1))V t.The indirect trap-assisted tunneling current at the source–channel junction can be expressed as[10]–[12]I tun=qfW PE FSE CCT(E)D2−d(E)v(E)(f s(E)−f c(E))dE.(16)2638IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.59,NO.10,OCTOBER2012Fig.7.Gate Capacitance as a series combination of C ox and C c .Therefore,charge in the channel for the subthreshold region can be written asQ =−q 2pλm ∗π 2W fV t e−βλ(V GS −V MOS th +Φs ) ln 21+e(V GS −V th )V t .(17)IV .G ATE C APACITANCEThe gate capacitance is a series combination (see Fig.7)of oxide capacitance C ox and channel capacitance C c ,where C c is due to a variation of charges in the channel with gate voltage.The gate capacitance for both superthreshold and subthresh-old regions can be written asC G =dQ m dV GS = dQ ox dV GS +dQ dV GS = dQ dV GS .(18)Case I—Superthreshold Region (V GS >V th ):Differentiat-ing (12)with respect to V GS givesC G =−q 2λm ∗π 2W fV t× e −βλ(V GS −V MOS th +Φs e (V GS −V th )V t V t 1+e(V GS −V th )V t +βλV GS −V MOS th +Φs2×e−βλ(V GS −V MOS th+Φs)ln1+e(V GS −V th )V t2.(19)Case II—Subthreshold Region (V GS ≤V th ):Differentiating (17)with respect to V GS givesC G =q 2P λm ∗π 2W fV t× e −βλ(V GS −V MOS th +Φs e (V GS −V th )V t V t 1+e(V GS −V th )V t +βλV GS −V MOS th +Φs2e−βλ(V GS −V MOS th+Φs ) ×ln 1+e (V GS −V th )V t 2 +q 2P λm ∗π 2W fV t V teq×e−βλ(V GS −V MOS th+Φs)ln1+e(V GS −V th )V t)2.(20)TABLE ID RAIN T HRESHOLD V OLTAGE AT D IFFERENT G ATE V OLTAGES FOR D IFFERENT DEVICESNow,the channel capacitance can be obtained from thefollowing:1C G =1C OX +1C C.(21)V .D RAIN T HRESHOLD V OLTAGEUnlike MOSFET,the TFET has a new region (drain thresh-old region)in its output characteristics,which is observedbefore the linear region.The peak of g DS curve is not at the origin,and it corresponds to a drain threshold voltage of the device.Drain threshold voltage is the value of drain voltage below which the drain current is dominated by reverse-bias p-n junction current at the drain–channel junction.The drain threshold voltage can be extracted from TCAD-simulated out-put characteristics and the output conductance (g DS )curve of the device using peak g DS point method.The numerical values of the drain threshold voltage obtained for different devices using this method are shown in Table I.The drain current for the subdrain threshold region (0≤V DS ≤V Dth )can be written as [9]I DS =Et epi qn 2iN iD n τe 1−e V DS V t+q n i τe 2 si q1N i +1N D (V bi +V DS )(22)where W is the width of the device,D n is the electron diffusioncoefficient,and τe is the minority carrier lifetime of electrons.VI.D RAIN C URRENTIn this section,the drain current has been derived for linear,saturation,and subthreshold regions.Linear Region—V Dth ≤V DS ≤V Dsat and V GS ≥V th :The charge at a point “y ”in the channel can be written asQ (y )=−q 2λm ∗π2W fV t e−βλ(V GS −V MOS th+Φs ) ×ln1+e(V GS −V (y )−V th )V t2.Since 0<V (y)<V dsatln 1+e(V GS −V (y )−V th )V t2≈(V GS −V (y )−V th )V t−ln 2.BHUSHAN et al.:DC COMPACT MODEL FOR SOI TFETs2639 ThereforeQ(y)=−q2λm∗π 2W fV t e−βλ(V GS−V MOSth+Φs)×(V GS−V th−V t ln2−V(y))(23)I DS=Q(y)t=Q(y)v(ξy)y=Q(y)μξyy=−Q(y)μydVdy(24)L0I DS ydy=V DS−V Dthμq2λm∗L2π 2W fe−βλ(V GS−V MOSth+Φs)×V GS−V th−V t ln2−V(y)dVI DS=2μq2λm∗L2π 2fW e−βλ(V GS−V MOSth+Φs)×(V GS−V th−V t ln2)(V DS−V Dth)−(V DS−V Dth)22.(25)If we take the effective mobility and velocity saturation[8],[9] into account,the drain current can be written asI DS=2μeff1+V DSLξcq2λm∗L2π 2fW e−βλ(V GS−V MOSth+Φs)×(V GS−V th−V t ln2)(V DS−V Dth)−(V DS−V Dth)22.(26)Saturation Region—V Dsat≤V DS≤V DD and V GS≥V th: Ideally,in the saturation region,the drain current is independent of drain voltage because there is no barrier for the electrons to overcome at the channel–drain junction.In this region,the drain current depends upon the number of electrons available in the channel.Differentiating(25)and equating it to zero will give saturation drain voltage V Dsat,and substituting V Dsat in(25) gives saturation drain current I Dsat as shown in the following:V Dsat=V Dth−V GS−V th−V t ln2(27)I Dsat=μq2λm∗L2π 2fW e−βλ(V GS−V MOSth+Φs)×(V GS−V th−V t ln2)2.(28) In this region,saturated drain current is derived using a general expression of drain current i.e.,(25);therefore,the charge term is not used in the derivation.Subthreshold Conduction—V GS<V th:In the subthreshold region,gate voltage is less than threshold voltage,and the drain current is dominated by diffusion,which can be expressed asI DS=−qAD ndndy=qAD nn(0)−n(L)L=−AD nQ(0)−Q(L)LV ch(29)where D n is a diffusion coefficient of electrons,A is a cross section of currentflow,Q(0)is the charge at y=0,Q(L)is the charge at y=L,and V ch is a volume of channelQ(0)=−q2λm∗π 2W fV t e(V GS−V th)V teq e−βλ(V GS−V MOSth+Φs)×ln21+e(V GS−V th)V tln21+e(V GS−V th)V t≈ln2Q(0)=−q2λm∗π 2W fV t ln2e(V GS−V th)V teq e−βλ(V GS−V MOSth+Φs)×Q(L)≈0(30) I DS=q2λm∗L2π 2D n W fV t ln2e(V GS−V th)V teq×e−βλ(V GS−V MOSth+Φs).(31)VII.S UBTHRESHOLD S WINGThe subthreshold swing S is defined as the gate voltage swing needed to reduce the subthreshold drain current by1dec. It is expressed asS=d(log I DS)dV GS−1=ln101V teq+βλ(V GS−V MOSth+Φs)2.(32)Unlike the MOSFET,in the TFET,S is a function of V GS. Hence,we take its average in the interval0≤V GS≤V th to get an average subthreshold swing S avg,i.e.,S avg=1(V th−0)V thSdV GS=n(n+1)V t ln10−ln10√βλV thn(n+1)32tan−1×⎛⎝V thβλn(n+1)V tΦs−V MOSth2+V thΦs−V MOSth+βλn(n+1)V t⎞⎠(33)where S avg is a strong function of the parameter“n”(a positive real number).ThereforeS avg<n(n+1)V t ln10≤V t ln10=60mVdecat room temperature.2640IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.59,NO.10,OCTOBER2012Fig.8.Structure of 40nm NTFET generated using TCAD SENTAURUS.VIII.T RANSCONDUCTANCE AND O UTPUT C ONDUCTANCE The transconductance g m and output conductance g DS are obtained by differentiating drain current with respect to gate voltage and drain current.Thereforeg sat m=dI Dsat dV GS =μq 2λm ∗L 2π 2W fe−βλ(V GS −V MOS th +Φs ) ×(V GS −V th −V t ln 2)×2+(V GS −V th −V t ln 2)βλV GS −V MOS th +Φs2 .(34)Similarly,in the subthreshold region,it can be written as g subm =I S e(V GS −V offset −V th )V teq−βλ(V GS −V MOS th+Φs)×1V teq+βλV GS −V MOS th +Φs2g DS =dI D dV DS=2μq 2λm ∗L 2π2W fe−βλ(V GS −V MOS th +Φs )×((V GS −V th −V t ln 2)−V DS ).(35)IX.R ESULTSIn order to check the accuracy of our model,TCAD sim-ulations were carried out for three different SOI devices:40-nm Si nTFET and pTFET,0.4μm Si nTFET and pTFET,and 40-nm Ge nTFET and pTFET.We have taken a standard TFET structure with abrupt source–channel and drain–channel junctions,as shown in Fig.8.Some of the important physical parameters used are the following:average tunneling thickness λ;parameter f introduced in Section III;life times of electrons and holes τe and τh ,respectively;and the parameter n defined in Section III.Average tunneling thickness and parameter n are the functions of gate voltage,f is a function of both gate and drain voltages,and the life times of electrons and holes are the functions of drain voltage.The numerical values of these parameters have to be adjusted depending upon the gate and drainbiases.Fig.9.Modeled and TCAD simulated drain current (on both log and linearscale)as a function of gate voltage at |V DS |=1.0V for 40nm NTFET andPTFET.Fig.10.Modeled and TCAD simulated drain current as a function of drainvoltage at different gate bias for 40nm NTFET and PTFET.The parameter n is a ratio of temperatures (i.e.,T ∗/T ;T ∗is related to kT ∗,which is the slope of the tail-like distribution of traps in the forbidden region,and T is the lattice temperature).The probability of trap-assisted tunneling changes with the shift in energy bands of the channel region with the variation in V gs .Therefore,different regions of the distributed trap energy values are in alignment with the empty energy states in the conduction band of the intrinsic channel region.Therefore,in order to account for the variation of slope of the trap energy distribution in different regions within the band gap,the values of n are different for different values of V gs up to the threshold voltage.Similarly,the carrier life times of electrons and holes τe and τh change with the carrier injection levels across the drain–channel junction.With the variation of injection levels (high or low)with the drain voltage,the carrier lifetimes are adjusted accordingly.Our model shows a good match with the TCAD simulations for different device structures and parameters,as shown in Figs.9–16.In subthreshold conduction,trap-assisted tunneling has been included in the simulation.In the TCAD simulations,traps (electron and hole traps and fixed charges)are coupled to nearby interfaces and contacts via tunneling models.In the device simulations,nonlocal tunneling models have been considered.These models consider nonlocal tunneling to traps as the sum of an inelastic phonon-assisted process and an elasticBHUSHAN et al.:DC COMPACT MODEL FOR SOI TFETs2641Fig.11.Modeled and TCAD simulated drain current (on both log and linear scale)as a function of gate voltage at V DS =1.0V for three different devicesnamely 40nm Ge NTFET,40nm Si NTFET and 0.4μmNTFET.Fig.12.Modeled and TCAD simulated drain current as a function of drain voltage at V GS =1.0V for three different devices namely 40nm Ge NTFET,40nm Si NTFET and 0.4μmNTFET.Fig.13.Modeled and TCAD simulated trans-conductance as a function of gate voltage at |V DS |=1.0V for 40nm NTFET and PTFET.process.In the inelastic process,transmission probability is computed at the tunneling energy E CC +kT n /2.For elastic process,the computation is done at energy E trap (for the process parameters,see Table II).The electrical quantities of different TFETs obtained from their transfer and output characteristics predicted by thepro-Fig.14.Modeled and TCAD simulated output-conductance as a function of drain voltage at different gate bias for 40nm NTFET andPTFET.Fig.15.Modeled and TCAD simulated trans-conductance as a function of gate voltage at V DS =1.0V for three different devices namely 40nm Ge NTFET,40nm Si NTFET and 0.4μmNTFET.Fig.16.Modeled and TCAD simulated output-conductance as a function of drain voltage at V GS =1.0V for three different devices namely 40nm Ge NTFET,40nm Si NTFET and 0.4μm NTFET.posed model are shown in Table III.The threshold voltage of the 0.4-μm nTFET is higher than that of the 40-nm nTFET,as evident from the short-channel effects [8].The average subthreshold swing of the 0.4-μm TFET is lower than that of2642IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.59,NO.10,OCTOBER 2012TABLE IIP ROCESS P ARAMETERS OF S IMULATED 40-nmnTFETTABLE IIIE LECTRICAL Q UANTITIES OF D IFFERENT D EVICESF ROM THE M ODEL AT |V DS |=1Vthe 40-nm nTFET because of better gate control (electrostat-ics)in long-channel devices,compared with the short-channel devices.The OFF -state current of the 0.4-μm nTFET is lower than that of the 40-nm nTFET because of a lower average subthreshold swing and higher threshold voltage in the 0.4-μm nTFET compared with that of the 40-nm nTFET for the same technology parameters.Similarly,the higher threshold voltage values for the 40-nm pTFET compared with that of the 40-nm nTFET is due to the positive oxide charge values that have been considered in our model.ON -state and OFF -state currents of the pTFET are lower compared with that of the nTFET because mobility and diffusion coefficient values for holes are less than that for electrons,and the pTFET has a higher threshold voltage compared to that of the nTFET.The threshold voltage of the 40-nm Ge nTFET is lower compared with that of the 40-nm Si nTFET because Ge has a lower band gap compared with Si.Lower threshold voltage implies a lower subthreshold swing,which can be seen from the model (33).The OFF -state current of Ge nTFET is higher compared with the Si nTFET because Ge nTFET has a lower threshold voltage compared with the Si nTFET.X.C ONCLUSIONWe have developed a physics-based analytical model for TFET circuit applications using the Landauer approach.The dc compact model predictions of important electrical parameters have a good match with the state-of-the-art TCAD simula-tion results.The model predicts subthreshold swing (S avg )values lower than the thermal limit at room temperature,i.e.,60mV/dec.The lowest S avg value (39mV/dec)has been pre-dicted for the 40-nm-gate-length Ge nTFET.We also show from the analytical modeling results that an I ON /I OFF exceeding 1012can be achieved with TFETs,as predicted by TCAD simulations.A CKNOWLEDGMENTWe would like to acknowledge the CMOS group in the Centre of Excellence in Nanoelectronics (CEN),Department of Electrical Engineering,IIT Bombay for the fruitful discussions.R EFERENCES[1]W.Y .Choi, B.-G.Park,J. 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