NEC_USB PCB guideline

USB 2.0 PCB Board Layout GuidelineRevision 0.9 6/04/01This document shows guideline to design board using NEC USB2.0 devices. This guideline is our recommendation and NEC do not guarantee.1. USB2.0 signal integrity guidelinesa. Limit the trace length of USB D+ and D- from USB2.0 chip to USB receptaclesb. Keep traces of USB bus D+ and D- in the same length. The difference between D+ and D-should be at least less than 0.5mmc. In considering the distance between each layer, trace width of D+/D-, and trace pitchbetween D+ and D-, it is necessary to achieve 90 ohm differential characteristic impedance.d. Common mode trace impedance for D+ and D- should be kept at 45 ohme. Maintain parallelism between D+ and D- thru out the route from USB2.0 chip to receptaclesf. Prevents right-angle bended trace in minimizing trace length between USB2.0 chip toreceptacles. If it becomes necessary to turn 90 degree, should use two 45 degree turns or arc instead of making a single 90 degree turns.g. Maximize the distance between each trace pair of D+ and D-h. Minimize the red traces around Rs resister as shown in Fig1 and Fig2.i. Do not route USB2.0 D+ and D- over the power plane splitj. It is preferred to route USB2.0 D+ and D- on top layer to avoid via on trace USB2.0 D+ and D- between USB2.0 chip to receptacles.k. Route USB2.0 D+ and D- using minimum of vias and corners. This reduces signal reflections and impedance changes.l. Do not put copper pour close to USB2.0 D+ and D- signal since it may affect the impedance of that. But it is preferred to put copper pour along all edge of the board for FCC compliance.m. Maximize the distance between D+ and D- pair from other signalsn. The preferred layer stack is:Signal layer 1 Signal layer 1Ground PowerPower GroundSignal layer 2 Signal layer 2USB2.0 D+/D- route on signal layer 1 USB2.0 D+/D- route on signal layer22. Power supplya. Traces that supply USB 5V bus power should be wide and thick enough for the currentconsumption of the number of ports implemented. The worst case assumption should bemade that one of the ports may be in over current condition (depends on when over currentsensor trips) while others are drawing maximum current consumption (500mA).b. Add ferrite bead to the Vbus power for reducing noise supply to the busc. Power and ground layer should be adjacent to each other in order to prevent big currentloops and noise.3. Analog VDDa. Prepare special Analog VDD that is only used for analog circuit of USB2.0 devices. Separateanalog VDD field and digital VDD field. In achieving this separation using same layer,separate the field on it.b. AVDD and PVDD pin of our devices must be connected with analog VDD field.c. Connect digital VDD and analog VDD via the inductor or the resister as shown Fig 3. Ifinductors are used in analog filtering to analog power of USB2.0 chip, they should be placed away from one other. And also prevent the resonance problem between board capacitanceand inductor. If you use resister to connect between digital VDD and analog VDD, you should use less than 3ohm resister.4. Analog VSSa. Preparing special Analog VSS that is only used for analog circuit of USB2.0 devices will bemore effective. This means separating analog VSS from digital VSS.b. In that case, AVSS pin, PVSS pin, and 9.1kohm resister (with 1% precision) should beconnected with this Analog VSS field.c. In case not separating analog VSS and digital VSS, it is desirable to locate AVSS pin, PVSSpin, and 9.1kohm resister (1% precision) not affected with any noise from digital VSS.d. Connect digital VSS and analog VSS via the inductor or the resister as shown Fig 3. Ifinductors are used in analog filtering to analog power of USB2.0 chip, they should be placed away from one other. And also prevent the resonance problem between board capacitanceand inductor. If you use resister to connect between digital VDD and analog VDD, you should use less than 3ohm resister.5. Decoupling capacitora. Mount enough decoupling capacitors between digital VDD and VSS. These should belocated nearby USB2.0 devices. It may be effective to mount these capacitors on oppositeside.b. Use surface-mount configurations using wide and squat mounting pads with vias jammed upnext to the pads without traces. Vias should have big holes.c. Use more bypass capacitorsd. Mount at least one 10uF capacitor and several pieces of 0.1uF and 0.01uF capacitorbetween analog VDD and analog VSS. These should be located nearby USB2.0 devices.e. Do not use electrolytic capacitors as decoupling capacitors, but use tantalum capacitors orceramic capacitors, which have good performance under high frequency.6. EMI ProtectionAccording to our test result, does not need common mode choke coil for EMI protection. But if you want to use it, this may degrade USB signaling waveform, so you must take care its feature when you select the common mode choke coil.7. USB cable and receptacleUse USB2.0 compliance components such as USB receptacles on the PCB, and USB cables8. PCI USB Host Controller add-in CardLimit the length from USB2.0 host controller chip to PCI connector with PCI specification.Fig2 downstream portless than 3 ohm。