Structural parameters for the M31 dwarf spheroidals

合集下载

国内外标准对照

国内外标准对照
G3460
A333-1.6
TT St35N
1.0356
SEW680
15MnV
STBL39
G3464
A334-1.6
09Mn2V
A333-7.9
A334-7.9
TT St35N
1.0356
SEW680
(06A1NbCuN)
STPL46
STBL
G3460
G3464
A333-3.4
A334-3.4
10Ni14
A106-A
St37-2
1.0112
DIN17175
STS38
G3455
St35.8
St35.4
1.0305
1.0309
DIN1629/4
STB30
G3461
A179-C
A214-C
St35.8
1.0305
DIN17175
STB33
G3461
A192
A226
St35.8
1.0305
DIN17175
STB35
适用于石油精炼厂的炉管、热交换器管和管道 Furnace tubes heat exchanger tubes and pipeline used in petroleum refinery
7
化肥设备用高压无缝钢管 Hign-pressure seamless steel pipe for chemical fertilizer equipments
20,35,45,27SiMn
GB/T 17396
(neq DIN 1629)
适用于制造液压支架和支柱的缸、柱用热轧无缝钢管 For hydraulic pillar.

ITTC - Recommended Procedures and Guidelines

ITTC - Recommended Procedures and Guidelines

7.5 – 02 05 – 06 Page 2 of 5
Effective Date Revision
1999
00
High Speed Marine Vehicles: Structural Loads
1 PURPOSE OF PROCEDURE
To describe model test for prediction structural loads on high speed marine vehicles.
2.2 Structural Loads
The dimensioning of large high speed vehicles demands a knowledge and methods to determine the limiting environmental loads, operational aspects and structural strength. To achieve good design load predictions, appropriate model test techniques must be developed. Model tests are also required for verification and calibration of theoretical methods and numerical codes.
Effective Date Revision
1999
00
2.2.1 Local Loads
For the local problem the slamming force is the most important load contribution. Firstly, one should not consider point pressures, but rather forces on a sensibly chosen area, e.g. a single plating field (Carcaterra & Ciappi, 1998, Carcaterra et al., 1999). The dynamic behaviour of the elastic plate is governed by the structural properties of the plating (including longitudinal stiffeners between two transverse frames). The global response of the ship will serve as input to the problem defining the relative speed and orientation of the local area of interest during the impact with the waves. For flat-bottom slamming, and wet-deck slamming of multi-hulls, hydro elasticity is crucial for the magnitude of the slamming loads. Testing is done either with the dynamic behaviour correctly modelled, or the results are used solely to document the occurrence of slamming, not the magnitude of the forces. For bow slamming, and slamming on surfaces with a dead rise angle of more than approximately 15°, hydroelastic effects are less important and testing can be performed without modelling the local structural dynamics (Faltinsen, 1998). Forces can be measured by means of a suitably sized panel mounted on a strain-gauge arrangement. The panel should be stiffly mounted in order to avoid artificial hydroelastic effects.

基于AASHTO规范的混凝土桥梁上部结构设计

基于AASHTO规范的混凝土桥梁上部结构设计

第3期(总第263期)域命i祈5衫決2021 年 3 月U R B A N R O A D S B R ID G E S &FL O O D C O N T R O L桥梁结构D O I:10.16799/ki.csdqyfh.2021.03.018基于A A S H T O规范的混凝土桥梁上部结构设计韩雄刚(中国市政工程华北设计研究总院有限公司,天津市300000)摘要:在美国公路桥梁设计规范“AASHTO LRFD Bridge Design Specifications 2017-8th Edition”的基础上,采用 美国本土桥梁设计软件CSI Bridge,从强度极限状态、使用极限状态、疲劳极限状态等方面介绍了混凝土桥梁上部结 构的设计验算。

关键词:AASHTO LRFD;CSI Bridge;极限状态;桥梁上部结构中图分类号:U441 文献标志码:A文章编号:1009-7716(2021 )03-0059-030引言美国公路桥梁设计规范AASHTO LRFD BridgeDesign Specifications 2017-8th E d itio n(简称A A S H-TO L R F D规范)为目前现行美国桥梁设计的最新规范,相比之前版本有较大变化,我国现行《公路钢筋混凝土及预应力混凝土桥涵设计规范》(JT G3362—2018)许多条文均参考了AASHTO L R F D规范。

很 多国内设计院对于按照AASHTO L R F D规范设计桥 梁还比较陌生,且用美标设计桥梁存在许多难点。

本 文通过按美标设计T梁的流程来介绍AASHTO L R F D规范,以期为国内设计院走出国门、承揽按美 标设计的桥梁项目提供技术参考和借鉴。

1工程概况本工程为某高速公路项目,标准跨径以30 m简 支结构为主,上部结构采用预应力混凝土T梁,桥梁 全宽20.56 m,横桥向由6片中梁和2片边梁组成,横 向设置2道端横隔板和3道中横隔板,间距7.04 m。

USB Type-C 规范1.2(中文版)

USB Type-C 规范1.2(中文版)
INTELLECTUAL PROPERTY DISCLAIMER
知识产权声明
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
预发行行业审查公司提供反馈
Revision History.......................................................................................................................14
LIMITED COPYRIGHT LICENSE: The USB 3.0 Promoters grant a conditional copyright license under the copyrights embodied in the USB Type-C Cable and Connector Specification to use and reproduce the Specification for the sole purpose of, and solely to the extent necessary for, evaluating whether to implement the Specification in products that would comply with the specification.

安世亚太培训资料—ANSYS WORKBENCH 11.0 培训教程 第三章 通用前处理

安世亚太培训资料—ANSYS WORKBENCH 11.0 培训教程 第三章 通用前处理

注意在零件之间网格没有匹配上。 存在六面体单元和四面体单元的混signSpace Entra De si gnS pa ce P rofe ssiona l S tru ctu ra l M e cha nica l/M ulti physics
Availability
Availability x x x x x
B. 接触
• 当存在很多零件时,需要定义零件之间相互关 系。
– 接触区域定义了实体或壳如何相互影响。 – 点焊提供了定义壳组件的方法。
• 如不进行接触和点焊设置,那么零件之间就没有 相互关系。
– 在结构分析中,接触和点焊能阻止零件之间的穿 透,同时也提供了零件之间载荷传递的方法。
A vailabilit y x
… 材料属性
• 为体添加材料属性,从目录树中选取 体,然后在下拉菜单中选取 “Material”
– 材料可以从外部的 XML 文件选取 – 新的材料数据可以在“Engineering Data”下添
加和输入。然后新的材料就可以从下拉菜单 中得到。 – 对于 surface bodies, 如上所讲,定义一个厚 度是必要的。
x x x x
… 实体体素接触
• 在“contact”分支点击某个接触域,构成这个接触的零 件就会变成透明的,以便观察。
– 选取一个接触对,接触区域就变成透明的并不包括其它的部 分。
– 透明度可以通过 “Tools > Options… > Simulation:Contact: Transparency”控制. 在“Contact” 分支的Detail view中可以关 掉透明显示
– Surface bodies 被划分成线性壳单元。 – 对于结构分析,每个节点上有三个平动自由度和三个转动自由

MicroDIMM设计规范

MicroDIMM设计规范

4.20.12 - 214-Pin DDR2 SDRAM Unbuffered MicroDIMM DesignSpecificationPC2-4200/PC2-3200 DDR2 Unbuffered MicroDIMM Reference Design SpecificationRevision 0.526,April, 2004Contents1. Product Description (3)Product Family Attributes (3)Raw Card Summary (3)2. Environmental Requirements (4)Absolute Maximum Ratings (4)3. Architecture (4)Pin Description (4)Input/Output Functional Description (5)DDR2 SDRAM MicroDIMM Pinout (6)Block Diagram x16 2Ranks Raw Card A (7)Block Diagram x16 1Rank Raw Card B (8)4. Component Details (9)x16 Ballout for 256Mb, 512Mb, 1Gb, 2Gb and 4Gb DDR2 SDRAMs (Top View) (9)DDR2 SDRAM FBGA Component Specifications (9)Reference SPD Component Specifications (9)SPD Component DC Electrical Characteristics (9)5. Unbuffered MicroDIMM Details (10)DDR2 SDRAM Module Configurations (Reference Designs) (10)Input Loading Matrix (10)DDR2 MicroDIMM Gerber File Releases (11)Example Raw Card Component Placement (12)6. MicroDIMM Wiring Details (13)Signal Groups (13)General Net Structure Routing Guidelines (13)Explanation of Net Structure Diagrams (13)Differential Clock Net Structures (14)Data Net Structures (16)Control Net Structures S[1:0], CKE[1:0], ODT[1:0] (18)Address/Control Net Structures Ax, BAx, RAS, CAS, WE (19)Cross Section Recommendations (21)Test Points (22)7. Serial Presence Detect Definition (23)Serial Presence Detect Data Example (23)8. Product Label (26)9. MicroDIMM Mechanical Specifications (27)1. Product DescriptionThis reference specification defines the electrical and mechanical requirements for the PC2-4200 memory module, a 214-pin, 267 MHz clock (533 MT/s data rate), 64-bit wide, Unbuffered Synchronous Double Data Rate 2(DDR2) DRAM Micro Dual In-Line Memory Module (DDR2 SDRAM MicroDIMMs). It also defines a slower version, the PC2-3200, using 200MHz clock (400 MT/s data rate) DDR2 SDRAMs. These DDR2 SDRAM MicroDIMMs are intended for use as main memory when installed in systems such as mobile per-sonal computers.Reference design examples are included which provide an initial basis for Unbuffered MicroDIMM designs. Any modifications to these reference designs must meet all system timing, signal integrity and thermal requirements for 267 MHz clock rate support. Other designs are acceptable, and all Unbuffered DDR2MicroDIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design.Raw Card SummaryProduct Family AttributesAttribute:Values:Notes:MicroDIMM Organizationx 64MicroDIMM Dimensions (nominal)30 mm high, 54.0mm wide MicroDIMM Types Supported Unbuffered Pin Count214SDRAMs Supported 256 Mb, 512 Mb, 1 Gb, 2 Gb, 4 GbCapacity128 MB, 256 MB, 512 MB, 1 GB, 2GB, 4 GB Serial Presence DetectConsistent with JEDEC Rev. 1.0Voltage Options, Nominal1.8 V V DD 1.8 V V DD Q1.8 V to 3.3 V V DD SPD 1InterfaceSSTL_18Note 1: V DD SPD is not tied to V DD or V DD Q on the DDR2 MicroDIMM.Raw CardNumber of DDR2 SDRAMsSDRAM OrganizationNumber of RanksA 8x162B4x1612. Environmental RequirementsPC2-4200 DDR2 SDRAM Unbuffered MicroDIMMs are intended for use in mobile computing environments that have limited capacity for heat dissipation.3. ArchitectureAbsolute Maximum RatingsSymbol ParameterRating Units Notes T OPR Operating Temperature (ambient) 0 to +65°C 1H OPR Operating Humidity (relative) 10 to 90%1T STG Storage Temperature-50 to +100°C 1H STGStorage Humidity (without condensation) 5 to 95%1Barometric Pressure (operating & storage)105 to 69kPa1, 21.Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2.Up to 9850 ft.Pin DescriptionCK[1:0] Clock Inputs, positive line 2 DQ[63:0] Data Input/Output 64CK[1:0]Clock inputs, negative line 2DM[7:0] Data Masks 8CKE[1:0]Clock Enables 2DQS[7:0]Data strobes8RAS Row Address Strobe 1DQS[7:0]Data strobes complement8CAS Column Address Strobe 1WE Write Enable 1NC,TESTLogic Analyzer specific test pin (No connecton MicroDIMM1S[1:0]Chip Selects2A[9:0],A[15:11]Address Inputs15V DD Core and I/O Power 15A10/AP Address Input/Autoprecharge 1V SS Ground56BA[2:0] SDRAM Bank Address 3V REF Input/Output Reference 1ODT[1:0]On-die termination control2V DD SPD SPD Power1SCL Serial Presence Detect (SPD)Clock Input1RFU Reserved for future use 12 SDA SPD Data Input/Output 1 NCNo connect4SA[1:0]SPD address2Total:214Input/Output Functional DescriptionSymbol Type Polarity FunctionCK0/CK0, CK1/CK1InputCrosspointThe system clock inputs. All address and command lines are sampled on the cross point of therising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from theclock inputs and output timing for read operations is synchronized to the input clock.RFU pins for 2 CK pairs reserved.CKE[1:0]Input Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. RFU pins for 2 CKEs reserved.S[1:0]Input Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the com-mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical banks". RFU pins for 2 Ss reserved.RAS, CAS,WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK CAS, RAS, and WE define the operation to be executed by the SDRAM.BA[2:0]Input—Selects which DDR2 SDRAM internal bank of four or eight is activated.ODT[1:0]Input Active High Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2SDRAM mode register. RFU pins for 2 ODTs reserved.A[9:0],A10/AP, A[15:11]Input—During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle,defines the column address when sampled at the cross point of the rising edge of CK and fall-ing edge of CK. In addition to the column address, AP is used to invoke autoprecharge opera-tion at the end of the burst read or write cycle. If AP is high, autoprecharge is selected andBA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During aPrecharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) toprecharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAninputs. If AP is low, then BA0-BAn are used to define which bank to precharge.DQ[63:0]In/Out—Data Input/Output pins.DM[7:0]Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.DQS[7:0], DQS[7:0]In/Out CrosspointThe data strobes, associated with one data byte, sourced with data transfers. In Write mode,the data strobe is sourced by the controller and is centered in the data window. In Read mode,the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the datawindow. DQS signals are complements, and timing is relative to the crosspoint of respectiveDQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signalsmust be tied on the system board to VSS and DDR2 SDRAM mode registers programmedappropriately.V DD, V DD SPD,V SSSupply—Power supplies for core, I/O, Serial Presence Detect, and ground for the module.SDA In/Out—This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to V DD to act as a pull up.SCL Input—This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-nected from SCL to V DD to act as a pull up.SA[1:0]Input—Address pins used to select the Serial Presence Detect base address. RFU pins for 2nd SPD reserved.NC,TEST In/Out—The TEST pin is reserved for bus analysis tools and is not connected on normal memory mod-ules (MicroDIMMs)..DDR2 SDRAM MicroDIMM PinoutPin #LowerSidePin#UpperSidePin#LowerSidePin#UpperSidePin#LowerSidePin#UpperSidePin#LowerSidePin#UpperSide1V REF108V SS28DQS2135Vss55BA0162BA182DQ43189DQ47 2V SS109DQ429Vss136DQ2856WE163RAS83V SS190V SS 3DQ0110DQ530DQ18137DQ2957V DD164V DD84DQ48191DQ52 4DQ1111V SS31DQ19138Vss58RFU(S2)165S085DQ49192DQ535V SS112DM032Vss139DQS359RFU(ODT2)166ODT086V SS193V SS6DQS0113V SS33DQ24140DQS360CAS167A1387RFU(CK3)194CK17DQS0114DQ634DQ25141Vss61V DD168V DD88RFU(CK3)195CK18V SS115DQ735Vss142DQ3062S1169RFU(S3)89V SS196V SS9DQ2116V SS36DM3143DQ3163ODT1170RFU(ODT3)90DM6197DQS610DQ3117DQ1237Vss144Vss64V DD171V DD91V SS198DQS6 11V SS118DQ1338DQ26145NC,TEST65NC172NC92DQ50199V SS 12DQ8119V SS39DQ27146V DD66V SS173V SS93DQ51200DQ54 13DQ9120DM140Vss147CKE167DQ32174DQ3694V SS201DQ5514V SS121V SS41NC148RFU(CKE3)68DQ33175DQ3795DQ56202V SS15RFU(CK2)122CK042V DD149V DD69V SS176V SS96DQ57203DQ6016RFU(CK2)123CK043CKE0150A1570DQS4177DM497V SS204DQ6117V SS124V SS44RFU(CKE2)151A1471DQS4178V SS98DQS7205V SS18DQS1125DQ1445V DD152V DD72V SS179DQ3899DQS7206DM7 19DQS1126DQ1546BA2153A1273DQ34180DQ39100V SS207V SS 20V SS127V SS47A11154A974DQ35181V SS101DQ58208DQ62 21DQ10128DQ2048A7155A875V SS182DQ44102DQ59209DQ63 22DQ11129DQ2149V DD156V DD76DQ40183DQ45103V SS210V SS 23Vss130Vss50A5157A677DQ41184V SS104SDA211SA0 24DQ16131DM251A4158A378V SS185DQS5105SCL212RFU(*1) 25DQ17132Vss52A2159A179DM5186DQS5106NC213SA1 26Vss133DQ2253V DD160V DD80V SS187V SS107V DD SPD214RFU(*2) 27DQS2134DQ2354A10/AP161A081DQ42188DQ46Note: NC = No Connect; NC,TEST(pin 145) is for bus analysis tool and is not connected on normal memory modules. (*1) = SA0 for 2nd SPD, (*2) = SA1 for 2nd SPD.Block Diagram: Raw Card Version A (Populated as 2 ranks of x16 SDRAMs)Block Diagram: Raw Card Version B (Populated as 1 rank of x16 SDRAMs)#Unless otherwise noted, resistorand V DD Q values are 22 Ω ± 5%DQ wiring may differ from that described in this drawing;however, DQ/DM/DQS/DQS relationships are maintained as shown8pFLoad CapacitorsA0-AN RAS CAS WEmatching on ± 0.5pFBA0-BA23.0Ω±5%4. Component Detailsx16 Ballout for 256Mb, 512Mb, 1Gb, 2Gb and 4Gb DDR2 SDRAMs (Top View) 123789NC NC A NC NCBCVDD NC VSS D VSSQ UDQS VDDQ UDQ6VSSQ UDM E UDQS VSSQ UDQ7 VDDQ UDQ1VDDQ F VDDQ UDQ0VDDQ UDQ4VSSQ UDQ3G UDQ2VSSQ UDQ5VDD NC VSS H VSSQ LDQS VDDQ LDQ6VSSQ LDM J LDQS VSSQ LDQ7 VDDQ LDQ1VDDQ K VDDQ LDQ0VDDQ LDQ4VSSQ LDQ3L LDQ2VSSQ LDQ5 VDDL VREF VSS M VSSDL CK VDD CKE WE N RAS CK ODT BA2BA0BA1P CAS CSA10A1R A2A0VDD VSS A3A5T A6A4A7A9U A11A8VSS VDD A12A14V A15A13WYNC NC AA NC NCDDR2 SDRAM FBGA Component SpecificationsThe DDR2 SDRAM components used with this DIMM design specification are intended to be consistent with JEDEC MO-207 DK-Z and DL-Z.Reference SPD Component SpecificationsThe Serial Presence Detect EEPROMs have their own power pin, V DD SPD, so that they can be programmed or read without powering up the rest of the module. The wide voltage range permits use with 1.8V, 2.5V or 3.3V serial buses.SPD Component DC Electrical CharacteristicsSymbol Parameter Min Max UnitsV DD SPD Core Supply Voltage 1.7 3.6V5. Unbuffered MicroDIMM DetailsDDR2 SDRAM Module Configurations (Reference Designs)Raw Card MicroDIMMCapacityMicroDIMMOrganizationSDRAMDensitySDRAMOrganization# ofSDRAMs# ofRanksSDRAMPackage Type# of banks inSDRAM# Address bitsrow/colA256 MB32 M x 64256 Mbit16 M x 1682FBGA413/9 A512 MB64 M x 64512 Mbit32 M x 1682FBGA413/10 A 1 GB128 M x 64 1 Gbit64 M x 1682FBGA813/10 A 2 GB256 M x 64 2 Gbit128 M x 1682FBGA814/10 A 4 GB512 M x 64 4 Gbit256 M x 1682FBGA8TBDRaw Card MicroDIMMCapacityMicroDIMMOrganizationSDRAMDensitySDRAMOrganization# ofSDRAMs# ofRanksSDRAMPackage Type# of banks inSDRAM# Address bitsrow/colB128 MB16 M x 64256 Mbit16 M x 1641FBGA413/9 B256 MB32 M x 64512 Mbit32 M x 1641FBGA413/10 B512 MB64 M x 64 1 Gbit64 M x 1641FBGA813/10B 1 GB128 M x 64 2 Gbit128 M x 1641FBGA814/10B 2 GB256 M x 64 4 Gbit256 M x 1641FBGA8TBD Input Loading MatrixSignal NamesInputDeviceR/C A R/C BClock (CKn, CKn )SDRAM42 CKEn/Sn/ODTn SDRAM44 Addr/RAS/CAS/BA/WE SDRAM84 DQn/DQSn/DQSn/DMn SDRAM21 SCL/SDA/SAn EEPROM11DDR2 MicroDIMM Gerber File ReleasesReference design file updates will be released as needed. This specification will reflect the most recent design files, but may be updated to reflect clarifications to the specification only; in these cases, the design files will not be updated. The following table outlines the most recent design file releasesNote: Future design file releases will include both a date and a revision label. All changes to the design file are also documented within the ‘read-me’ file.Raw Card SpecificationRevisionApplicable Design File NotesA0.5A0 B0.5B0Example Raw Card Component PlacementThe component layout for Raw Cards A, and B are similar. In the case of Raw Card B, DDR2 SDRAMs will be included on the front side of the card; however, passive components are on both sides of the board. This example is for reference only; refer to JEDEC standard MO-TBD for details.6. MicroDIMM Wiring DetailsSignal GroupsThis specification categorizes SDRAM timing-critical signals into four groups whose members have identical loadings and routings. The following table summarizes the signals contained in each group..Signal Group Signals In Group PageClocks for Unbuffered MicroDIMM CK [1:0], CK [1:0]14, 15Data, Data Mask, Data Strobe DQ [63:0], DM[7:0], DQS[7:0], DQS[7:0]16, 17Select, Clock Enable, ODT S [1:0], CKE [1:0], ODT[1:0]18Address/Control Ax, BAx, RAS, CAS, WE19, 20General Net Structure Routing GuidelinesNet structures and lengths must satisfy signal quality and setup/hold time requirements for the memory inter-face. Net structure diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace length table that lists the minimum and maximum allowable lengths for each trace segment and/or net.The general routing recommendations are as follows. Other stackups and layouts are possible that meet the electrical characteristics.•Route all signal traces using appropriate trace width(e.g: 0.075mm) and enough spacing(e.g: 0.15mm) between adjacent traces considering cross talk effect.•Route clocks as much as possible using the inner layers.•Test points are required.Explanation of Net Structure DiagramsThe net structure routing diagrams provide a reference design example for each raw card version. These designs provide an initial basis for unbuffered MicroDIMM designs. The diagrams should be used to deter-mine individual signal wiring on a MicroDIMM for any supported configuration. Only transmission lines (repre-sented as cylinders and labeled with trace length designators “TL”) represent physical trace segments. All other lines are zero in length. To verify MicroDIMM functionality, a full simulation of all signal integrity and tim-ing is required. The given net structures and trace lengths are not inclusive for all solutions.Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. Some configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one DDR2 SDRAM input unless mentioned. It is highly recommended that the net structure routing data in this document be simulated by the user.Differential Clock Net Structures CK[1:0], CK[1:0]DDR2 SDRAM clock signals must be carefully routed to meet the following requirements:•Signal quality •Rise/Fall time•Cross point of the differential pair in the SDRAM •JEDEC-compatible reference delays•Minimal segment length differences (less than 2.54mm total) between clocks of the same functionClock Net Wiring (Raw card A)Clock Routing Trace Lengths (Raw card A)Raw card TL0 Outer TL1 Inner TL2 Inner TL3 Outer TL4 Inner TL5 Outer Notes Min Max Min Max Min Max Min Max Min Max Min Max A2.02.36.26.77.78.13.84.36.37.90.70.911.All distances are given in millimeters and must be kept within a tolerance of ± 0.8 millimeter.TL0MicroDIMM ConnectorTL1TL2TL3TL3CK CKSDRAM SDRAMTL5TL2TL3TL3SDRAMSDRAMTL5R = 200 Ω± 5%R = 200 Ω± 5%TL4TL4Clock Net Wiring (Raw card B)Clock Routing Trace Lengths (Raw card B)Raw card TL0 Outer TL1 Inner TL2 Inner TL3 Outer TL4 Outer Notes Min Max Min Max Min Max Min Max Min Max B2.02.318.218.47.78.13.84.31.52.011.All distances are given in millimeters and must be kept within a tolerance of ± 0.8 millimeter.TL0MicroDIMM ConnectorTL1TL2TL3CK CKSDRAMTL2TL3SDRAMR = 200 Ω± 5%R = 200 Ω± 5%TL4TL4Data Net StructuresDQ[63:0], DM[7:0], DQS[7:0], DQS[7:0]Special attention has been paid to balancing the data nets within a DDR2 SDRAM, within a particularMicroDIMM, and across the MicroDIMM family. Data nets have been placed in order to bound the data strobe nets. Because data travels with the data strobe, the placement of the strobe in the middle of the narrow win-dow aids in data timing. Although it is not necessary to ensure consistent delays between SDRAMs and/or card types, doing so facilitates system design, system simulation, and DIMM specifications. It is recommend to maintain consistent delays for all nets as described in the following tables.Net Structure Routing for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card A)Trace Lengths for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card A)Raw card TL0 Outer TL1 Outer TL2 Outer TotalR1Ohms Notes Min Max Min Max Min Max Min Max A1.04.618.720.92.93.125.325.5221,2,3,41.All distances are given in millimeters and must be kept within a tolerance of ± 0.8 millimeter.2.Total Min and Total Max refer to the min and max respectively of TL0 + TL1 + TL2.3.TL0 and TL1 of Raw Card A is adjusted to compensate for the delay caused by vias on DQ nets. Traces with one via are assumed to have 1.6mm additional length. Traces with two vias are assumed to have 3.2mm additional length.4.These signals must be referenced to ground.TL0MicroDIMM Connector22 Ω ± 5%TL2SDRAM PinTL2SDRAM PinTL1Net Structures Routing for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card B )Trace Lengths for DQ[63:0], DM[7:0], DQS[7:0], DQS[7:0] (Raw card B )Raw cardTL0 Outer TL1 OuterTotalR1Ohms Notes Min Max Min Max Min Max B1.04.621.723.925.325.5221,2,3,41.All distances are given in millimeters and must be kept within a tolerance of ± 0.8 millimeter.2.Total Min and Total Max refer to the min and max respectively of TL0 + TL1.3.TL0 and TL1 of Raw Card B is adjusted to compensate for the delay caused by via on DQ nets.Traces with one via are assumed to have 1.6mm additional length. Traces with two vias are assumed to have 3.2mm additional length.4.These signals must be referenced to ground.TL0MicroDIMM Connector22 Ω ± 5%SDRAM PinTL1Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw cards A, B)Net Structure Routing for Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw cards A, B)Trace Lengths for Control Net Structures S [1:0], CKE[1:0], ODT[1:0] (Raw cards A, B)TL0 OuterTL1 Outer/Inner TL2 Inner TL3 Inner TL4 Outer Notes Raw CardMin Max Min Max Min Max Min Max Min Max A 1.0 4.622.029.116.017.5 6.57.1 2.7 4.21,2,3B1.04.622.029.116.017.56.57.12.74.21,2,31. All distances are given in mm and should be kept within a tolerance of ± 0.8 mm2. TL0 and TL1 are adjusted to compensate for the delay caused by via. Traces with one via are assumed to have 1.6mm additional length. Traces with two vias are assumed to have3.2mm additional length.3. These signals must be referenced to VDD.TL0MicroDIMM ConnectorTL2TL23.0 Ω ± 5%TL1TL3TL3TL4SDRAM PinTL4SDRAM PinTL4SDRAM PinTL3TL3TL4SDRAM PinAddress/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card A ).Net Structure Routing for Address/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card A )Trace Lengths for Address/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card A )TL0 OuterTL1 Outer/Inner TL2 Inner TL3 inner TL4 Outer Notes Raw CardMin Max Min Max Min Max Min Max Min Max A1.04.622.029.116.017.56.57.11.08.31,2,31. All distances are given in mm and should be kept within a tolerance of ± 0.8 mm2. TL0 and TL1 are adjusted to compensate for the delay caused by via. Traces with one via are assumed to have 1.6mm additional length. Traces with two vias are assumed to have3.2mm additional length. 3. These signals must be referenced to VDD.TL0MicroDIMM ConnectorTL4SDRAM PinTL2TL23.0 Ω ± 5%TL1TL3TL3TL4SDRAM PinTL4SDRAM PinTL4SDRAM PinTL4SDRAM PinTL3TL3TL4SDRAM Pin TL4SDRAM PinTL4SDRAM PinAddress/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card B).Net Structure Routing for Address/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card B)Trace Lengths for Address/Control Net Structures Ax, BAx, RAS, CAS, WE (Raw card B)TL0 OuterTL1 Outer/Inner TL2 Inner TL3 inner TL4 Outer TL5 Outer Notes Raw CardMin Max Min Max Min Max Min Max Min Max Min Max B1.04.622.029.116.017.56.57.11.08.33.04.01,2,31. All distances are given in mm and should be kept within a tolerance of ± 0.8 mm2. TL0 and TL1 are adjusted to compensate for the delay caused by via. Traces with one via are assumed to have 1.6mm additional length. Traces with two vias are assumed to have3.2mm additional length.3. These signals must be referenced to VDD.TL0MicroDIMM ConnectorTL2TL23.0 Ω ± 5% TL1TL3TL3TL4SDRAM PinTL4SDRAM PinTL4SDRAM PinTL3TL3TL4SDRAM PinTL58pF ± 0.5pFCross Section RecommendationsAn example of the DDR2 MicroDIMM printed circuit board design uses six-layers of glass epoxy material. PCBs should contain full plane layers for reference plane. The reference planes can be divided so adjacent signal layers maintain a constant Vss or Vdd reference. All data group signals are referenced to Vss and all address/command are referenced to Vdd. The required board impedance is 60 Ω± 10%.PCB Electrical SpecificationsParameter Min Max UnitsTrace velocity: S0 (outer layers) 5.5 6.7ps/mmTrace velocity: S0 (inner layers) 6.57.6ps/mmTrace impedance: Z0 (all layers)5466OhmsExample Layer Stackup for 0.075mm width traceTest PointsAll DDR2 components are in BGA packages which makes the package pads inaccessible for probing during-system development. The DDR2 MicroDIMMs have test points identified to make initial evaluation easier. In some cases test pads have been added and in other cases existing vias are used as test points. An effort has been made to provide testability on some signals in all signal groups but 100% coverage is not possible.Raw Card A Test Points Example(Front View)DQ22CK0-CK1-DQS at resistor pack.CK0CK1DQ7DQ44DQ52DQ28Raw Card B Test Points Example(Front View)BA2DQ22CK0-CK1-A7A3A12A10A9A14S0-A11A6BA0A2BA1CKE0A15A5A1CAS-ODT0RAS-WE-DQS at resistor pack.CK0CK1DQ7DQ44DQ52A13A0A4A8DQ28DQ367. Serial Presence Detect DefinitionThe Serial Presence Detect (SPD) function MUST be implemented on the PC2-4200 DDR2 SDRAM Unbuf-fered MicroDIMM. The component used and the data contents must adhere to the most recent version of the JEDEC DDR2 SDRAM SPD Specifications. Please refer to this document for all technical specifications and requirements of the serial presence detect devices.The following table is intended to be an example of a typical PC2-4200 MicroDIMM. SPD values indicating different MicroDIMM performance characteristics will be utilized based on specific characteristics of the SDRAMs or MicroDIMMs. This example assumes:•Module Organization: 512MB•Device Composition: 32Mx16•Device Package: FBGA•Module Physical Ranks: 2•CAS latency: 4(DDR2-533), 3(DDR2-400)Serial Presence Detect Data Example (Part 1 of 3)Byte # (dec)Byte #(hex)DescriptionSPD Entry ValueSerial PDData Entry(Hexadecimal)NotesDDR2-533DDR2-400DDR2-533DDR2-400000Number of Serial PD Bytes written during production128801 101Total Number of Bytes in Serial PD device256082202Fundamental Memory Type (FPM, EDO, SDRAM,DDR, DDR2, ...)DDR2 SDRAM08303Number of Row Addresses on Assembly130D 404Number of Column Addresses on Assembly100A505Number of DIMM RanksModule height:30mm, Planar,card on card: no,2Ranks61606Data Width of this Assembly x6440 707Reserved Undefined00 808Voltage Interface Level of this assembly SSTL 1.8V05909SDRAM Cycle Time at maximum supported CASlatency (CL), CL = X3.75ns 5.00ns3D503100A SDRAM Access from Clock+/-0.50ns+/-0.50ns5050110B DIMM configuration type (Non-parity, or ECC)Non-Parity00120C Refresh Rate/Type7.8us/SR823,4 130D Primary SDRAM Width x1610140E Error Checking SDRAM Width NA00150F Reserved Undefined001.This will typically be programmed as 128 bytes.2.This will typically be programmed as 256 bytes.3.From Data sheet.4.High order bit is self refresh "flag". If set to "1", the assembly supports self refresh.5.These are optional, in accordance with JEDEC specification.1610SDRAM device attributes: Burst lengths supported4,80C1711SDRAM device attributes: Number of Banks onSDRAM device40431812SDRAM device attributes: CAS Latency4310083 1913Reserved Undefined000 2014DIMM type information MicroDIMM082115SDRAM Module Attributes Normal DIMM002216SDRAM device attributes: General no optional aspect002317Minimum Clock Cycle at CLX -1Undefined FF32418Maximum Data Access Time (t AC) from Clock at CLX -1Undefined FF32519Minimum Clock Cycle Time at CLX-2Undefined FF3261A Maximum Data Access Time (t AC) from Clockat CLX-2Undefined FF3271B Minimum Row Precharge Time (t RP)15.0ns15.0ns3C3C3 281C Minimum Row Active to Row Active delay (t RRD)7.5ns7.5ns1E1E3 291D Minimum RAS to CAS delay (t RCD)15.0ns15.0ns3C3C3 301E Minimum Active to Precharge Time (t RAS)45.0ns45.0ns2D2D3 311F Module Rank Density256MB403220Address and Command input Setup Time BeforeClock (t IS)0.60ns0.60ns606033321Address and Command input Hold Time After Clock(t IH)0.60ns0.60ns606033422Data Input Setup Time Before Clock (t DS)0.35ns0.35ns35353 3523Data Input Hold Time After Clock (t DH)0.35ns0.35ns35353 3624Write recovery time (t WR)15.0ns15.0ns3C3C3 3725Internal write to read command delay (t WTR)7.5ns10ns1E283 3826Internal read to precharge command delay (t RTP)7.5ns7.5ns1E1E3 3927Memory analysis probe characteristics Undefined004028Reserved Undefined004129SDRAM device minimum active to active/auto refreshtime (t RC)60.0ns60.0ns3C3C3422A SDRAM device minimum auto-refresh to active/autorefresh command period (t RFC)105.0ns105.0ns69693Serial Presence Detect Data Example (Part 2 of 3)Byte # (dec)Byte #(hex)DescriptionSPD Entry ValueSerial PDData Entry(Hexadecimal)NotesDDR2-533DDR2-400DDR2-533DDR2-4001.This will typically be programmed as 128 bytes.2.This will typically be programmed as 256 bytes.3.From Data sheet.4.High order bit is self refresh "flag". If set to "1", the assembly supports self refresh.5.These are optional, in accordance with JEDEC specification.。

长安大学硕士学位论文37很合理尤...

III
(4)Speed of blast-resistant doors Explosion early, each special node of blast-resistant doors appeared negative velocity
first, the larger the distance, the larger the speed peak, after reach the negative velocity peak, began to decrease, then reaches 0, and increase the principal speed peak, also present a reciprocating vibration. The whole speed of blast-resistant doors is less than the speed of the special nodes. Each special node of blast-resistant doors weak heavily than the whole blast-resistant doors. The moment of maximum speed about special nodes and the whole blast-resistant doors are coincided basically. (5)Energy of blast-resistant doors
对于折合距离 0.4 时的爆炸冲击荷载作用,动能出现先增大后减小的现象,最后动 能为零。应变能和总能都出现先增大后减小,最后稳定的现象。
2、分别改变抗爆门的材料强度、抗爆门面板的厚度、钢龙骨、爆炸荷载峰值和作 用时间等一系列参数,对抗爆门进行了有限元动力模拟。计算结果表明:虽然从计算结 果上看抗爆门面板的厚度对抗爆门的力学性能影响最大,工字钢龙骨的型号对抗爆门的 力学性能影响较大,材料强度对抗爆门的力学性能影响最小,但是从经济性的角度来考 虑,采用较大型号的工字钢龙骨来提高抗爆门的抗变形性能得到的经济效益最高,提高 材料的强度来提高抗爆门的抗变形性能得到的经济效益较高,而采用增大抗爆门面板厚 度来提高抗爆门的抗变形性能不够经济。

错误和警告解析1

错误和警告解析1错误和警告解析 1.txt Model Size (current problem)1.183933e+000,BTOL setting 1.00000e-005,minmum KPTdistance 4.308365e-006先在要分割的地方设置一个工作平面,用布尔运算“divided --volume by working plane”进行分割的时候,出现上述错误,主要愿意可能是设置的公差太小,当时试了几次都么有成功,最后干脆把体重新建立了一个,又画了一个很大的面,终于成功了。

2.一个常见的代表性错误!原来我的虚拟内存设置为“无分页文件”,现在改为“系统管理”,就不在出现计算内存不够的情况了。

Error!Element type 1 is Solid95,which can not be used with the AMES command, meshing ofarea 2 aborted.刚开始学习的人经常出这种错误,这是因为不同单元类型对应不同的划分网格操作。

上面的错误是说单元类型为Solid95(实体类型),不能用AMES 命令划分面网格。

3 Meshing of volume 5 has been aborted because of a lack of memory. Closed down otherprocesses and/or choose a larger element size, then try the VMESH command again.Minimum additional memory required=853MB(bykitty_zoe )说你的内存空间不够,可能因为你的计算单元太多,增加mesh 尺寸,减少数量或者增加最小内存设定(ansys10中在customization preferences菜单存储栏可以修改)你划分的网格太细了,内存不足。

ANSYS中文翻译官方高级手册_adv4

第四章子结构什么是子结构?子结构就是将一组单元用矩阵凝聚为一个单元的过程。

这个单一的矩阵单元称为超单元。

在ANSYS分析中,超单元可以象其他单元类型一样使用。

唯一的区别就是必须先进行结构生成分析以生成超单元。

子结构可以在ANSYS/Mutiphysics,ANSYS/Mechanical和ANSYS/Structural中使用。

使用子结构主要是为了节省机时,并且允许在比较有限的计算机设备资源的基础上求解超大规模的问题。

原因之一如a)非线性分析和带有大量重复几何结构的分析。

在非线性分析中,可以将模型线性部分作成子结构,这样这部分的单元矩阵就不用在非线性迭代过程中重复计算。

在有重复几何结构的模型中(如有四条腿的桌子),可以对于重复的部分生成超单元,然后将它拷贝到不同的位置,这样做可以节省大量的机时。

子结构还用于模型有大转动的情况下。

对于这些模型,ANSYS假定每个结构都是围绕其质心转动的。

在三维情况下,子结构有三个转动自由度和三个平动自由度。

在大转动模型中,用户在使用部分之前无须对子结构施加约束,因为每个子结构都是作为一个单元进行处理,是允许刚体位移的。

另外一个原因b)一个问题就波前大小和需用磁盘空间来说相对于一个计算机系统太庞大了。

这样,用户可以通过子结构将问题分块进行分析,每一块对于计算机系统来说都是可以计算的。

如何使用子结构子结构分析有以下三个步骤:●生成部分●使用部分●扩展部分生成部分就是将普通的有限元单元凝聚为一个超单元。

凝聚是通过定义一组主自由度来实现的。

主自由度用于定义超单元与模型中其他单元的边界,提取模型的动力学特性。

图4-1是一个板状构件用接触单元分析的示意。

由于接触单元需要迭代计算,将板状构件形成子结构将显著地节省机时。

本例中,主自由度是板与接触单元相连的自由度。

图4-1 子结构使用示例使用部分就是将超单元与模型整体相连进行分析的部分。

整个模型可以是一个超单元,也可以象上例一样是超单元与非超单元相连的。

ASNZS 1170.0 General Principles

AS/NZS 1170.0:2002(Incorporating Amendment Nos 1,2&4)Australian/New Zealand Standard ™Structural design actions Part 0:GeneralprinciplesBuildingCodeofAustralia Primaryreferenced StandardAS/NZS1170.0:2002This Joint Australian/New Zealand Standard was prepared by Joint Technical Committee BD-006,General Design Requirements and Loading on Structures.It was approved on behalf of the Council of Standards Australia on29March2002 and on behalf of the Council of Standards New Zealand on28March2002.It was published on4June2002.The following are represented on Committee BD-006:Association of Consulting Engineers AustraliaAustralian Building Codes BoardAustralian Institute of Steel ConstructionBuilding Research Association of New ZealandCement and Concrete Association of AustraliaConcrete Masonry Association of AustraliaCSIRO,Building,Construction and EngineeringCyclone Testing Station—James Cook UniversityElectricity Supply Association of AustraliaHousing Industry AssociationInstitution of Engineers AustraliaInstitution of Professional Engineers New ZealandMaster Builders AustraliaNew Zealand Heavy Engineering Research AssociationSteel Reinforcement Institute of AustraliaUniversity of Canterbury New ZealandUniversity of MelbourneUniversity of NewcastleAdditional interests participating in the preparation of this Standard:Monash UniversityCurtin University of TechnologyKeeping Standards up-to-dateStandards are living documents which reflect progress in science,technology and systems.To maintain their currency,all Standards are periodically reviewed,and new editions are published.Between editions,amendments may be issued. Standards may also be withdrawn.It is important that readers assure themselves they are using a current Standard,which should include any amendments which may have been published since the Standard was purchased.Detailed information about joint Australian/New Zealand Standards can be found by visiting the Standards Australia web site at .au or Standards New Zealand web site at and looking up the relevant Standard in the on-line catalogue.Alternatively,both organizations publish an annual printed Catalogue with full details of all current Standards.For more frequent listings or notification of revisions,amendments and withdrawals,Standards Australia and Standards New Zealand offer a number of update options.For information about these services, users should contact their respective national Standards organization.We also welcome suggestions for improvement in our Standards,and especially encourage readers to notify us immediately of any apparent inaccuracies or ambiguities.Please address your comments to the Chief Executive of either Standards Australia International or Standards New Zealand at the address shown on the back cover.This Standard was issued in draft form for comment as DR00904.AS/NZS 1170.0:2002(Incorporating Amendment Nos 1, 2 & 4)Australian/New Zealand Standard™Structural design actionsPart 0: General principlesOriginated in Australia as part of AS CA1—1933.Originated in New Zealand as part of NZS 1900:1964.Previous Australian editions AS 1170.1—1989 and AS 2867—1986.Previous New Zealand edition NZS 4203:1992.AS 1170.1—1989, AS 2867—1986, and NZS 4203:1992 jointly revised, amalgamated and redesignated in part as AS/NZS 1170.0:2002.Reissued incorporating Amendment Nos 1, 2 & 4 (April 2005)COPYRIGHT© Standards Australia/Standards New ZealandAll rights are reserved. No part of this work may be reproduced or copied in any form or by any means, electronic or mechanical, including photocopying, without the written permission of the publisher.Jointly published by Standards Australia International Ltd, GPO Box 5420, Sydney, NSW 2001 and Standards New Zealand, Private Bag 2439, Wellington 6020AS/NZS 1170.0:20022PREFACEThis Standard was prepared by the Joint Standards Australia/Standards New Zealand Committee BD-006, General Design Requirements and Loading on Structures to supersede, in part, AS 1170.1—1989, Minimum design loads on structures, Part 1: Dead and live loads , and, in part, NZS 4203:1992, Code of practice for general structural design and design loadings for buildings, Volume 1: Code of practice and, in part, AS 2867—1986, Farm structures—General requirements for structural design .This Standard is published as a joint Standard (as are also AS/NZS 1170.1 and AS/NZS 1170.2) and it is intended that it is suitable for use in New Zealand as well as Australia.For Australia, this Standard will be referenced in the Building Code of Australia by way of BCA Amendment 11 to be published on 1 July 2002, thereby superseding in part the previous Edition, AS 1170.1—1989, which will be withdrawn 12 months from the date of publication of this edition. AS 1170.1—1989 may be used for structures not covered by the Building Code of Australia, until an Appendix is developed for inclusion in this Standard by amendment.The objective of this Standard is to provide designers with general procedures and criteria for the structural design of structures. It outlines a design methodology that is applied in accordance with established engineering principles.This Standard includes revised Clauses covering load combinations (referred to as combinations of actions) and general design and analysis clauses. It does not include values of actions (e.g. values of dead or live loads; referred to as permanent or imposed actions). This Standard is Part 0 of the 1170 series, Structural design actions , which comprises the following parts, each of which has an accompanying Commentary published as a Supplement:The Commentary to this Standard is AS/NZS 1170.0 Supp 1, Structural design actions —General principles —Commentary (Supplement to AS/NZS 1170.0:2002).This Standard is based on the philosophy and principles set out in ISO 2394:1998, General principles on reliability for structures . ISO 2394 is written specifically as a guide for the preparation of national Standards covering the design of structures. It includes methods for establishing and calibrating reliability based limit states design Standards.The terms ‘normative’ and ‘informative’ have been used in this Standard to define the application of the appendix to which they apply. A ‘normative’ appendix is an integral part of a Standard, whereas an ‘informative’ appendix is only for information and guidance.Notes to the text contain information and guidance and are not considered to be an integral part of the Standard. AS/NZS 1170.0 General principlesAS/NZS 1170.1 Permanent, imposed and other actionsAS/NZS 1170.2 Wind actionsAS/NZS 1170.3 Snow and ice actionsAS 1170.4Earthquake loads NZS 1170.5Earthquake actions – New Zealand A4 A4AS/NZS 1170.0:20023CONTENTSPage SECTION 1 SCOPE AND GENERAL1.1 SCOPE (4)1.2 APPLICATION (5)1.3 REFERENCED DOCUMENTS (5)1.4 DEFINITIONS (5)1.5 NOTATION (7)SECTION 2 STRUCTURAL DESIGN PROCEDURE2.1 GENERAL (9)2.2 ULTIMATE LIMIT STATES (9)2.3 SERVICEABILITY LIMIT STATES (10)SECTION 3 ANNUAL PROBABILITY OF EXCEEDANCE(FOR NEW ZEALAND USE ONLY)3.1 GENERAL (11)3.2 IMPORTANCE LEVELS (11)3.3 DESIGN WORKING LIFE (11)3.4 ANNUAL PROBABILITY OF EXCEEDANCE (12)SECTION 4 COMBINATIONS OF ACTIONS4.1 GENERAL (15)4.2 COMBINATIONS OF ACTIONS FOR ULTIMATE LIMIT STATES (15)4.3 COMBINATIONS OF ACTIONS FOR SERVICEABILITY LIMIT STATES (17)4.4 CYCLIC ACTIONS (17)SECTION 5 METHODS OF ANALYSIS5.1 GENERAL (18)5.2 STRUCTURAL MODELS (18)SECTION 6 STRUCTURAL ROBUSTNESS6.1 GENERAL (19)6.2 LOAD PATHS (19)SECTION 7 CONFIRMATION METHODS7.1 GENERAL (20)7.2 ULTIMATE LIMIT STATES (20)7.3 SERVICEABILITY LIMIT STATES (20)APPENDICESA SPECIAL STUDIES (21)B USE OF TEST DATA FOR DESIGN (22)C GUIDELINES FOR SERVICEABILITY LIMIT STATES (26)D FACTORS FOR USE WITH AS 1170.4—1993 (29)F ANNUAL PROBABILITY OF EXCEEDANCE(FOR AUSTRALIAN USE ONLY–STRUCTURES FOR WHICH DESIGNEVENTS ARE NOT GIVEN) (32)AS/NZS 1170.0:2002 4STANDARDS AUSTRALIA/STANDARDS NEW ZEALANDAustralian/New Zealand StandardStructural design actionsPart 0: General principlesS E C T I O N1S C O P E A N D G E N E R A L1.1 SCOPEThis Standard specifies general procedures and criteria for the structural design of a building or structure in limit states format. It covers limit states design, actions, combinations of actions, methods of analysis, robustness and confirmation of design.The Standard is applicable to the structural design of whole buildings or structures and their elements.This Standard covers the following actions:(a)Permanent action (dead load).(b)Imposed action (live load).(c)Wind.(d)Snow.(e)Earthquake.(f)Liquid pressure.(g)Ground water.(h)Rainwater ponding.(i)Earth pressure.NOTES:1Where this Standard does not give information required for design, special studies should be carried out. Guidance is given in Appendix A.2Where testing is used to determine data for design or to confirm a design, guidance on methods is given in Appendix B.3Normal design practice is that all likely actions be considered. Any actions considered in design that are not in the above list should be the subject of special studies, as they are notcovered by this Standard.4Additional information on other actions such as movement effects, construction loads and accidental actions is given in the Commentary (see Preface).5Movement effects include actions on structures resulting from expansion or contraction of materials of construction (such as those due to creep, temperature or moisture contentchanges) and also those resulting from differential ground settlement. Serviceability may beparticularly affected by such actions.6Guidance on criteria for serviceability is given in Appendix C, which have been found to be generally suitable for importance level 2 buildings. Structures of special importance orstructures where more stringent criteria are appropriate may require the stated criteria to betightened.AS/NZS 1170.0:20025 1.2 APPLICATIONThis Standard may be used as a means for demonstrating compliance with the Requirements of Part B1 of the Building Code of Australia.This Standard is intended for citation by New Zealand’s Building Industry Authority as a document that contributes towards establishing compliance with Clause B1 ‘Structure’ of the New Zealand Building Code. A code complying design is also contingent upon the Standard being used in conjunction with the appropriate material Standard and with additional approval being granted in respect of the engineering judgement calls made in the application of the Standard.1.3 REFERENCED DOCUMENTSThe following documents are referred to in this Standard:1.4 DEFINITIONSFor the purpose of this Standard the definitions below apply.1.4.1 ActionSet of concentrated or distributed forces acting on a structure (direct action), or deformation imposed on a structure or constrained within it (indirect action).NOTE: The term load is also often used to describe direct actions.1.4.2 Action effects (internal effects of actions, load effects)Internal forces and bending moments due to actions (stress resultants).1.4.3 Combination of actionsSet of design values used to confirm that the limit states are not exceeded under the simultaneous influence of different actions.1.4.4 Design action effectThe action effect computed from the design values of the actions or design loads.1.4.5 Design capacityThe product of the capacity reduction factor and the nominal capacity.1.4.6 Design situationSet of conditions for which the design is required to demonstrate that relevant limit states are not exceeded.AS 1170 Minimum design loads on structures 1170.4Part 4: Earthquake loads AS/NZS 1170 Structural design actions 1170.1 Part 1: Permanent, imposed and other actions 1170.2 Part 2: Wind actions 1170.3Part 3: Snow and ice actions NZS 1170 Structural design actions 1170.5 Part 5: Earthquake actions – New Zealand Australian Building Codes Board Building Code of Australia A4 A1 A1AS/NZS 1170.0:2002 61.4.7 Imposed actionA variable action resulting from the intended use or occupancy of the structure.1.4.8 Limit statesStates beyond which the structure no longer satisfies the design criteria.NOTE: Limit states separate desired states (compliance) from undesired states (non-compliance).1.4.9 Limit states, serviceabilityStates that correspond to conditions beyond which specified service criteria for a structure or structural element are no longer met.NOTE: The criteria are based on the intended use and may include limits on deformation, vibratory response, degradation or other physical aspects.1.4.10 Limit states, ultimateStates associated with collapse, or with other similar forms of structural failure.NOTE: This generally corresponds to the maximum load-carrying resistance of a structure or structural element but, in some cases, to the maximum applicable strain or deformation.1.4.11 LoadThe value of a force appropriate to an action.1.4.12 Permanent actionAction that is likely to act continuously and for which variations in magnitude with time are small compared with the mean value.1.4.13 Proof testingApplication of test loads to a structure, sub-structure, member or connection, to ascertain the structural characteristics of that one item under test.1.4.14 Prototype testingApplication of test loads to one or more samples of structures, sub-structures, members or connections to ascertain the structural characteristics of the population that the sample represents.1.4.15 ReliabilityAbility of a structure or structural element to fulfil the specified criteria, including the working life, for which it has been designed.NOTE: Reliability covers structural safety and serviceability, and can be expressed in terms of probability.1.4.16 ServiceabilityAbility of a structure or structural element to perform adequately for normal use under all expected actions.1.4.17 ShallIndicates that a statement is mandatory.1.4.18 ShouldIndicates a recommendation (non-mandatory).1.4.19 StructureOrganized combination of connected structural elements designed to provide some measure of resistance.AS/NZS 1170.0:200271.4.20 Structural elementPhysically distinguishable part of a structure, for example, wall, column, beam, connection.1.4.21 Structural robustnessAbility of a structure to withstand events like fire, explosion, impact or consequences ofhuman errors, without being damaged to an extent disproportionate to the original cause.1.4.22 Special studyA procedure for justifying departure from this Standard or for determining information notcovered by this Standard.NOTE: Special studies are outside the scope of this Standard.1.4.23 Design working lifeA2Duration of the period during which a structure or a structural element, when designed, isassumed to perform for its intended purpose with expected maintenance but without majorstructural repair being necessary.NOTE: In the context of this Standard, the design working life is a ‘reference period’ usuallystated in years. It is a concept that can be used to select the probability of exceedance of differentactions.1.4.24 Environmental influencesChemical, biological or physical influences on a structure, which may deteriorate thematerials constituting the structure, and which in turn may affect its reliability in anunfavourable way.1.5 NOTATIONWhere non-dimensional ratios are involved, both the numerator and denominator areexpressed in identical units.The dimensional units for length and stress in all expressions or equations are to be taken asmillimetres (mm) and megapascals (MPa) respectively, unless specifically noted otherwise.Unless otherwise stated, the notation in this Standard has the following meanings:E = action effectE = earthquake actionE s= serviceability earthquake actionE u= ultimate earthquake actionE d= design action effectE d,dst= design action effect of destabilizing actionsE d,stb= design action effect of stabilizing actionsF e= earth pressure actionF e,u= ultimate earth pressure actionF ice= ice actionF gw= ground water actionF l p= liquid pressure actionF pnd= rainwater ponding actionF sn= snow actionAS/NZS 1170.0:2002 8G = permanent action (self-weight or ‘dead’ action)k p= probability factork t= factor to allow for variability of structural unitsN = design working life of a building or structure, in yearsP = the annual probability of exceedanceP ref= reference probability of exceedance for safetyQ = imposed action (due to occupancy and use, ‘live’ action)R= nominal capacity (based on the fifth percentile strength)R d= design capacity (equal to φR)S u= ultimate value of various actions appropriate for particular combinationsV sc= coefficient of variation of structural characteristicsW = wind actionW s= serviceability wind actionW u= ultimate wind actionδ= values of the serviceability parameter determined on the basis of the design actionsδ = limiting value of the serviceability parameter (the subscript ‘ ’ stands for limiting value)φ= capacity reduction factorψc= combination factor for imposed actionψs= factor for determining frequent values (short-term) of actionsψ = factor for determining quasi-permanent values (long-term) of actionsS E C T I O N 2 S T R U C T U R A L D E S I G NP R O C E D U R E2.1 GENERALStructural design shall be carried out using the procedure given in Clause 2.2 for ultimate limit states and Clause 2.3 for serviceability limit states. 2.2 ULTIMATE LIMIT STATESDesign for ultimate limit states shall be carried out by the following procedure:(a)Adopt the importance level for the building or structure and the associated annual probability of exceedance (P ) for wind, snow and earthquake as follows: (i)For Australia—(A) structures covered by the Building Code of Australia—as given in theBuilding Code of Australia. (B) structures not covered by the Building Code of Australia and for whichno design events are specified by the applicable legislation or by other Standards—as given in Appendix F. (ii) For New Zealand—as given in Section 3.(b) Determine the permanent (G ) and imposed (Q ) loads in accordance with AS/NZS 1170.1.(c)Determine the ultimate loads for wind (W ) in accordance with AS/NZS 1170.2. (d)Determine the ultimate loads for earthquake (E u ) for Australia, in accordance with AS 1170.4 as modified by Appendix D of this Standard including the probability factor (k p ) and the changes to earthquake design category. For New Zealand determine the ultimate loads for earthquake (E u ), in accordance with NZS 1170.5. (e) Determine the ultimate loads for snow (F sn ) and ice (F ice ) in accordance with AS/NZS 1170.3.(f)Where such actions are relevant, determine the ultimate loads for liquid pressure (F l p ) ground water (F gw ) rainwater ponding (F pnd ) and earth pressure loads (F e,u ) in accordance with AS/NZS 1170.1.(g) Determine combinations of actions in accordance with Section 4.(h) Analyse the structure and its parts for the relevant combinations in accordance with Section 5.(i)Design and detail the structure in accordance with— (i)Section 6 for robustness; and(ii) for Australia, AS 1170.4 for earthquake, or (iii) for New Zealand, NZS 1170.5 for earthquake.(j) Determine the design resistance using the applicable Standard or other document. The Building Code of Australia specifies the documents to be used within its jurisdiction. (k)Confirm that the design resistance exceeds the appropriate action effects in accordance with Section 7.A4A4A1A22.3 SERVICEABILITY LIMIT STATESDesign for serviceability limit states shall be carried out by the following procedure as appropriate:(a) Determine for the whole structure and for individual elements, the type of designserviceability conditions to be considered.(b) Determine the design situation including the serviceability load event andserviceability limits for the design serviceability condition being considered (see Section 3 for New Zealand).NOTE: Guidelines for serviceability events and associated limits are given in Appendix C for loads associated with an appropriate annual probability of exceedance (P ).(c) Determine the permanent loads (G ) and serviceability imposed loads (Q ) in accordance with AS/NZS 1170.1.(d)Determine serviceability loads for wind (W ) in accordance with AS/NZS 1170.2. (e) Determine serviceability loads for snow (F sn ) and ice (F ice ) in accordance with AS/NZS 1170.3.(f)Where such actions are relevant, determine serviceability loads for liquid pressure (F l p ) ground water (F gw ) rainwater ponding (F pnd ) and earth pressure (F e,u ) in accordance with AS/NZS 1170.1.(g) Determine the applicable combinations corresponding to the selected design serviceability conditions in accordance with Section 4.(h)Model the serviceability response of the structure and its parts for the relevant combinations for each serviceability condition using methods of analysis appropriate for the serviceability limit state in accordance with Section 5.(i)Determine the serviceability response using the applicable Standard or other document. The Building Code of Australia specifies the documents to be used within its jurisdiction.(j)Confirm, in accordance with Section 7, that the modelled serviceability response does not exceed the appropriate limiting values for each of the serviceability conditions identified.A2A1S E C T I O N 3 A N N U A L P R O B A B I L I T Y O FE X C E E D A N C E(F O R N E W Z E A L A N D U S E O N L Y )3.1 GENERALThis Section shall be used to determine the annual probability of exceedance of ultimate limit state loads for New Zealand. It does not form part of the Standard for use in Australia. Structures of importance level 5 are outside the scope of this Standard and require the annual probability of load exceedance (design event) to be determined by a special study.NOTE: For buildings within Australia, refer to the Building Code of Australia.3.2 DESIGN REQUIREMENTSA structure shall be designed and constructed in such a way that it will, during its design working life, with appropriate degrees of reliability sustain all actions and environmental influences likely to occur. In particular it shall be designed as follows: (a)To withstand extreme or frequently repeated actions, or both, occurring during its construction and anticipated use (resistance, deformability and static equilibrium requirements; that is, for safety).Specifically, for earthquake actions for ultimate limit states this shall mean— (i)avoidance of collapse of the structural system;(ii) avoidance of collapse or loss of support of parts of the structure representing ahazard to human life inside and outside the structure or parts required for life safety systems; and (iii) avoidance of damage to non-structural systems necessary for the buildingevacuation procedures that renders them inoperative. (b)So that it will not be damaged to an extent disproportionate to the original cause, by events like fire, explosion, impact or consequences of human error (robustness requirement).(c)To perform adequately under all expected actions (serviceability requirement).Structural design carried out using the procedures given in Clause 2.2 for ultimate limit states and Clause 2.3 for serviceability limit states is deemed to comply with this Clause.NOTE:The design should include consideration of appropriate maintenance and the effects of environmental influences.3.3 IMPORTANCE LEVELSThe importance level of the structure shall be determined in accordance with its occupancy and use, as given in Tables 3.1 and 3.2. The Table describes, in general terms, five categories of structure and gives some examples of each. For those buildings not specifically mentioned, the designer will need to exercise judgement in assigning the appropriate level.Structures that have multiple uses shall be assigned the highest importance level applicable for any of those uses. Where access to a structure is via another structure of a lower importance level, then the importance level of the access structure shall be designated the same as the structure itself.A2A43.4 ANNUAL PROBABILITY OF EXCEEDANCE3.4.1 Ultimate limit statesFor ultimate limit states for structures of importance levels 1 to 4, the annual probability of exceedance (P) for wind, snow and earthquake loads shall be as given in Table 3.3.The design working life of structures that are erected for a number of short periods of use and dismantled between each, is equal to the total of the periods of use.3.4.2 Serviceability limit statesServiceability limit states shall include—(a) SLS1—the structure and the non-structural components do not require repair after theSLS1 earthquake, snow or wind event; and(b) SLS2 — the structure maintains operational continuity after the SLS2 earthquake. For serviceability limit states for structures of importance levels 2 to 4, the annual probability of exceedance (P) for wind, snow and earthquake loads shall be determined as given in Table 3.3.NOTE: Guidelines for limits associated with serviceability events are given in Appendix C.TABLE 3.1CONSEQUENCES OF FAILURE FOR IMPORTANCE LEVELSConsequences of failure DescriptionImportancelevelCommentLow Low consequence for loss of human life, orsmall or moderate economic, social orenvironmental consequences1Minor structures (failure not likely toendanger human life)Ordinary Medium consequence for loss of human life, orconsiderable economic, social or environmentalconsequences2Normal structures and structures notfalling into other levels3 Major structures (affecting crowds)HighHigh consequence for loss of human life, orvery great economic, social or environmentalconsequences 4Post-disaster structures (post disasterfunctions or dangerous activities)Exceptional Circumstances where reliability must be set on acase by case basis5 Exceptional structuresA2 A4TABLE 3.2IMPORTANCE LEVELS FOR BUILDING TYPES—NEW ZEALAND STRUCTURES ImportancelevelComment Examples1 Structures presenting a lowdegree of hazard to life andother property Structures with a total floor area of <30 m2Farm buildings, isolated structures, towers in rural situations Fences, masts, walls, in-ground swimming pools2 Normal structures andstructures not in otherimportance levels Buildings not included in Importance Levels 1, 3 or 4Single family dwellingsCar parking buildingsBuildings and facilities as follows:(a) Where more than 300 people can congregate in one area(b) Day care facilities with a capacity greater than 150(c) Primary school or secondary school facilities with a capacitygreater than 250(d) Colleges or adult education facilities with a capacity greater than500(e) Health care facilities with a capacity of 50 or more residentpatients but not having surgery or emergency treatment facilities (f) Airport terminals, principal railway stations with a capacitygreater than 250(g) Correctional institutions(h) Multi-occupancy residential, commercial (including shops),industrial, office and retailing buildings designed to accommodate more than 5000 people and with a gross area greater than10 000 m2(i) Public assembly buildings, theatres and cinemas of greater than1000 m23 Structures that as a wholemay contain people in crowdsor contents of high value tothe community or pose risksto people in crowdsEmergency medical and other emergency facilities not designated aspost-disasterPower-generating facilities, water treatment and waste water treatmentfacilities and other public utilities not designated as post-disasterBuildings and facilities not designated as post-disaster containinghazardous materials capable of causing hazardous conditions that do notextend beyond the property boundaries4 Structures with special post-disaster functions Buildings and facilities designated as essential facilitiesBuildings and facilities with special post-disaster functionMedical emergency or surgical facilitiesEmergency service facilities such as fire, police stations and emergency vehicle garagesUtilities or emergency supplies or installations required as backup for buildings and facilities of Importance Level 4Designated emergency shelters, designated emergency centres and ancillary facilitiesBuildings and facilities containing hazardous materials capable of causing hazardous conditions that extend beyond the property boundaries5 Special structures(outside the scope of thisStandard—acceptableprobability of failure to bedetermined by special study) Structures that have special functions or whose failure poses catastrophic risk to a large area (e.g. 100 km2) or a large number of people (e.g., 100 000)Major dams, extreme hazard facilitiesA2。

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2
McConnachie & Irwin
branch morphology, such that their are more blue horizontal branch stars located at larger radius from the centre of the dwarf (Da Costa et al. 1996). Some evidence for AGB components have also been seen in these systems (most recently by Kerschbaum et al. 2004 and Harbeck et al. 2004), although a strong intermediate age component similar to some of the Galactic dSphs is generally lacking. As a compliment to the deeper pointed HST observations, we have obtained wide field Johnston V (V ′ ) and Gunn i (i′ ) photometry for the majority of the members of the M31 subgroup using the Wide Field Camera (WFC) on the 2.5m Isaac Newton Telescope (INT). This is a fourchip EEV 4K x 2K CCD mosaic camera with a ∼ 0.29 ◦ field of view (Walton et al. 2001). With typical exposures of ∼ 1000 s in each passband, this photometry is deep enough to observe the top few magnitudes of the red giant branch in each system and has already been used to derive a homogeneous set of distance and metallicity estimates for each of these galaxies (McConnachie et al. 2004, 2005). Here, we use the same data to analyse the structural properties of each of the Andromeda dSphs, as well as the isolated dSph in Cetus as a comparison. In common with Tucana, this galaxy is one of only two dSphs not found as a satellite to a large galaxy in the Local Group. Our results for Andromeda IX are presented elsewhere (Chapman et al. 2005). Our overall technique and methodology is similar to that adopted by IH95 for the Galactic dSphs, insofar as we base most of our analysis on resolved star counts. Caldwell et al. (1992) and Caldwell (1999) have performed a similar analysis for the Andromeda dSphs based upon the integrated light, and we will compare our results to these later (Section 4.1). In Section 2, we derive contour maps, radial profiles and associated structural parameters for Andromeda I, II, III, V, VI, VII and Cetus based upon resolved star counts. The integrated luminosities, central surface brightnesses and related quantities are derived in Section 3. We postpone discussion of all the results until Section 4, which also compares the M31 dSph population to the Galactic dSph population. Section 5 summarises and concludes.
Willman et al. (2005) have recently discovered a new Galactic companion in Ursa Major, which is not included here
ysed the structure of the Galactic dSphs, except Sagittarius, by mapping their resolved star counts from photographic plates. They found that the stellar profiles of the dSphs were generally well described by a single component King or exponential model. A generic feature was an excess of stars at large radii, over and above that expected from the best-fit King tidal model, which have generally been interpreted as evidence for tidal disturbance. A King profile is not a physically motivated model for dSphs since their relaxation time
arXiv:astro-ph/0511004v1 31 Oct 20பைடு நூலகம்5
5 February 2008
ABSTRACT
The projected structures and integrated properties of the Andromeda I, II, III, V, VI, VII and Cetus dwarf spheroidal galaxies are analysed based upon resolved counts of red giant branch stars. The observations were taken as part of the Isaac Newton Telescope Wide Field Survey of M31 and its environs. For each object, we have derived isopleth maps, surface brightness profiles, intensity-weighted centres, position angles, ellipticities, tidal radii, core radii, concentration parameters, exponential scale lengths, Plummer scale lengths, half-light radii, absolute magnitudes and central surface brightnesses. Our analysis probes to larger radius and fainter surface brightnesses than most previous studies and as a result we find that the galaxies are generally larger and brighter than has previously been recognised. In particular, the luminosity of Andromeda V is found to be consistent with the higher metallicity value which has been derived for it. We find that exponential and Plummer profiles provide adequate fits to the surface brightness profiles, although the more general King models provide the best formal fits. Andromeda I shows strong evidence of tidal disruption and S-shaped tidal tails are clearly visible. On the other hand, Cetus does not show any evidence of tidal truncation, let alone disruption, which is perhaps unsurprising given its isolated location. Andromeda II shows compelling evidence of a large excess of stars at small radius and suggests that this galaxy consists of a secondary core component, in analogy with recent results for Sculptor and Sextans. Comparing the M31 dwarf spheroidal population with the Galactic population, we find that the scale radii of the M31 population are larger than those for the Galactic population by at least a factor of two, for all absolute magnitudes. This difference is either due to environmental factors or orbital properties, suggesting that the ensemble average tidal field experienced by the M31 dwarf spheroidals is weaker than experienced by the Galactic dwarf spheroidals. We find that the two populations are offset from one another in the central surface brightness – luminosity relation, which is probably related to this difference in their scale sizes. Finally, we find that the M31 dwarf spheroidals show the same correlation with distance-from-host as shown by the Galactic population, such that dwarf spheroidals with a higher central surface brightness are found further from their host. This again suggests that environment plays a significant role in dwarf galaxy evolution, and requires detailed modelling to explain the origin of this result. Key words: Local Group - galaxies: general - galaxies: dwarf - galaxies: fundamental parameters - galaxies: structure - galaxies: interactions
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