数字系统设计与PLD应用答案

A BC(余)D(商)(1)算法模型(2)数据处理单元(框图)A B CR2.17、流水线操作结构：T S1=18*100+(256-1)*100=2.73*104(ns) 顺序算法结构：T S2=256*18*100=4.608*105(ns) 显然流水线操作时间短。

（若系统输入数据流的待处理数据元素为m 个，每一元素运算共计L 段，每段历经时间为Δ，则流水线操作算法结构共需运算时间为：T=L ·Δ+(m-1) Δ而顺序算法（或并行算法）结构所需运行时间为：m ·L ·Δ） 2.30、(1).DFF 状态编码A —000B —001C —010D —011E —100001101100010---XQ 1Q 0Q 201001101100100---XQ 1Q 0Q 20100110110000---Q 1Q 0Q 201D 2D 1D 0ZZ输出：XSETOUDOUT COUT BOUT AOUT QQ Q QQ QQQ QQQ Q Q Q Q 01212121212=====（2）“一对一”状态分配Q Q Q Q QE D C B A 4321-----次态表：激励方程：XZ XZ ZXX Z QQ D Q D QQ D QD Q Q QD 43413212142+==+==++=输出：X SETOU DOUT COUT BOUT AOUT Q Q Q Q Q4321=====3.2、试给出一位全减器的算法描述和数据流描述LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL; ENTITY full_sub ISPORT(x, y,bi : IN Std_Logic;d,bo : OUT Std_Logic); END full_sub; 算法描述：ARICHITECTURE alg_fs OF full_sub IS BIGINPROCESS(x,y,bi) BEGINIF (x=‘0’ AND y=‘0’ AND bi=‘0’ OR x=‘1’ AND y=‘0’AND bi=‘1’ OR x=‘1’ AND y=‘1’ AND bi=‘0’ ) THENbo<=‘0'; d<=‘0’;ELSIF (x=‘1’ AND y=‘0’ AND bi=‘0’ ) THENbo<=‘0'; d<=‘1’;ELSIF (x=‘0’ AND y=‘1’ AND bi=‘1’ ) THENbo<=‘1'; d<=‘0’;ELSEbo<=‘1'; d<=‘1’;END IF;END PROCESS c1;END alg_fs;数据流描述：（d=x⊕y⊕bi bo=x’y+x’bi+ybi）ARICHITECTURE dataflow_fs OF full_sub ISBEGINd<=x XOR y XOR bi;bo<=(NOT x AND y) OR (NOT x AND bi)OR (y AND bi);END dataflow_ha;3.4、(1).十进制-BCD码编码器，输入、输出均为低电平有效。

LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0)b : OUT Std_Logic_Vector(3 DOWNTO 0));END encoder;ARCHITECTURE beh_encoder OF encoder ISBEGINWITH a SELECTb<= “0110” WHEN “0111111111”,“0111” WHEN “1011111111”,“1000” WHEN “1101111111”,“1001” WHEN “1110111111”,“1010” WHEN “1111011111”,“1011” WHEN “1111101111”,“1100” WHEN “1111110111”,“1101” WHEN “1111111011”,“1110” WHEN “1111111101”,“1111” WHEN “1111111110”,“0000” WHEN OTHERS;END beh_encoder;补充：优先编码器ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0)b : OUT Std_Logic_Vector(3 DOWNTO 0)); END encoder;ARCHITECTURE beh_encoder OF encoder IS BEGINWITH a SELECTb<= “0110” WHEN “0XXXXXXXXX”, “0111” WHEN “10XXXXXXXX”, “1000” WHEN “110XXXXXXX”, “1001” WHEN “1110XXXXXX”, “1010” WHEN “11110XXXXX”, “1011” WHEN “111110XXXX”, “1100” WHEN “1111110XXX”, “1101” WHEN “11111110XX”,“1110” WHEN “111111110X”, “1111” WHEN “1111111110”, “0000” WHEN OTHERS; END beh_encoder;(2).时钟RS 触发器。

QS CP RQLIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL; ENTITY clk_rs_ff ISPORT(r,s,cp:IN Std_Logic; q,nq : BUFFER Std_Logic); END clk_rs_ff ;ARCHITECTURE beh_clkrsff OF clk_rs_ff IS BEGINASSERT NOT(r=‘1‘ AND s=‘1')REPORT"Control error" SEVERITY Error; PROCESS(r,s,cp) BEGINIF cp=‘1’ THENq<= s OR (NOT r AND q);nq<= NOT( s OR (NOT r AND q)); END IF; END PROCESS; END beh_clkrsff;(3).带复位端、置位端、延迟为15ns 的响应CP 下降沿的JK 触发器。

QQS CP J KENTITY jk_ff ISGENERIC (tpd:Time:=15 ns);FORT (r,s,j,k,cp:IN Std_Logic; q,nq:BUFFEER Std_Logic); END jk_ff;ARCHITECTURE beh_jkff OF jk_ff ISBEGINASSERT NOT(r='0‘ AND s='0')REPORT "Control error" SEVERITY Error;PROCESS(r,s,cp)BEGINIF r=‘0’ THENq<=‘0’ AFTER tpd; nq<=‘1’ AFTER tpd;ELSIF s=‘0’ THENq<=‘1’ AFTER tpd; nq<=‘0’ AFTER tpd;ELSIF (cp’Event AND cp=‘0‘) THENq<=j AND nq OR NOT k AND q AFTER tpd;nq<=NOT( j AND nq OR NOT k AND q) AFTER tpd;END IF;END PROCESS;END beh_jkff;(4).集成计数器74161。

LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;USE IEEE.Std_Logic_Unsigned.ALL;ENTITY counter16 ISPORT (cr, ld, cp, ctt, ctp : IN Std_Logic;d : IN Std_Logic_Vector(3 DOWNTO 0);q : BUFFER Std_Logic_Vector(3 DOWNTO 0);co :OUT Bit);END counter16;ARCHITECTURE behav_ctr16 OF counter16 ISBEGINPROCESS (cr,cp)IF cr=‘0’ THENq<=“0000”;ELSIF (cp’Event AND cp=‘1’) THENIF ld=‘0’ THENq<=d;ELSIF (ctt=‘1’ AND ctp=‘1’) THENIF q=“1111” THENq<=“0000”;ELSEq<=q+“0001”;END IF;END IF;END IF;END PROCESS;co<=‘1’ WHEN (q=“1111” AND ctt=‘1’) ELSE ‘0’;END beh_ctr16;(5).集成移位寄存器74194。

LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY srg ISPORT(cr, cp : IN Std_Logic;d : IN Std_Logic_Vector(3 DOWNTO 0);sl, sr: IN Std_Logic;m: IN Std_Logic_Vector(1 DOWNTO 0);q: BUFFER Std_Logic_Vector(3 DOWNTO 0));END srg;ARCHITECTURE behav_srg OF srg ISPROCESS(cr, cp)BEGINIF cr=‘0' THENq<=“0000”; --异步复位ELSIF(cp’Event AND cp=‘1’) THENCASE m ISWHEN "01"=> q<=sr & q(3 DOWNTO 1); --右移WHEN "10"=> q<=q(2 DOWNTO 0) & sl; --左移WHEN "11"=> q<=d; --并行输入(同步预置)WHEN OTHERS=>NULL; --空操作，即保持END CASE;END IF;END PROCESS;END behav_srg;3.6、(2).由D触发器构成的异步二进制模8计数器Q0Q1Q2CPkLIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY asyn_ctr8 ISPORT(cp : IN Bit;q : BUFFER Std_Logic_Vector( 2DOWNTO 0));END ctr8;ARCHITECTURE struct_ctr8 OF asyn_ctr8 ISCOMPONENT d_ff PORT (clk,d : IN Std_Logic; q,nq :OUT Std_Logic);END COMPONENT;SIGNAL nq0,nq1,nq2 : Std_Logic;BEGINff0: d_ff PORT MAP(cp,nq0,q(0),nq0);ff1: d_ff PORT MAP(q(0),nq1,q(1),nq1);ff2: d_ff PORT MAP(q(1),nq2,q(2),nq2);END struct_ctr8;4.3、一位全减器：输入为x(被减数)、y(减数)、bi(低位借位)、d(差)和bo(本位向高位的借位) (1).PROM实现：(2).PLA实现：d boxybid bo Xybi4.10、QQQQD QQQ Q Q Q Z Q Q Q Q D Q QQ Q Q Q Q Q Z QQQ Q D Q nn n nn n n nn n nn n n n 1201212121220121110121121212010+==+=+==++=+==+++状态转换图：000/01001/11011/00111/11110/10100/01010/00101/00Q 2Q 1Q 0/Z 2Z 1。