OSD7516 字符叠加芯片用户手册
OSD7556 字符叠加芯片用户手册(V2.1)

命令 3:字符整行控制命令
15 – 12 11 10 9 8 7 6 5 4 3
2
1
0
0010
R3 R2 R1 R0
BLK_OFF BLK_ON CLR
位域 Bit15-Bit12 Bit11-Bit8
Bit7-Bit3 Bit2
缺省值 0010 0000
00 00
功能描述 命令码 行号值,0000 = 字符显示行 1。
1 = 该行闪烁功能禁止。 0 = 无作用。
7 / 31
Bit1
0
N 行显示闪烁使能标志位,该位设 1 表示使能整行的闪烁。
1 = 该行闪烁功能使能。
0 = 无作用。
Bit0
0
N 行显示内容清除命令,该位设 1 为清除该行所有显示内容,写 0
到该位无影响。
1 = 将整行内容全部清零。
0 = 无作用
20
VL2
21
NC
No Connected
22
NC
No Connected
23
VSS
数字电源地
24
VDD 数字部分电源
25
CS
SPI 片选信号
3.3V SPI 通信接口
26
SCLK SPI 时钟信号
27 SDOUT SPI 数据输出端口
28
SDIN SPI 数据输入端口
29
NC
30
NC
31
NC
32 HSYNC 混合同步输出信号 同步信号比较器的同步输出,如果 SYNC_IN 直连到 VIN 的话,则从该脚可以检测到同步信号比较器检 测到同步信号的质量,从而调整 SYNC_REF 得到最 佳的同步检测效果。
茵斯瑟150S6FS菲利普LCD显示器产品说明书

Philips38 cm (15")XGA150S6FSperformance and convenience maximize your budgetThis slim, compact 150S6 pumps up productivity with great performance andconvenience while business-friendly features like SmartManage deliver the best total costof ownership and lead-free design safeguards our environment.Best total cost of ownership solution•SmartManage compatibility enables LAN-based asset management•Power consumption below the industry average•Environmentally responsible Energy Star partner•Kensington anti-theft lock-ready for added securityOutstanding front of screen performance•16ms On/off response time: Better text and graphics display•XGA 1024x768 resolution for sharper display•sRGB ensures color matching between display and printoutsGreat convenience•Embedded power supply eliminates external power adaptors•Easy, user friendly plug-and-play installation•Convenient, built in holder for notes, cards or photos•Screen tilts to your ideal, individualized viewing angleHighlightsSmartManage enabledSmartManage is a system for monitoring, managing and checking status of display devices as well as delivering remote support to users who experience difficulties - all accomplished over a LAN.Lower power consumptionReduction of the electrical power required to operate a device.Kensington lock compatibleSmall apertures built into the display's frame for use with a locking device that secures a display to a fixed object for added protection against theft.16ms response time (On-Off)On-Off response time is the period required for a liquid crystal cell to go from active (black) to inactive (white) and back to active (black)again. It is measured in milliseconds. Faster isbetter: Lower response time means fastertransitions and, therefore, results in fewervisible image artifacts in the display oftransition of text and graphics. On-Offresponse time is a more important measure inthe display of business content like documents,graphs and photos.sRGB readysRGB is an industry standard that ensures thebest possible match between the colorsdisplayed on your screen and those in yourprintouts.Embedded power supplyAn embedded power supply is a poweradaptor built into the body of a display devicethat replaces a bulky external power adaptor.Easy plug-and-playPlug-and-play is a peripheral connectivitystandard. A plug and play display device can beconnected to a PC and operate withoutrequiring user intervention to adjustcomplicated settings.FlexiHolderFlexiHolder is a slim groove on the top ofmonitor that neatly and conveniently storesfavorite photos, reminders, to-do lists orphone numbers in your line of sight.Adjustable tiltAdjustable tilt is backward and forwardmovement of a screen on its base to achievecustom positioning for an ideal viewing angleand more comfort for people who spend longhours working on the computer.Issue date 2022-05-10 Version: 2.0.312 NC: 8639 000 16456 EAN: 87 10895 91089 7© 2022 Koninklijke Philips N.V.All Rights reserved.Specifications are subject to change without notice. Trademarks are the property of Koninklijke Philips N.V. or their respective owners.SpecificationsPicture/Display•LCD panel type: 1024 x 768 pixels, Anti-glare polarizer, RGB vertical stripe•Panel Size: 15"/ 38 cm•Effective viewing area: 304.1 x 228.1 mm •Pixel pitch: 0.297 x 0.297 mm•Brightness (nits): 250 nit•Contrast ratio (typical): 450:1•Display colors: 16.2 M•Viewing angle: @ C/R > 5•Viewing angle (H / V): 160 / 140 degree •Response time (typical): 16 ms•White Chromaticity, 6500K: x = 0.313 / y = 0.329•White Chromaticity, 9300K: x = 0.283 / y = 0.297•Maximum Resolution: 1024 x 768 @ 75 Hz •Optimum resolution: 1024 x 768 @ 60 Hz •Factory Preset Modes: 15 modes•User definable modes: 50 modes•Video Dot Rate: 80 MHz•Horizontal Scanning Frequency: 30 - 63 kHz •Vertical Scanning Frequency: 56 - 76 Hz •sRGBConnectivity•Signal Input: VGA (Analog )•Sync Input: Composite Sync, Separate Sync, Sync on GreenConvenience•User convenience: On-screen Display, SmartManage enabled•Monitor Controls: Auto, Brightness Control, Left/Right, Menu (OK), Power On/Off, Up/Down •OSD Languages: English, French, German, Italian, Simplified Chinese, Spanish•Other convenience: Kensington lock compatible, FlexiHolder•Plug & Play Compatibility: DDC/CI, sRGB, Windows 98/ME/2000/XP•Regulatory approvals: Energy Star, FCC Class B, UL•Tilt: -5° to 25°•VESA Mount: 100 x 100 mmAccessories•Included accessories: AC Power Cord, VGA cable •User ManualDimensions•Dimensions (with base) (W x H x D):342 x 344 x 180 mm•MTBF: 50,000 hrs•Relative humidity: 20% - 80%•Temperature range (operation): 5°C to 40°C •Temperature range (storage): -20°C to 60°C •Weight:2.7 kgPower•Complies with: Energy Star•Consumption(On mode): 17W (Typical)•Consumption(Off Mode): < 1 W•Power LED indicator: Operation - green, Stand by/ sleep - Amber•Power supply: Built-in, 90-264 VAC, 50/60 Hz。
OSD调节

on Screen display简介它通过显示在屏幕上的功能菜单达到调整各项参数的目的,不但调整方便,而且调整的内容也比以上的两种方式多,增加了失真、会聚、色温、消磁等高级调整内容。
像以前显示器出现的网纹干扰、屏幕视窗不正、磁化等需要送维修厂商维修的故障,举手之间便可解决。
另外在OSD选项里还可以调整显示的位置、无动作关闭显示的时间OSD:Object Sequence Diagram,对象顺序图,软件工程专用术语。
定义OSD 是 On Screen Display 的缩写,是应用在 CRT/LCD 显示器上,在显示器的荧幕中产生一些特殊的字形或图形,让使用者得到一些讯息。
常见于家用电视机或个人 PC 电脑之显示荧幕上,当使用者操作电视机换台或调整音量、画质等,电视荧幕就会显示目前状态让使用者知道,此控制 IC 可在荧幕上的任何位置显示一些特殊字形与图形,成为人机界面上重要的讯息产生装置。
技术原理OSD核心是利用字符发生芯片在显示器的屏幕上显示需要的字符。
常用的OSD芯片有MAX7456、OSD7556、OSD7516、UPD6465、MB90092等。
技术方式是:与图像实时同步附加或改变图像中某些像素的颜色,使之组合成人类可以在图像中辨识的数据。
以固定或不固定的方式,改变某个特定的OSD控制暂存器,即可达到动态的效果。
如:在荧幕上产生由左向右移动的OSD字形,只要将控制左右位置的OSD控制暂存器依序填入由小变大或由大变小的数值,OSD 输出字形自然随更改的数值而做左右移动。
技术应用比较典型的动态OSD应用:有用于处理、叠加银行柜员工作数据的“点钞机字符叠加器”;用于电梯监控的“电梯楼层字符叠加器”;用于高速公路、普通公路收费站的“收费系统字符叠加器”;还有用于公众场所,在播放视频节目的同时可使用字符叠加各种通知等信息的“信息发布叠加器。
”除此之外,还有常用的温湿度字符叠加器等。
[1]比较典型的静态OSD应用:是指不需要接收外部数据,即可在视频信号上显示相对固定形式字符信息的设备。
字符叠加芯片MB90092手册中文版

屏幕显示控制的专用标准产品CMOS屏幕显示控制芯片——MB900921.描述MB90092是用于显示控制视频中的文字和图像的视频显示控制芯片,内部集成了显示内存(VRAM)、外挂字库接口和视频信号发生器,其外部只需连接少量的电子元件就可以显示汉字和图形。
MB90092提供两种屏幕叠加方法,分别称为“主屏”和“副屏”,二者可单独或相互重叠出现在监视器上。
主屏由12行24个字符组成,允许设置每个字符的数据。
副屏由12行24个字符组成或最多达到16行24个字符。
数据不仅可以在前期配置的每行中被设置,也可以集中地在后期配置的整个屏幕中被设置。
MB90092所支持的字符为24×32点阵的普通字符和8×32点阵的图形字符,这些字符单元可以任意八种不同的颜色显示。
如果主屏中只有图形字符,则有192×384个像素点,在同样的情况下,副屏有192×384个像素点或256×512个像素点。
(实际显示屏由水平方向的像素点的时钟频率和电视系统垂直方向的一定光栅数决定。
)MB90092把RAM作为字库内存,能够显示自由图形。
MB90092总共能够使用16384种类型的字符,包括普通字符和图形字符。
它能够控制外部16M bits的字库内存。
对于视频信号的输出,MB90092具有合成视频信号,Y/C分离视频信号,RGB数字信号输出引脚。
MB90092还具有视频信号输入引脚,允许重叠显示任意一种复合视频信号和Y/C分离视频信号。
2.封装80个引脚的PQFP封装3.特性3.1主屏显示•屏幕显示能力:24字符×12行(达到288字符)•字符点配置:24×32点(每个字符)•字符类型:16384种字符(当使用16M比特的外部时钟)•字符大小:标准,双宽度,双高度,双宽度×双高度,四倍宽度×双高度(每行可设置)•显示位置控制:水平显示位置:1/3字符单元设置垂直显示位置:光栅单元设置行空间控制:光栅单元设置(0~15光栅)•显示优先级控制:副屏显示控制优先级的能力3.2副屏显示屏幕显示位置:可设置的水平和垂直为2个点单元•普通屏幕模式:屏幕显示能力:32字符×12行(达到384字符)56×384点(仅限图形字符)(实际显示屏幕由电视系统和点时钟频率决定)。
叠加器常用芯片有哪些?

叠加器常用芯片有哪些?常见的字符叠加器芯片主要有:1、MTV018,MTV030台湾世纪民生(MYSON)是最早专注于结合视频及通信领域开发的集成电路设计公司,在显示器MCU和屏幕显示(OSD)领域具有很高的全球市场占有率。
MYSON推出的专用字符叠加(OSD)芯片MTV018、MTV021、MTV030等,可以在屏幕上显示15行30列的字符,每个字符为12X18点阵,最高1524点/行的可编程水平分辨率,拥有强大的中文,数字,英文字库,可以根据需要调整并显示一些特效功能,比如字体颜色,闪烁,阴影,渐变等,产品成熟,应用简单,成本低廉。
2、UPD6453NEC公司推出的专用字符叠加(OSD)芯片,可以在屏幕上显示12行24列的字符,每个字符为12×18点阵,字符的大小、闪烁频率可以根据需要进行调整。
可以实现常规的英文、数字、及部分自定义字符的叠加显示。
但遗憾的是此芯片只支持外同步,就是自身不能直接输出字符信号,而只能在视频信号上进行叠加显示。
利用上位机提取12 x 12的点阵信息,然后发送给 UPD6453进行任意自定义字符的显示,成本低廉,还是有一定的应用意义的。
3、M35055三菱公司推出的专用字符叠加(OSD)芯片,可以显示24x10或32x7个字符,字库中包含了常用的大部分字符,具有内部同步和外部同步两种工作方式,这个方案外围电路比较简单,但需要外部振荡电路,IC不能直接接晶体。
和微控制器接口需要3根线,时序也比较简单,总体来说使用还是比较方便的。
4、MB90092富士通公司推出的专用字符叠加(OSD)芯片,在功能上可以说是目前所有的字符叠加芯片中功能最强的,但价格也是最贵的,在安防、楼宇对讲、信息发布等行业都有很广泛的应用。
芯片具有视频信号发生器、显示存储器(VRAM)和字形存储器接口,只需少量外部元件就可具备字符和图形显示功能,应用比较广。
5、STV5730AST公司推出的专用字符叠加(OSD)芯片,可以实现常规的英文、数字等的叠加显示。
LG ProBeam DLP投影仪 BU50NST-GL 使用说明书

用户手册DLP 投影仪使用产品前请阅读使用说明。
保留备用。
BU50NST-GLBU60PST-GLP/NO : SAC37813570 (2102-REV02)版权 © 2020 乐金电子(中国)有限公司版权所有。
2中文目录许可证 3开源软件提示信息 4安全预防措施 5准备工作 17安装 25遥控器 34连接设备 37规格 43标志 49故障排除 503中文许可证不同型号所支持的许可证可能会有所不同。
有关许可证的详细信息,请访问 。
HDMI、HDMI高清晰度多媒体接口以及HDMI标志是HDMI Licensing Administrator, Inc.在美国和其他国家的商标或注册商标。
本产品经过杜比实验室的许可而制造。
杜比, 杜比视界,杜比音效,杜比全景声,和双 D 符号是杜比实验室的注册商标。
有关 DTS 专利,请参阅 。
在获得 DTS Licensing Limited 许可的条件下制造。
DTS、符号、DTS 与符号同时出现、DTS 2.0 Channel、DTS 2.0+Digital Out、DTS-HD 和 DTS Virtual:X 是 DTS, Inc. 在美国和/或其他国家/地区的注册商标或商标。
© DTS, Inc. 保留所有权利。
注意• 所示的图像可能与您的投影仪有所不同。
• 投影仪的 OSD(在屏显示)可能与此手册的显示略有不同。
4中文开源软件提示信息为取得本产品内搭载的 GPL、LGPL、MPL 及其他开源证书下的源代码,请您访问 。
除源代码以外,所有相关的许可条款、免责声明和版权通知均可供下载。
LG Electronics 也可以 CD-ROM 的形式为您提供开源代码,如有需要,请发送电子邮件至******************,仅收取执行配送的费用(如介质费用、运输费和手续费)。
此报价从该产品出厂之日起,三年内有效。
此报价对收到本信息的任何人有效。
ic-751操作说明书
我收集正理了IC-751A正反面板的操作说明,提供有此机的爱好者使用,如有错误请提出。
第四节操作控制4. 1 前面板1 总电源开关(POWER)电源开关是一个按销式开关,它控制给IC—751A输入电源。
2 自动增益控制开关(AGC)此开关用于改变AGC电路的时间常数。
该开关在OFF时AGC不起作用。
该开关置于SLOW 位置时AGC电压适用于单边带接收。
将开关置于FAST位置时AGC电压控制适用于有衰弱影响和工作于等幅报模式。
3 电表开关(METER)此开关有6种工作模式1.SWR(显示驻波)2 PO(输出功率)3 ALC (自动电平控制指示)4 COMP (音压缩电平) 5 IC (功放集电极电流) 6 VC (功放集电极电压)4 收/发转换开关(TRANSMIT)该开关是用于人工控制接收和发射状态,在(TRANISMIT)上时是发,在(RECEIVE)下时是接收。
在用手咪和台咪时开关要在下挡(RECEIVE)。
5 话筒连接器(MICROPHONE)该位置可连接手咪话筒和台试话筒。
6 耳机插座(PHONES)可插入一个为1/4英寸阻抗为4-16欧姆的标准耳机。
7 音频增益控制(AF GAIN)内旋在接收模式时控制音频输出电平,顺时针旋转时电平增加。
8 射频增益控制(RF GAIN)外旋在接收模式时控制射频部分增益。
顺时针可最大一般都在最大位置。
FM模式不起作用。
9 静噪控制(SQUELCH)调整静噪阀值电平。
反时针不动是关闭静噪功能(一般在此位置),顺时针是调高电平。
10 音调控制(TONE)控制接收机的音频声调,调节此旋可提供舒适的接收音调。
11 话筒增益控制(MIC GAIN)根据话筒的输入来调节调制电平,顺时针旋转可使话筒增益增加。
因为输入的信号由于使用了不同的话筒或声音不同而要变化,所以应当旋动旋使电表指针在ALC模式时慢慢地移动。
在单边带模式使用语音处理器时,将话筒增益控制调到限幅状态。
AEO G-OSD 用户手册说明书
AEO TECHNOLOGY AEO G-OSD User Instruction ManualProduct Introduction:Welcome to use AEO GPS-OSD,which is specially designed for micro electric-powered plane with following features:● GPS coordinate display, time display, airspeed display● voltmeter and stopwatch● RSSI receiver signal strength detection● Programming the display content● Support NTSC and PAL TV signal● Support anti-glare shade control signal● Support manual calibration1. Hardware Specification:Weight: main board 4.6g GPS module 22gSize: main board 34mm*20mm*4mm GPS Module 35mm*35mm*5mmWorking Voltage:G-OSD 7.4V-12V GPS Module 5V2. Connection & Button Introduction:2.1 BATT1—Power Supply Port:G-OSD power supply port, commonly parallel with powerbattery.2.2 BATT2—Auxiliary Equipment Voltage Detection Port(Auxiliary):Detect the equipment voltage connected to this port, andused to measure auxiliary equipment voltage.2.3 RSSI—Receiver Signal Strength DetectionDetect the signal strength pin voltage value on RCreceiver signal decode chip, the user can know the RCreceiver wireless signal strength from RC transmitter by thisvoltage value.2.4 GPS—Global Position System Module PortConnect the GPS module for positioning, measure the speed and time.2.5 Video—Video Overlay Port:Be responsible for outputting the overlaid video signal to video port equipment.Suggested Connection Picture:AEO TECHNOLOGY 3. Interface Introduction:3.1 GPS coordinate display.3.2 Local time and receiver signal strength detection.3.3 GPS signal lock(IND:unlocked/FIX:locked)andGPS module altitude at current position.3.4 V1:G-OSD power voltage display,V2: auxiliaryequipment voltage detection display.3.5 Airspeed(KM/H)and stopwatch display.(Britishsystem version is British system displaying)4.Manual Calibration Setting:There are three buttons and a switch at the back of the G-OSD,the functions respectively as follows:4.1 Manually calibrate the BATT1 voltage value.4.2 Manually calibrate the BATT2 voltage value.4.3 Manually calibrate the RSSI displayingvalue.4.4 Calibrate the OSD value displayinginterface.We suggest using high-precision voltmeterwhile manually calibrate the voltage.Time Zone option mode: Press the buttonshow in above picture 4.4 in the condition of normal connection and blackout, then will come into the time zone option mode.000--023 is the 24 time zones, respectively stands for Prime Meridian—East 12 zone—West 11 zone –West 1 zone--- Prime Meridian .The increase of value stands for increasing zone to East, for example in the below picture the “008”stands for East 8 zone Beijing time.”019” stands for West 5 zone New York time.5.Attention:5.1 The time of locking GPS position relates to signal strength, generally needs about one minute, meantime must sure there’s no signal interference surroundings.5.2 This OSD is specially designed for micro electric-powered plane, cannot change to any other usage.5.3 Please use this product within reliable distance, do not let the plane beyond the view distance.5.4 Please operate the plane at open and no man’s land.5.5 Please supply the power in strict accordance with safe power voltage, and use the low-noise, reliable power module or battery system.5.6 Please do not arbitrarily maintain, rebuild, detect or upgrade this product.5.7 Please do not let the children play this product, or put the product into the mouth.5.8 Forbid to use this product at gas station and other places where definitely regulate no use for wireless signal.。
SYN8086 语音合成芯片_用户手册说明书
中文语音合成芯片用户手册北京宇音天下科技有限公司************************宇音天下官方订阅号宇音天下售前咨询历史版本版本发布日期内容描述1.0 2021/12/28 首次发布版本1.1 2022/04/15 修改公司网址重要声明版权声明版权归北京宇音天下科技有限公司所有,保留所有权利。
商标声明北京宇音天下科技有限公司的产品是北京宇音天下科技有限公司专有。
在提及其他公司及其产品时将使用各自公司所拥有的商标,这种使用的目的仅限于引用。
本文档可能涉及北京宇音天下科技有限公司的专利(或正在申请的专利)、商标、版权或其他知识产权,除非得到北京宇音天下科技有限公司的明确书面许可协议,本文档不授予使用这些专利(或正在申请的专利)、商标、版权或其他知识产权的任何许可协议。
不作保证声明北京宇音天下科技有限公司不对此文档中的任何内容作任何明示或暗示的陈述或保证,而且不对特定目的的适销性及适用性或者任何间接、特殊或连带的损失承担任何责任。
本手册内容若有变动,恕不另行通知。
本手册例子中所用的公司、人名和数据若非特别声明,均属虚构。
未得到北京宇音天下科技有限公司明确的书面许可,不得为任何目的、以任何形式或手段(电子的或机械的)复制或传播手册的任何部分。
保密声明本文档(包括任何附件)包含的信息是保密信息。
接收人了解其获得的本文档是保密的,除用于规定的目的外不得用于任何目的,也不得将本文档泄露给任何第三方。
本软件产品受最终用户许可协议(EULA)中所述条款和条件的约束,该协议位于产品文档和/或软件产品的联机文档中,使用本产品,表明您已阅读并接受了EULA 的条款。
版权所有:北京宇音天下科技有限公司目录1概述 (6)2特别说明 (6)3主要应用领域 (6)4产品功能描述 (6)5订货信息 (8)6系统构成框图 (8)7引脚定义 (9)8芯片控制方式 (10)8.1控制命令 (10)8.2芯片回传 (11)9通讯方式 (11)9.1异步串行通讯模式(UART) (11)9.1.1硬件连接 (11)9.1.2通讯传输字节格式 (12)9.1.3波特率配置方法 (12)10通信帧定义及通信控制 (12)10.1命令帧格式 (13)10.2芯片支持的控制命令 (13)10.3命令帧相关的特别说明 (14)10.3.1深度睡眠与唤醒说明 (14)10.3.2其它特别说明 (14)10.4命令帧举例 (14)10.4.1语音合成播放命令 (14)10.4.2停止合成命令 (16)10.4.3暂停合成命令 (16)10.4.4恢复合成命令 (16)10.4.5芯片状态查询命令 (17)10.4.6芯片进入Deep sleep模式命令 (17)10.4.7芯片唤醒命令 (17)11产品规格 (18)11.1封装 (18)11.2特性参数 (19)11.2.1极限值 (19)11.2.2推荐电压工作范围 (19)11.2.3音频DAC特性 (19)11.2.4芯片各状态下的功耗参数 (19)11.2.5接收合成命令到开始播音间隔时间 (20)11.3焊接工艺要求 (20)11.3.1烘烤温度及时间 (20)11.3.2回流焊的峰值温度 (20)12附录 (21)12.1文本控制标记 (21)12.2文本控制标记使用示例 (23)12.2.1标记[i*] –识别汉语拼音 (23)12.2.2标记[m*] –发音人选择 (23)12.2.3标记[n*] –数字处理策略 (24)12.2.4标记[p*] –静音一段时间 (24)12.2.5标记[r*] –姓氏读音策略 (24)12.2.6标记[s*] –语速调节 (24)12.2.7标记[t*] –语调调节 (25)12.2.8标记[v*] –音量调节 (25)12.2.9标记[x*] –提示音策略 (25)12.2.10标记[y*] –号码1的读法 (25)12.2.11标记[z*] –韵律标注处理策略 (26)12.2.12标记[=*] –强制单个汉字的拼音 (26)12.2.13标记[f*] –发音风格 (26)12.2.14标记[b*] –读标点策略 (26)12.2.15标记[d] –恢复默认 (26)12.3提示音 (27)12.4上位机对SYN8086芯片的调用方式 (28)12.4.1简单调用方式 (28)12.4.2标准调用方式 (29)12.5查询芯片工作状态的方法 (29)12.6芯片识别的编码体系和范围 (29)12.6.1GB2312编码体系 (29)12.6.2GBK编码体系 (30)12.6.3BIG5编码体系 (30)12.6.4Unicode编码体系 (30)13发送合成文本的示例程序 (31)13.1 C 语言范例程序 (31)13.2汇编语言范例程序 (33)1概述SYN8086语音合成芯片是北京宇音天下科技有限公司于2021年12月最新推出的一款性/价比更高,效果更自然的一款高端语音合成芯片。
智能融合cSoC:多通道FFT共享处理器使用FPGA纤维说明书
Application Note AC381February 20121© 2012 Microsemi Corporation SmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA FabricTable of ContentsIntroductionThe SmartFusion ® customizable system-on-chip (cSoC) device integrates FPGA technology with a hardened ARM ® Cortex™-M3 processor based microcontroller subsystem (MSS) and programmable high-performance analog blocks built on a low power flash semiconductor process. The MSS consists of hardened blocks such as a 100 MHz ARM Cortex-M3 processor, peripheral direct memory access (PDMA), embedded nonvolatile memory (eNVM), embedded SRAM (eSRAM), embedded FlashROM (eFROM), external memory controller (EMC), Watchdog Timer, the Philips Inter-Integrated Circuit (I 2C),serial peripheral interface (SPI), 10/100 Ethernet controller, real-time counter (RTC), GPIO block, fabric interface controller (FIC), in-application programming (IAP), and analog compute engine (ACE).The SmartFusion cSoC device is a good fit for applications that require interface with many analog sensors and analog channels. SmartFusion cSoC devices have a versatile analog front-end (AFE) that complements the ARM Cortex-M3 processor based MSS and general-purpose FPGA fabric. The SmartFusion AFE includes three 12-bit successive approximation register (SAR) ADCs, one first order sigma-delta DAC (SDD) per ADC, high performance signal conditioning blocks, and comparators. The SmartFusion cSoCs have a sophisticated controller for the AFE called the ACE. The ACE configures and sequences all the analog functions using the sample sequencing engine (SSE) and post-processes the results using the post processing engine (PPE) and handles without intervention of Cortex-M3 processor.Refer to the SmartFusion Programmable Analog User’s Guide for more details.This application note describes the capability of SmartFusion cSoC devices to compute the Fast Fourier Transform (FFT) in real time. The Multi Channel FFT example design can be used in medical applications, sensor network applications, multi channel audio Spectrum analyzers, Smart Metering, and sensing applications (such as vibration analysis).This example design uses the Cortex-M3 processor in the SmartFusion MSS as a master and the FFT processor in the FPGA fabric as a slave. All three of the SmartFusion cSoC A2F500’s ADCs are used for data acquisition. The example design uses Microsemi’s CoreFFT IP and the advanced peripheral bus interface (CoreAPB3). A custom-made APB3 interface has been developed to connect CoreFFT with the MSS via CoreAPB3. The Cortex-M3 processor uses the PDMA controller in the MSS for the data transfer and thus helps to free up the Cortex-M3 processor instruction bandwidth.A basic understanding of the SmartFusion design flow is assumed. Refer to Using UART with SmartFusion - Microsemi Libero ® SoC and SoftConsole Flow Tutorial to understand the SmartFusion design flow.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Implementing Multi Channel FFT on EVAL KIT BOARD . . . . . . . . . . . . . . . . . . . . . . . . . 7Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Appendix A – Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10SmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA Fabric2Design OverviewThis design example demonstrates the capability of the SmartFusion cSoC device to compute the FFT for multiple data channels. The FFT computation is a complex task that utilizes extensive logic resources and computation time. In general, for N number of channels, N number of FFT IP’s are needed to be instantiated, which in turn utilize more logic resources on the FPGA. A way to avoid this limitation is to use the same FFT logic for multiple input channels.This design illustrates the implementation of a Multichannel FFT to process multiple data channels through a single FFT and store FFT points in a buffer. The FFT computes the input data read from each channel and stores the N-point result in the respective channel’s allocated buffer. The channel multiplexing is done once each channel buffer has been loaded with the FFT length.Computing frequency components for a real time data of six channels is described in this application note. For sampling the input signals the AFE is used and the complex FFT computation is implemented in the fabric of the SmartFusion cSoC device. The Cortex-M3 processor in the MSS of the SmartFusion cSoC handles the buffer management and channel muxing.Figure 1 depicts the block diagram of six channel FFT co-processor in FPGA fabric.Design DescriptionThe design uses CoreFFT for computing the FFT results. You can download the core generator for CoreFFT at /soc/portal/default.aspx?r=4&p=m=624,ev=60.The design example uses a 512-point and 16-bit FFT. A custom-made APB3 interface has been developed to connect CoreFFT IP with the MSS’s FIC. The CoreFFT output data is stored in a 512x32FIFO within the fabric. The FIFO status signals are given in Table 1 on page 3. The status signals indicate that FFT is ready to receive data and data is available in the output of FIFO. These status signals are mapped to the GPIOs in the MSS. The Cortex-M3 processor can read the GPIOs to handle flow control in the data transfer process from the MSS to CoreFFT.Figure 1 • Multi Channel FFT Block DiagramDesign Description3Figure 2 shows the block diagram of logic in the fabric with custom-made APB3 bus.The data valid signal (ifiD_valid) is generated in custom logic whenever the master needs to write data into the input buffer of the FFT to process through the APB3 interface. The FFT_IP_RDY signal indicates the status of the input buffer of the FFT. If the input buffer is full, the FFT_IP_RDY goes low. The master can read the FFT_IP_RDY signal to get the FFT input buffer status. The FFT generates the processed data with a data valid signal (ifoY_valid). The processed data is stored in the FIFO. When FIFO is not ready to receive output data, it can stop the data fetching from the FFT by pulling down the ifiRead_y signal. The status signal FFT_OP_RDY is used to indicate to the master that processed data is available in the FIFO. FFT_OP_RDY goes High whenever processed data is available in the FFT output buffer.The master can use AEMPTY_OUT or EMPTY_OUT to determine whether the FIFO is empty and all the processed data has been read. Refer to the CoreFFT Handbook for more details on architecture and interface signal descriptions.Three ADCs are configured to have two channels, each channel with 100 ksps sampling rate. The external memory is used for input and output buffers. For each channel, one input buffer having length double to the length of FFT i.e. 1024 words and one output buffer having length equal to the length of FFT i.e. 512 words are used. After each channel's input buffer has 512 points required for the full length of the FFT, each channel, one after the other, streams its points from the FIFO through the FFT. During the FFT computational period, the sampled data values of each channel are stored in the second half of the input buffer. Once the FFT computations for the First half of input buffer completes then the points in the second half of the input buffer will be streamed to FFT. This operation utilizes a ping-pong method. The Cortex-M3 processor is used for data management, that is, buffering the sampled points and data routing or muxing of these values to the FFT computation block. Sampling of the real time data is done by the ACE. The PDMA handles the data transfer between the external SRAM (eSRAM) buffers and CoreFFT logic in FPGA fabric.Figure 2 • CoreFFT with APB Slave InterfaceTable 1 • FIFO Status Signals with DescriptionsSignalDescription FFT_IP_RDYFFT is ready to receive the Input from the master processor FFT_OP_RDYProcessed data is ready in output buffer of FFT AEMPTY_OUTOutput FIFO is almost empty EMPTY_OUT Output FIFO is emptySmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA Fabric4Figure 3 shows the implementation of multi channel FFT on the SmartFusion cSoC device.Hardware ImplementationThe MSS is configured with an FIC, clock conditioning circuit (CCC), GPIOs, EMC and a UART. The CCC generates 80 MHz clock, which acts as the clock source. The FIC is configured to use a master interface with an AMBA APB3 interface. Four GPIOs in the MSS are configured as inputs that are used to handle flow control in data transfer from MSS to FFT coprocessor. The EMC is configured for Region 0as Asynchronous RAM and port size as half word. The UART_0 is configured for printing the FFT values to the PC though a serial terminal emulation program.ADC0, ADC1, and ADC2 are configured with 12-bit resolution, two channels and the sampling rate is set to approximately 100 KHz. Figure 4 on page 5 shows the ACE configuration window.Figure 3 • Implementation of Multi Channel FFT on the SmartFusion cSoCDesign Description5The APB wrapper logic is implemented on the top of CoreFFT and connected to CoreAPB3. A FIFO of size 512*32 is used to connect to CoreFFT output.CoreAPB3 acts as a bridge between the MSS and the FFT coprocessor block. It provides an advanced microcontroller bus architecture (AMBA3) advanced peripheral bus (APB3) fabric supporting up to 16APB slaves. This design example uses one slave slot (Slot 0) to interface with the FFT coprocessor block and is configured with direct addressing mode. Refer to the CoreAPB3 Handbook for more details on CoreAPB3 IP .For more details on how to connect FPGA logic MSS, refer to the Connecting User Logic to the SmartFusion Microcontroller Subsystem application note.The logic in the FPGA fabric consumes 18 RAM blocks out of 24. We cannot use eSRAM blocks for implementing CoreFFT as the transactions between these SRAM blocks and FFT logic are very high and are time critical.Figure 5 on page 6 illustrates the multi channel FFT example design in the SmartDesign.Figure 4 • Configure ACESmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA Fabric6Table 2 summarizes the logic resource utilization of the design on the A2F500M3F device.Software ImplementationThe Cortex-M3 processor continuously reads the values from ACE and stores the values into the input buffers. If the first 512 points are filled then the processor initiates the FFT process. In the FFT process,the input buffers are streamed one after other to the CoreFFT with the help of PDMA. Using another channel of PDMA the output of FFT is moved to the corresponding channel output buffers.During the FFT process the Cortex-M3 processor stores the sampled values into the second half of the input buffers. Once the FFT process completes the first half of input buffer, then the second half of the input buffer are streamed to CoreFFT.Figure 5 • SmartDesign Implementation of Multi Channel FFTTable 2 • Logic Utilization of the Design on A2F500M3FCoreFFTOther Logic in Fabric Total Ram Blocks14418 (75%)Tiles 78424718313 (72.1%)Implementing Multi Channel FFT on EVAL KIT BOARD7The CALL_FFT(int *) application programmable interface (API) initiates the PDMA to transfer input buffer data to the FFT in the fabric. Before initiating PDMA it checks for FFT whether or not it is ready to read the data. The CALL_FFT(int *) API also checks if the output FIFO is empty so that all the FFT out values have been already read. When the input buffer has points equal to the full length of FFT, then it will be called.The Read_FFT() API initiates the PDMA for reading the FFT output values from FIFO in fabric to the corresponding output buffer. After reading all the values it calls the CALL_FFT() API with the next channel buffer to compute the FFT for next channel. This is done for all channels. After completion of FFT computation for all channels, if the continuous variable is not defined, it will print the FFT output values on the serial terminal. When FFT_OP_READY interrupt occurs then this API will be called.The GPIO1_IRQHandler() interrupt service routine occurs on the positive edge of FFT_OP_READY signal. It calls Read_FFT() API. This interrupt mechanism is used to read the sample values continuously while computing the FFT.If continuous variable is defined, then the FFT is computed without any loss of data samples. If #define continuous line is commented then after every completion of FFT computation of all channels the FFT output is printed on serial terminal. The printed values are in the form of complex numbers.The ping-pong mechanism is used for input data buffer to store the samples continuously. For each channel the input buffer length is double of the full FFT length. While computing the FFT for the first half of the buffer, the new sample values are stored in the second half of the input buffer and while computing the FFT for second half of buffer, the new sample values are stored in first half of the input buffer.Customizing the Number of ChannelsYou can change the design depending on your requirement. Configure the ADC (Figure 4 on page 5)with the required number of channels and required sampling rate. In SoftConsole project change the parameter value NUM_CHANNELS according to the ADC configuration. Edit the main code for reading ADCs data into buffers according to ACE configuration.Throughput CalculationsThe actual time to get 512 samples with 100 ksps is 5.12 ms. Each channel is configured to 100 ksps, so for every 5.12 ms we will have 512 samples in the input buffers.The actual time taken to compute the FFT for each channel is the sum of time taken to transfer 512points to CoreFFT, FFT computation time, and time to read FFT output to the output buffer.•Total time for computing FFT = (time taken to receive 512 data + computational latency for 512points + time taken to store 512 data) = 512*5 + 23292 + 512*5 =28412 clks •Time to compute FFT for 6 channels = 28412*6 = 170472 clksTime to compute FFT for six channels is 2.1309 ms (If CLK is 80 MHz). It is less than half the sample rate of 5.12 ms.If only one channel is configured with maximum sampling rate (600 ksps) then time to get 512 samples with 600 ksps is 0.853 ms. Time to compute FFT for these 512 samples is 0.355 ms. If you configure three ADCs with maximum sampling rate (1800 ksps) then time to compute the FFT for these three channels will be 1.065 ms which is higher than the sampling time. In this there is a loss of some samples.The design works fine up to 1440 ksps.Implementing Multi Channel FFT on EVAL KIT BOARDTo implement the design on the SmartFusion Evaluation Kit Board the FFT must be 256 point and 8 bit because the A2F200 device has less RAM blocks and logic cells. The ADC channels must be selected for only ADC0 and ADC1. Figure 6 on page 8 shows the implementation of multi channel FFT on the SmartFusion cSoC (A2F200M3F) device.SmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA Fabric8Table 3 summarizes the logic resource utilization of the design with 256 points 8-bit FFT on A2F200M3F device.Running the DesignProgram the SmartFusion Evaluation Kit Board or the SmartFusion Development Kit Board with the generated or provided *.stp file (refer to "Appendix A – Design Files" on page 10) using FlashPro and then power cycle the board.For computing continuous FFT values for the all six signals sampled through the ADCs, uncomment the line #define continuous in the main program. The FFT output values are stored in the rdata buffer. This buffer is updated for every computation of FFT.For printing the FFT values on serial terminal (HyperTerminal or PuTTy), comment the line #define continuous in the main program.Figure 6 • Implementation of Multi Channel FFT on the SmartFusion Evaluation Kit BoardTable 3 • Logic Utilization of the Design on A2F200M3F DeviceCoreFFTOther Logic in Fabric Total Ram Blocks718 (100%)Tiles 3201853286 (66%)Conclusion9Connect the analog inputs to the SmartFusion Kit Board with the information provided in Table 4.Invoke the SoftConsole IDE, by clicking on Write Application code under Develop Firmware in Libero ®System-on-Chip (SoC) project (refer to "Appendix A – Design Files") and launch the debugger. Start HyperTerminal or PuTTY with a baud rate of 57600, 8 data bits, 1 stop bit, no parity, and no flow control.If your PC does not have the HyperTerminal program, use any free serial terminal emulation program such as PuTTY or Tera Term. Refer to the Configuring Serial Terminal Emulation Programs Tutorial for configuring the HyperTerminal, Tera Term, or PuTTY .ConclusionThis application note describes the capability of the SmartFusion cSoC devices to compute the multi channel FFT. The Cortex-M3 processor, AFE, and FPGA fabric together gives a single chip solution for real time multi channel FFT system. This design example also shows the 6-channel data acquisition system.Table 4 • SettingsChannelEvaluation Kit Development Kit Channel 173 of J21 (signal header)ADC0 of JP4Channel 274 of J21 (signal header)ADC1 of JP4Channel 377 of J21 (signal header)77 of J21 (signal header)Channel 478 of J21 (signal header)78 of J21 (signal header)Channel 585 of J21 (signal header)Channel 686 of J21 (signal header)Figure 7 • FFT Output Data for 1 kHz Sinusoidal Signal on PUTTYSmartFusion cSoC: Multi-Channel FFT Co-Processor Using FPGA Fabric10Appendix A – Design FilesThe Design files are available for download on the Microsemi SoC Product Groups website:/soc/download/rsc/?f=A2F_AC381_DF.The design zip file consists of Libero SoC projects and programming file (*.stp) for A2F200 and A2F500.Refer to the Readme.txt file included in the design file for directory structure and description.51900249-0/02.12© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996。
- 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。
应用
★ 安防监控系统 ★ 安全监控摄像机 ★ 工业应用 ★ 家庭娱乐系统 ★ 其他需要视频字符叠加的应用
电气特性
极限参数
符号
描述
最低值
最高值
Vdd-Vss
外部供电电压
-0.3
4
Vspi-Vss
通信数据线耐受电压
-0.3
5.5
Twork
工作温度
-40
85
Tstg
储存温度
-40
150
注意:不要超出上表所列的环境条件,否则芯片可能无法正常工作甚至受损坏。
6 / 31
(2)在发送清除屏幕显示内容之后,最大需等待 2 个视频行同步之后(64uS×2)才 能送显示内容进入视频缓冲区,否则有可能清除动作尚未完成而被清除掉该显示内容。
命令 2:显示移位位置控制
15 – 12 0001
11 10 9 8 7 6 5 4 3 2 1 0
V4 V3 V2 V1 V0
命令 3:字符整行控制命令15 – 12 11 10 9 8 7 6 5 4 3
2
1
0
0010
R3 R2 R1 R0
BLK_OFF BLK_ON CLR
位域 Bit15-Bit12 Bit11-Bit8
Bit7-Bit3 Bit2
缺省值 0010 0000
00 00
功能描述 命令码 行号值,0000 = 字符显示行 1。
36 SW_WHITE 字符信号白电平开 字符信号的白色电平输出开关 关输出端口
37
NC
4 / 31
38
NC
39
NC
40
NC
41
NC
42
NC
43
NC
44
CFG0 配置脚
45
NC
No Connected
46
NC
No Connected
47
VSS
数字电源地
48
VDD 数字部分电源
请使用一个 4.7K-10K 电阻将其接入地。 3.3V
0 = 该字符闪烁显示功能关闭
VRAM 字符地址的分区码,OSD 芯片中共分有 4 个区域存储字符点阵,
第 1 区为固化在芯片内部空间的 96 个 12×18 点阵英文字符和符号,
第 2 区为用户定制在 RAM 中的 64 个 16×18 点阵字符,第 3 区包括
固化在芯片内部的 384 个 16×18 点阵汉字,第 4 区为特殊间隔码(因 为该芯片支持 12×18 点阵和 16×18 点阵的混合显示,如果用户想
1 = 该行闪烁功能禁止。 0 = 无作用。
7 / 31
Bit1
0
N 行显示闪烁使能标志位,该位设 1 表示使能整行的闪烁。
1 = 该行闪烁功能使能。
0 = 无作用。
Bit0
0
N 行显示内容清除命令,该位设 1 为清除该行所有显示内容,写 0
到该位无影响。
1 = 将整行内容全部清零。
0 = 无作用
写 0 到该位无影响。
Bit2
1
自动同步切换功能开关位,当外部视频同步信号丢失时,是否自动
切换为内部视频同步信号。在内部视频同步时,检测到外部同步信
号时,则自动切换回外部视频信号同步状态。
1 = 自动切换使能(ENABLE)
0 = 自动切换禁止(DISABLE),在自动切换禁止状态,强制为视 频外同步模式。
写数据
读数据
命令 1:视频显示模式设定
15 – 12 0000
11 10 9 8 7 6 5 CLR BT
43210
RST SW
EN
位域
缺省值
功能描述
Bit15-Bit12 0000 命令码
Bit11-Bit8 00000 Reserved
Bit7
0
VRAM 清理操作,1 = 将所有的显示内存 VRAM 全部清 0,该位硬件
为 96 个相应的有效字符点阵数据地址。
01 = 第 2 区(RAM 区 16×18 点阵字符),C7,C6 为无效,C5-C0
为有效的字符点阵数据地址。
10 = 第 3 区(芯片内置 16×18 点阵汉字字符),C8-C0 为 384
★ RAM 可实时更改字符共 64 个汉字字符(64 个 16×18 点阵汉字),提供专用的字符 点阵生成软件,不存在 RAM 字符字体和内置字体不一致的问题。
★ 可单独设定每一个显示字符单位(汉字和英文字符)闪烁功能。 ★ 最多可显示 14 行×28 列标准显示单位,满屏最多可显示 392(14×28)个英文字
Bit1
0
Reserved
Bit0
0
OSD 功能开关位,1 = 启动字符叠加功能模块(OSD ENABLE)
0 = 关闭字符叠加功能模块(OSD DISABLE)
注意:(1)Bit8 相当于清除屏幕显示内容,而显示控制方式并不发生变化;Bit3 是相当于芯
片复位,不仅清除屏幕显示内容,而且所有的控制寄存器会初始化成缺省值。
H4 H3 H2 H1 H0
位域 Bit15-Bit12 Bit10-Bit6
Bit4-Bit0
缺省值 0001 01000
01000
功能描述 命令码 垂直位置寄存器,起始位置为场同步后第 9 行开始,最大位移为 64 行, 00000 = 9H + 0
00001 = 9H + 1 00010 = 9H + 2 ………………… 11111 = 9H + 31 水平位置寄存器,起始位置为每行的 12us 处开始,每一个移位单 位为 2/Fclk, 00000 = 12uS + 0 * 2/Fclk 00001 = 12uS + 1 * 2/Fclk 00010 = 12uS + 2 * 2/Fclk ……………………………… 11111 = 12uS + 31 * 2/Fclk
0001 = 字符显示行 2。 0010 = 字符显示行 3。 0011 = 字符显示行 4。 ………………………… 1111 = 字符显示行 16。 OSD 芯片最多支持 14 行显示,所以行号超出所规定范围之后的命 令将被直接忽略。
Reserved N 行显示闪烁禁止标志位,该位设 1 表示禁止该行的闪烁功能。
要在某个位置对齐的话,中间可能需要填补一个或几个不同于 12× 18 的空格字符符号,第 4 区则为可以填入不同宽度的空字符,具体
包括 4×18、8×18、12×18、16×18、20×18、24×18、28×18、 32×18 等不同的 8 种特殊间隔符号)。
A1,A0
00 = 第 1 区(芯片内置 12×18 点阵字符),C7 为无效位,C6-C0
OSD7516 具有唯一 ID 码的 16 点阵汉字字符叠加芯片 用户手册
(版本:V1.0)
版本修改说明:
序号 1 2 3
第一次释放版本
修改说明
参考页面
版本 V1.0
1 / 31
特性
★ 支持标准的英文字符显示(12×18)和 16 点阵汉字字符显示(16×18)的混合显 示。
★ 内置字符共支持 96 个英文字符及符号和 384 个 16 点阵汉字字符,通过专用字符生 成工具可在生产时由用户定制所需的汉字字符及其自定义图标等。
接入 VIN,或者已经被同步分离器器检测分离出来
的同步信号。
12
VIN
视频信号输入端 视频信号输入
13
NC
No Connected
14
VBLK 黑色信号电压输出 字符信号黑电平亮度输出端口
15
NC
No Connected
16
NC
No Connected
17 VSYNC 场同步输出端口 检测到分离的场同步信号输出
= 1,每一次写 VRAM 数据之后,VRAM 地址自动递增加 1。 = 0,每一次写 VRAM 数据之后,VRAM 地址不变。 Reserved VRAM 地址,VRAM 地址超出显示范围,则直接忽略该命令。 VRAM 地址设定请参考下面的图所示
显示内存区域(VRAM)示意图 0 28 …… Display Area (14 Rows × 28 Characters) ……
单位 V V ℃ ℃
2 / 31
工作特性
符号 Vdd Vspih Vspil Fclk VIN Iopr
描述 电源电压 SPI 数字信号输入高电平 SPI 数字信号输入低电平 时钟频率 视频输入信号 工作电流
管脚图
最低 标准 最高
+3.0 +3.3 +3.6
+2.7
+5.0
+0.8
17.734475
364
27
Line 0
55
Line 1
391 Line 13
应用注意点:
1, 显示内存区域为 14×28 个位置,即满屏显示内容为 14 行,每行 28 个 12×18 点阵字符 位置。
2, 每一行的显示像素为 28×12=336 点,即芯片可支持的每行显示像素点为 336 个,而汉 字点阵为 16×18,所以,每一行显示的汉字数最多为 336/16=21 个汉字。
命令格式及寄存器分配
SPI 通讯格式描述: OSD7556 支持高达 10MHz 的接口时钟(SCLK),SPI 模式设定为:CPHA = 0,CPOL = 0。具体 规格如下图所示:
5 / 31
所有的命令均为 16bit 长度,高位的 4bit 为命令识别码,低位的 12bit 为附加数据位。读写 命令分别如下图所示:
15 – 12 0100
11 10 9 8 7 6 5 4 3 2 1 0 BL A1 A0 C8 C7 C6 C5 C4 C3 C2 C1 C0