testbench仿真程序编写举例

数字基础—仿真实例零基础电子设计系列课程

主讲人：范秋华

国家级电工电子实验教学中心（青岛大学）

4.5.4Testbench仿真程序实例

?激励产生举例：多位位矢量所有可能输入情况的产生?组合逻辑电路：2位全加器的设计与验证

?时序逻辑电路：六进制计数器的设计与验证

国家级电工电子实验教学中心

激励产生举例：产生多位位矢量所有可能的输入情况signal test_vector3: std_logic_vector(3 downto0) := "0000";

signal test_vector4: std_logic_vector(3 downto0) := "0000";

signal test_vector5:std_logic_vector(3 downto0);

signal test_vector6: std_logic_vector

(3 downto

0);

TB3:process

begin

wait for 10 ns;

test_vector3 <= test_vector3 + 1; end process;TB4:process

begin

wait for 10 ns;

test_vector4<= test_vector4 + 1; wait for 10 ns;

end process;

TB5:process

begin

test_vector5 <= "0000";

wait for 10 ns;

test_vector5 <= test_vector5 + 1; end process;TB6:process

begin

test_vector6 <= "0000";

wait for 10 ns;

test_vector6 <= test_vector6 + 1; wait for 10 ns;

end process;

For 循环语句产生所有可能的输入情况

double_loop: process

begin

test_ab<="00";

test_sel<="00";

for I in 0 to 3 loop

for J in 0 to 3 loop

wait for 10 ns;

test_ab<= test_ab+ 1;

end loop;

test_sel<= test_sel+ 1;

end loop;

end process;

?2位全加器的设计

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder_2 is

port(cin:in std_logic;

a,b:in std_logic_vector(1 downto0);

s:out std_logic_vector(1 downto0);

cout:out std_logic);

end adder_2;

architecture beh of adder_2 is

signal sint:std_logic_vector(2 downto0); signal aa,bb:std_logic_vector(2 downto0); begin

aa<='0' & a(1 downto0);

bb<='0' & b(1 downto0);

sint<=aa+bb+cin;

s(1 downto0)<=sint(1 downto0);

cout<=sint(2);

end beh;

?2位全加器的验证

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder_2_tb is

end adder_2_tb;

architecture tb of adder_2_tb is

COMPONENT adder_2

PORT(cin:in std_logic;

a,b:in std_logic_vector(1 downto0);

s:out std_logic_vector(1 downto0);

cout:out std_logic);

END COMPONENT;

signal a_t,b_t,s_t:std_logic_vector(1 downto0);

signal cin_t,cout_t:std_logic;

begin

DUT:adder_2 PORT MAP

(cin=>cin_t,a=>a_t,b=>b_t,s=>s_t, cout=>cout_t);库、程序包

的调用

空实体

被测试元件

的声明

局部信号声明

例化被测试元件

国家级电工电子实验教学中心2位全加器的仿真波形

TB:process

begin

a_t <="00";

b_t <="00";

cin_t<='0';

for K in 0 to 1 loop

for I in 0 to 3 loop

产生激励信号

for J in 0 to 3 loop

wait for 10 ns;

b_t<= b_t+ 1;

end loop;

a_t<= a_t+ 1;

end loop;

cin_t<= not cin_t;

end loop;

end process;

数字启航

国家级电工电子实验教学中心

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt6 is

port (clr,en,clk:in std_logic;

q:out std_logic_vector(2 downto0) ); end entity;

architecture rtl of cnt6 is

signal tmp:std_logic_vector(2 downto0); begin

process(clk)

begin

if(clk'event and clk='1') then

if(clr='0')then tmp<="000";

elsif(en='1') then

if(tmp="101")then tmp<="000";

else

tmp<=unsigned(tmp)+'1';

end if; end if; end if;

q<=tmp;

end process; end rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt6_tb is

end cnt6_tb;

architecture rtl of cnt6_tb is

component cnt6

port(

clr,en,clk:in std_logic;

q :out std_logic_vector(2 downto0));

end component;

signal clr:std_logic:='0';

signal en:std_logic:='0';

signal clk:std_logic:='0';

signal q :std_logic_vector(2 downto0);

constant clk_period:time :=10 ns;

begin

DUT:cnt6 port map(clk=>clk,en=>en,clr=>clr,q=>q);

?六进制计数器的设计与验证

库、程序包

的调用

空实体

被测试元件

的声明

局部信号声明

例化被测试元件

clk_gen:process begin

wait for clk_period/2;

clk<='1';

wait for clk_period/2;

clk<='0';

end process;

clr_gen:process

begin

clr<='0';

wait for 15 ns;

clr<='1';

wait;

end process;

en_gen:process

begin

en<='0';

wait for 25 ns;

en<='1';

wait;

end process;

end rtl;

①②③

产生激励信号

六进制计数器的仿真波形

谢谢！再见！

?使用DELAYED属性产生两相关性信号

……

signal period1,period2: std_logic;

……

period1 <= '1' after 30 ns when period1='0' else

'0' after 20 ns when period1='1' else

'0';

period2 <= period1'delayed(10 ns);

……

数字启航

国家级电工电子实验教学中心

?典型错误

signal test_vector: STD_LOGIC_VECTOR(2 downto0);

signal reset : STD_LOGIC;

gen1:process

begin

reset <= '1';

wait for 100 ns;

reset <= '0';

test_vector<= "000";

wait;

end process; gen2:process

begin

wait for 200 ns;

test_vector<= "001";

wait for 200 ns;

test_vector<= "011";

end process;

一个信号不能在两

个进程中进行赋值