Verilog作业

Verilog作业1、8位加法器源代码adder.vmodule adder8(ina,inb,cin,cout,sum);input[7:0]ina,inb;input cin;output[7:0]sum;output cout;assign{cout,sum}=ina+inb+cin;endmodule测试代码adder_tp.v`timescale1ns/1ns`include"adder.v"module adder_tp;reg[7:0]a,b;reg cin;wire[7:0]sum;wire cout;adder8adder(a,b,cin,cout,sum);always#5cin=~cin;initialbegina=0;b=0;cin=0;repeat(100)#10a={$random}%256;//a is a random number between0and255 endinitialbegin#10b={$random}%256;//b is a random number between0and255 endinitialbegin$monitor($time,,,"%d+%d+%b={%b+%d}",a,b,cin,cout,sum);#1000$finish;endendmodule2、8位计数器源代码count.vmodule count8(reset,clk,out);input reset;input clk;output[7:0]out;reg[7:0]out;always@(posedge clk)beginif(reset)out<=0;else out<=out+1;endendmodule测试代码count_tp.v`timescale1ns/1ns`include"count.v"module count_tp;reg clk,reset;wire[7:0]out;parameter DELY=100;count8counter(reset,clk,out);always#(DELY/2)clk=~clk;initialbeginreset=0;clk=0;#DELY reset=1;#DELY reset=0;#(DELY*200)$finish;endinitial$monitor($time,,,"clk=%d reset=%d out=%d",clk,reset,out); endmodule3、4位移位寄存器源代码shifter.v//4Bit shift Registermodule shifter(din,clk,rst,out);input din;input rst;input clk;output[3:0]out;reg[3:0]out;always@(posedge clk)beginif(rst)out<=4'b0;elsebeginout<=out<<1;out[0]<=din;endendendmodule测试代码shifter_tp.vtimescale1ns/1ns`include"shifter.v"module shifter_tp;reg din,clk,rst;wire[3:0]out;parameter DELY=10;shifter myshift(din,clk,rst,out); always#(DELY/2)clk=~clk; initialbeginclk=0;//initializationrst=0;din=0;#DELY rst=1;#(DELY*2)rst=0;//reset#DELY din=1;//input data#DELY din=0;#DELY din=1;#DELY din=1;#DELY$finish;//finish simulationendinitial$monitor($time,,,"clk=%d rst=%d din=%d out=%b",clk,rst,din,out); endmodule5、7人投票表决器源代码voter.vmodule voter(vote,result);input[6:0]vote;output result;reg result;reg[2:0]sum;integer i;always@(vote)beginsum=0;for(i=0;i<7;i=i+1)if(vote[i])sum=sum+1;if(sum[2])result=1;else result=0;endendmodule测试代码voter_tp.v`timescale1us/1us`include"voter.v"module voter_tp;parameter DELY=100;reg[6:0]vote;wire result;voter myvoter(vote,result);initialbeginvote=0;#DELY vote=7'b0111011;#DELY vote=7'b0101000;#DELY vote=7'b1011111;#DELY$finish;endinitial$monitor($time,,,"vote=%d result is%b",vote,result); endmodule6、32位整数循环1)for语句实现源代码int_loop_for.v`timescale1us/1usmodule int_loop_for(num);input[31:0]num;reg[31:0]temp;reg lsb;integer i;parameter DELY=10;always@(num)begintemp=num;for(i=0;i<32;i=i+1)begin#DELY$display("num=%b i=%d",temp,i);lsb=temp[0];temp=temp>>1;temp[31]=lsb;endendendmodule测试代码Int_loop_tp.v`timescale1us/1us`include"int_loop_for.v"module int_loop_tp;reg[31:0]num;parameter DELY=10;int_loop_for my_int_loop(num);initialbeginnum=32'ha5363a2d;//32-bit integer 10100101001101100011101000101101#(DELY*33)$finish;endendmodule2)repeat语句实现源代码int_loop_repeat.v`timescale1us/1usmodule int_loop_repeat(num);input[31:0]num;reg[31:0]temp;reg lsb;parameter DELY=10;always@(num)begintemp=num;repeat(32)begin#DELY$display("num=%b",temp);lsb=temp[0];temp=temp>>1;temp[31]=lsb;endendendmodule测试代码int_loop_tp.v`timescale1us/1us`include"int_loop_repeat.v"module int_loop_tp;reg[31:0]num;parameter DELY=10;int_loop_repeat my_int_loop(num);initialbeginnum=32'ha5363a2d;//32-bit integer 10100101001101100011101000101101#(DELY*33)$finish;endendmodule3)while语句实现源代码int_loop_while.v`timescale1us/1usmodule int_loop_while(num);input[31:0]num;reg[31:0]temp;reg lsb;integer i;parameter DELY=10;always@(num)begintemp=num;i=32;while(i)begin#DELY$display("num=%b",temp);lsb=temp[0];temp=temp>>1;temp[31]=lsb;i=i-1;endendendmodule测试代码int_loop_tp.v`timescale1us/1us`include"int_loop_while.v"module int_loop_tp;reg[31:0]num;parameter DELY=10;int_loop_while my_int_loop(num);initialbeginnum=32'ha5363a2d;//32-bit integer 10100101001101100011101000101101#(DELY*33)$finish;endendmodule7、空调机状态图源代码air_condition.vmodule air_condition(clk,rst,temp_high,temp_low,cool,heat); input clk,rst,temp_high,temp_low;output cool,heat;reg cool,heat;parameter right=3'h1;//one-hot codeparameter too_hot=3'h2;parameter too_cold=3'h4;reg[2:0]state;always@(posedge clk)beginif(!rst)beginstate<=right;heat<=0;cool<=0;endcase(state)right:beginif(temp_high&&!temp_low)state<=too_hot;else if(!temp_high&&temp_low)state<=too_cold;else state<=right;endtoo_hot:beginif(temp_high&&!temp_low)state<=too_hot;else if(!temp_high&&temp_low)state<=too_cold;else state<=right;endtoo_cold:beginif(temp_high&&!temp_low)state<=too_hot;else if(!temp_high&&temp_low)state<=too_cold;else state<=right;enddefault:state<=right;endcaseendalways@(state)case(state)too_hot:begin cool<=1;heat<=0;endtoo_cold:begin cool<=0;heat<=1;endright:begin cool<=0;heat<=0;enddefault:begin cool<=0;heat<=0;endendcaseEndmodule测试代码air_conditon_tp.v//Herison`timescale1ns/1ns`include"air_condition.v"module air_condition_tp;reg rst,clk,temp_high,temp_low;wire heat,cool;parameter DELY=100;always#(DELY/2)clk=~clk;air_condition mytest(clk,rst,temp_high,temp_low,cool,heat); initialbeginrst=1;//initializationclk=0;temp_high=0;temp_low=0;#DELY rst=0;#DELY rst=1;//reset#DELY{temp_high,temp_low}=01;#DELY{temp_high,temp_low}=10;#DELY{temp_high,temp_low}=10;#DELY{temp_high,temp_low}=00;#DELY{temp_high,temp_low}=01;#DELY{temp_high,temp_low}=11;#DELY{temp_high,temp_low}=01;#DELY{temp_high,temp_low}=10;endinitialbegin$monitor($time,,,"temp_high=%d temp_low=%d heat=%d cool=%d",temp_high,temp_low,heat,cool);#(DELY*10)$finish;endendmodule8、交通灯状态图源代码traffic_light.v/*signal descriptionclk:system clockreset:reset portsensor:signal of sensorLAMPH:the lights signal of HighWay LAMPH[2]~LAMPH[0]:GREEN_H,RED_H,YELLOW_HLAMPC:the lights signal of CountyWay LAMPC[2]~LAMPC[0]:GREEN_C,RED_C,YELLOW_C*/module traffic_light(clk,reset,sensor,LAMPH,LAMPC);input clk,reset,sensor;output[2:0]LAMPH;output[2:0]LAMPC;reg[2:0]LAMPH;reg[2:0]LAMPC;reg[3:0]state;//record the stateparameter t_green_h=8'd36,//36st_red_h=8'd16,//16st_yellow=8'd4;//4sparameter s0=0,//h_Green c_Reds1=1,//h_Yellow c_reds2=2,//h_Red c_greens3=3;//h_Red c_yellow//the contol process of lightsalways@(posedge clk)beginif(!reset)//resetbeginLAMPH=3'b100;//Green lightLAMPC=3'b010;//Red lightstate=s0;endcase(state)s0:beginLAMPH=3'b100;//Green lightLAMPC=3'b010;//Red lightif(sensor)begin light(t_green_h);state=s1;endends1:beginLAMPH=3'b001;//Yellow lightLAMPC=3'b010;//Red lightstate=s2;light(t_yellow);ends2:beginLAMPH=3'b010;//Red lightLAMPC=3'b100;//Green lightstate=s3;light(t_red_h);ends3:beginLAMPH=3'b010;//Red lightLAMPC=3'b001;//Yellow lightstate=s0;light(t_yellow);endendcaseend//delay time tasktask light;input[7:0]t_color;beginrepeat(t_color)@(posedge clk);endendtaskEndmodule测试代码traffic_light_tp.v`timescale1us/1us`include"traffic_light.v"module traffic_light_tp;reg clk,reset,sensor;wire[2:0]LAMPH,LAMPC;parameter DELY=1000;//1s//generate the clk signalalways#(DELY/2)clk=~clk;traffic_light mylight(clk,reset,sensor,LAMPH,LAMPC);initialbeginclk=0;reset=1;sensor=0;#DELY reset=0;#(2*DELY)reset=1;#DELY sensor=1;#(DELY*100)sensor=0;#DELY$finish;endinitial$monitor($time,,,"clk=%d reset=%d sensor=%d LAMPH=%b LAMPC=%b", clk,reset,sensor,LAMPH,LAMPC);endmoduleBy Herison。