数字调制解调技术大学毕业论文英文文献翻译及原文

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外文翻译---6 数字数据传输：接口和调制解调器

英文资料及中文翻译6 TRANSMISSIONS OF DIGITAL DATA:INTERFACES AND MODEMS(From Introduction to Data Communications and Net Working,Behrouz Forouzan)Once we have encoder our information into a format that can be transmitted, the next step is to investigate the transmission process itself. Information-processing equipment such as PCs generate encoded signals but ordinarily require assistance to transmit those signals over a communication link. For example, a PC generates a digital signal but needs an additional device to modulate a carrier frequency before it is sent over a telephone line. How do we relay encoded data from the generating device to the next device in the process? The answer is a bundle of wires, a sort of mini communication link, called an interface.Because an interface links two devices not necessarily made by the same manufacturer, its characteristics must be defined and standards must be established. Characteristics of an interface include its mechanical specifications (how many wires are used to transport the signal); its electrical specifications (the frequency, amplitude, and phase of the expected signal); and its functional specifications (if multiple wires are used, what does each one do?). These characteristics are all described by several popular standards and are incorporated in the physical layer of the OSI model.6.1 DIGITAL DATA TRANSMISSIONOf primary concern when considering the transmission of data from one device to another is the wiring. And of primary concern when considering the wiring is the data stream. Do we send one bit at a time, or do we group bits into larger groups and, if so, how? The transmission of binary data across a link can be accomplished either in parallel mode or serial mode. In parallel mode, multiple bits are sent with each clock pulse. In serial mode, one bit is sent with each clock pulse. While there is only one way to send parallel data, there are two subclasses of serial transmission: synchronous and asynchronous (see Figure 6-1).Parallel TransmissionBinary data, consisting of 1s and 0s, may be organized into groups of n bits each. Computers produce and consume data in groups of bits much as we conceive of and use spoken language in the form of words rather than letters. By grouping, we cansend data n bits at a time instead of one. This is called parallel transmission.The mechanism for parallel transmissionis a conceptually simple one: use n wires to send n bits at one time. That way each bit has its own wire, and all n bits of one group can be transmitted with each clock pulse from one device to another. Figure 6-2 shows how parallel transmission works for n=8.Typically the eight wires are bundled in a cable with a connector at each end.Figure 6-2 Parallel transmissionThe advantage of parallel transmission is speed. All else being equal, parallel transmission can increase the transfer speed by a factor of n over serial transmission. But there is a significant disadvantage:cost. Parallel transmission requires n communication lines (wires in the example) just to transmit the data stream. Because this is expensive, parallel transmission is usually limited to short distances, up to a maximum of say 25 feet.Serial TransmissionIn serial transmission one bit follows another, so we need only one communication channel rather than n to transmit data between two communicating devices .The advantage of serial over parallel transmission is that with only one communication channel, serial transmission reduces the cost of transmission over parallel by roughly a factor of n.Since communication within devices is parallel, conversion devices are required at the interface between the sender and the line (parallel-to-parallel).Serial transmission occurs in one of two ways: asynchronous or synchronous. Asynchronous TransmissionAsynchronous transmission is so named because the timing of a signal is unimportant. Instead, information is received and translated by agreed-upon patterns. As long as those patterns are followed, the receiving device can retrieve the information without regard to the rhythm in which it is sent. Patterns are based on grouping the bit stream into bytes. Each group, usually eight bits, is sent along the link as a unit. The sending system handles each group independently, relaying it to the link whenever ready, without regard to a timer.Without a synchronizing pulse, the receiver cannot use timing to predict when the next group will arrive. To alert the receiver to the arrival of a new group, therefore, an extra bit is added to the beginning of each byte. This bit, usually a 0, is called the start bit. To let the receiver know that the byte is finished, one or more additional bits are appended to the end of the byte. These bits, usually 1s, are called stop bits. By this method, each byte is increased in size to at least 10 bits, of which 8 are information and 2 or more are signals to the receiver. In addition, the transmission of each byte may then be followed by a gap of varying duration. This gap can be represented either by an idle channel or by a stream of additional stop bits.In asynchronous transmission we send one start bit (0) at the beginning and one or more stop bits (1s) at the end of each byte. There may be a gap between each byte.The start and stop bits and the gap alert the receiver to the beginning and end of each byte and allow it to synchronize with the data stream. This mechanism is called asynchronous because, at the byte level, sender and receiver do not have to be synchronized. But within each byte, the receiver must still be synchronized with the incoming bit stream. This is, some synchronization is required, but only for the duration of a single byte. The receiving device resynchronizes at the onset of each new byte. When the receiver detects a start bit, it sets a timer and begins counting bits as they come in. after n bits the receiver looks for a stop bit. As soon as it detects the stop bit, it ignores any received pulses until it detects the next start bit.Asynchronou s here means “asynchronous at the byte level,” but the bits are still synchronized; their durations are the same.The addition of stop and start bits and the insertion of gaps into the bit stream make asynchronous transmission slower than forms of transmission that can operate without the addition of control information. But it is cheap and effective, two advantages that make it an attractive choice for situations like low-speed communication. For example, the connection of a terminal to a computer is a natural application for asynchronous transmission. A user types only one character at a time, types extremely slowly in data processing terms, and leaves unpredictable gaps of time between each character.Synchronous TransmissionIn synchronous transmission, the bit stream is combined into longer “frames,” which may contain multiple bytes. Each byte, however, is introduced onto the transmission link without a gap between it and the next one. It is left to the receiver to separate the bit stream into bytes for decoding purposes. In other words, data are transmitted as an unbroken string of 1s and 0s, and the receiver separates that string into the bytes, or characters, it needs to reconstruct the information.In synchronous transmission we send bits one after another without start/stop bits or gaps. It is the responsibility of the receiver to group the bits.Without gaps and start/stop bits, there is no built-in mechanism to help the receiving device adjust its bit synchronization in midstream. Timing becomes very important, therefore, because the accuracy of the received information is completely dependent on the ability of the receiving device to keep an accurate count of the bits as they come in.The advantage of synchronous transmission is speed. With no extra bits or gaps to introduce at the sending end and remove at the receiving end and, by extension, with fewer bits to move across the link, synchronous transmission is faster than asynchronous transmission is faster than asynchronous transmission. For this reason, it is more useful for high-speed applications like the transmission of data from one computer to another. Byte synchronization is accomplished in the data link layer.6.2 DTE-DCE INTERFACAt this point we must clarify two terms important to computer networking: data terminal equipment (DTE). There are usually four basic functional units involved in the communication of data: a DTE and DCE on one end and a DCE and DTE on theother end. The DTE generates the data and passes them, along with any necessary control characters, to a DCE. The DCE does the job of converting the signal to a format appropriate to the transmission medium and introducing it onto the network link. When the signal arrives at the receiving end, this process is reversed.Data Terminal Equipment (DTE)Data terminal equipment (DTE) includes any unit that functions either as a source of or as a destination for binary digital data. At the physical layer, if can be a terminal, microcomputer, computer, printer, fax machine, or any other device that generates or consumes digital data. DTEs do not often communicate directly with one another, they generate and consume information but need an intermediary to be able to communicate. Think of a DTE as operating the way your brain does when you talk. Let’s say you have an idea that you want to communicate to a friend. Your brain creates the idea but cannot transmit that idea to your friend’s brain by itself. Unfortunately or fortunately, we are not a species of mind readers. Instead, your brain passes the idea to your vocal chords and mouth, which convert it to sound waves that can travel through the air or over a telephone line to your friend’s ear and from there to his or her brain, where it is converted back into information. In this model, your brain and your friend’s brain are DTEs. Your vocal chords and mouth are your DCE. His or her ear is also a DCE. The air or telephone wire is your transmission medium.A DTE is any device that is a source of or destination for binary digital data. Data Circuit-Terminating Equipment (DCE)Data circuit-terminating equipment (DCE) includes any functional unit that transmits or receives data in the form of an analog or digital signal through a network. At the physical layer, a DCE takes data generated by a DTE, converts them to an appropriate signal, and then introduces the signal onto the telecommunication link. Commonly used DCEs at this layer include modems . In any network, a DTE generates digital data and passes it to a DCE; the DCE converts the data to a form acceptable to the transmission medium and sends the converted signal to another DCE on the network. The second DCE takes the signal off the line, converts it to a form usable by its DTE, and delivers it. To make this communication possible, both the sending and receiving DCEs must use the same encoding method, much the way that if you want to communicate to someone who understands only Japanese, you must speak Japanese. The two DTEs do not need to be coordinated with each other, but each of them must be coordinated with its own DCE and the DCEs must becoordinated so that data translation occurs without loss of integrity.A DCE is any device that transmits or receives data in the form of an analog or digital signal through a network.6 数字数据传输：接口和调制解调器（选自«数据通信与网络»， Behrouz Forouzan著）我们将信息编码成可以传输的格式，下一步就是探讨传输过程了。

4翻译

毕业设计（论文）外文参考资料及译文译文题目： CIC MegaCore Function 学生姓名：高佳学号： 1021129024 专业：通信工程所在学院：龙蟠学院指导教师：姜志鹏职称：讲师2013年11月06日CIC MegaCore Function----From DescriptionThis document describes the Altera CIC MegaCore function. The Altera CIC MegaCore function implements a cascaded integrator-comb filter with data ports that are compatible with the Avalon Streaming interface. CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation, and for constructing narrow-band signals from processed baseband signals using interpolation.CIC filters use only adders and registers, and require no multipliers to handle large rate changes. Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample rate conversion designs such as digital down converters (DDC) and digital up converters (DUC).The Altera CIC MegaCore function supports the following features:■Support for interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurable number of stages (1 to 12), and two differential delay options (1 or 2).■Single clock domain with selectable number of interfaces and a maximum of 1,024 channels.■Selectable data storage options with an option to use pipelined integrators.■Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width).■Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and Hogenauer pruning support.■Optimization for speed by specifying the number of pipeline stages used by each integrator.■Compensation filter coefficients generation.■Easy-to-use MegaWizard interface for parameterization and hardware generation.■IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.■DSP Builder ready.Cascaded Integrator Comb (CIC) filters are widely used in modern communication systems. As the signal processing in all aspects of requirements are constantly improve, in digital technology, the design of the filter appears increasingly important.Those who have signal processing ability of device can be referred to as a filter.In the modern telecommunications equipment and all kinds of control system, filter is widely used.Of all the electronic devices, using the most, the most widely used, technology is the most complex filter.Filter quality directly decides the product quality, good performance of filter can make the system more stable, so the filter of the countries all over the research and production has always been highly valued.With the wide application of digital technology, field programmable gate array (FPGA) has been the rapid development, integration and speed is growing.FPGA has high integration and reliability of the gate array (FPGA), and programmable resistance, maximum limit reduces the design cost, shorten the development cycle.Using CIC filters provides a silicon efficient architecture for performing sample rate conversion. This is achieved by extracting baseband signals from narrow-band sources using decimation, and constructing narrow-band signals from processed baseband signals using interpolation. The key advantage of CIC filters is that they use only adders and registers,and do not require multipliers to implement in hardware for handling large rate changes.A CIC filter (also known as a Hogenauer filter) can be used to perform either decimation or interpolation. A decimation CIC filter comprises a cascade of integrators (called the integrator section), followed by a down sampling block (decimator) and a cascade of differentiators (called the differentiator or comb section). Similarly an interpolation CIC filter comprises a cascade of differentiators, followed by an up sampling block (interpolator) and a cascade of integrators .In a CIC filter, both the integrator and comb sections have the same number of integrators and differentiators. Each pairing of integrator and differentiator is called a stage. The number of stages ( N ) has a direct effect on the frequency response of a CIC filter. The response of the filter is determined by configuring the number of stages N , therate change factor R and the number of delays in the differentiators (called the differential delay) M . In practice, the differential delay is set to 1 or 2.The MegaWizard interface only allows you to select legal combinations of parameters, and warns you of any invalid configurations .For high rate change factors, the maximum required data width for no data loss is large for many practical cases. To reduce the output data width to the input level, quantization is normally applied at the end of the output stage. In this case, the following rounding or saturation options are available:■Truncation : The LSBs are dropped. (This is equivalent to rounding to minus infinity.)■Convergent rounding . Also known as unbiased rounding . Rounds to the nearest even number . If the most significant deleted bit is one, and either the least significant of the remaining bits or at least one of the other deleted bits is one, then one is added to the remaining bits.■Round up: Also known as rounding to plus infinity. Adds the MSB of the discarded bits for positive and negative numbers via the carry in.■Saturation: Puts a limit value (upper limit in the case of overflow, or lower limit in the case of negative overflow) at the output when the input exceeds the allowed range. The upper limit is+2n-1 and lower limit is –2n.These rounding options can only be applied to the output st age of the filter. The data widths at the intermediate stages are not changed. The next section describes cases where the data width at the intermediate stages can be changed.Hogenauer pruning [Reference ] is a technique that utilizes truncation or rounding in intermediate stages with the retained numb er of bits decreasing monotonically from stage to stage, while the total error introduced is still no greater than the quantization error introduced by rounding the full precision output. This technique helps to reduce the number of logic cells used by the filter and gives better performance.The existing algorithms for computing the Hogenauer bit width growth for large N and R values are computationally expensive.For more information about these algorithms, refer to U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edition, Spinger, 2004.The CIC MegaCore function has pre-calculated Hogenauer pruning bit widths stored within the MegaCore function. There is no need to wait for Hogenauer pruning bit widths to be calculated if Hogenauer pruning is enabled for a decimation filter. Hogenauer pruning is only available to decimation filters when the selected output data width is smaller than the full output resolution data width.There are often many channels of data in a digital signal processing (DSP) system that require filtering by CIC filters with the same configuration. These can be combined into one filter, which shares the adders that exist in each stage and reduces the overall resource utilization. This combined filter uses fewer resources than using many individual CIC filters. For example, a two-channel parallel filter requires two clock cycles to calculate two outputs. The resulting hardware would need to run at twice the data rate of an individual filter. This is especially useful for higher rate changes where adders grow particularly large.To minimize the number of logic elements , a multiple input single output (MISO) architecture can be used for decimation filters, and a single input multiple output (SIMO) architecture for interpolation filters as described in the following sections.In many practical designs, channel signals come from different input interfaces. On each input interface, the same parameters including rate change factors are applied to the channel data that the CIC filter is going to process. The CIC MegaCore function allows the flexibility to exploit time sharing of the low rate differentiator sections. This is achieved by providing multiple input interfaces and processing chains for the high rate portions, then combining all of the processing associated with the lower rate portions into a single processing chain. This strategy can lead to full utilization of the resources and represents the most efficient hardware implementation. These architectures are known as multiple input single output (MISO) decimation filters.Single input multiple output (SIMO) is a feature associated with interpolation CIC filters. In this architecture, all the channel signals presented for filtering come from a single input interface.Like the MISO case, it is possible to share the low sampling rate differentiator section amongst more channels than the higher sampling frequency integrator sections. Therefore, this architecture features a single instance of the differentiator section, and multiple parallel instances of the integrator sections.After processing by the differentiator section, the channel signals are split into multiple parallel sections for processing in a high sampling frequency by the integrator sections. The sampling frequency of the input data is such that it is only possible to time multiplex two channels per bus, therefore the CIC filter must be configured with two input interfaces. Because two interfaces are required, the rate change factor must also be at least two to exploit this architecture. Up to 1,024 channels can be supported by using multiple input interfaces in this way.Single input multiple output (SIMO) is a feature associated with interpolation CIC filters. In this architecture, all the channel signals presented for filtering come from a single input interface. Like the MISO case, it is possible to share the low sampling rate differentiator section amongst more channels than the higher sampling frequency integrator sections.Therefore, this architecture features a single instance of the differentiator section, and multiple parallel instances of the integrator sections.After processing by the differentiator section, the channel signals are split into multiple parallel sections for processing in a high sampling frequency by the integrator sections.The required sampling frequency of the output data is such that it is only possible to time multiplex two channels per bus. Therefore the CIC filter must be configured with four output interfaces. Because four interfaces are required, the rate change factor must also be at least four to exploit this architecture, but in this example a rate change of eight is illustrated.SIMO architecture is applied when an interpolation filter type is chosen and the number of interfaces selected in the MegaWizard interface is greater than one.The total number of input channels must be a multiple of the number of interfaces. To satisfy this requirement, you may need to either insert dummy channels or use more than one CIC MegaCore function. Data is transferred as packets using AvalonStreaming interfaces. CIC filters have a low-pass filter characteristic. There are only three parameters (the rate change factor R , the number of stages N , and the differential delay M ) that can be modified to alter the passband characteristics and aliasing/imaging rejection. However, due to their drooping passband gains and wide transition regions, CIC filters alone cannot provide the flat passband and narrow transition region filter performance that is typically required in decimation or interpolation filtering applications.This problem can be alleviated by connecting the decimation or interpolation CIC filter to a compensation FIR filter which narrows the output bandwidth and flattens the passband gain.You can use a frequency sampling method to determine the coefficients of a FIR filter that equalizes the undesirable passband droop of the CIC and construct an ideal frequency response.The ideal frequency response is determined by sampling the normalized magnitude response of the CIC filter before inverting the response.Generally, it is only necessary to equalize the response in the passband, but you can sample further than the passband to fine tune the cascaded response of the filter chain.The Avalon-ST interface can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels.The Avalon-ST interface inherently synchronizes multi-channel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.CIC MegaCore函数----摘自描述这篇文章对Altera公司的CIC 宏函数作了说明。

英文参考文献原文复印件及译文

英文参考文献原文复印件及译文专业：自动化08级1班姓名：学号：080412122指导教师：赵奇完成日期年月SCM theory and the minimum MCU AdventWith the development of automation technology and microelectronics technology, as well as the fieldbus technology becomes more mature, numerical control technology in the production process is applied more and more widely, on the site of the signal collection, transmission and data processing is put forward higher requirements.Intelligent transmitter is composed of sensor and microprocessor ( computer ) and the phase structure. It makes full use of the microprocessor computing and storage capacity, the sensor data processing, including the measurement signal processing (such as filtering, amplification, A/D conversion ), data display, automatic calibration and automatic compensation.The microprocessor is the core of intelligent transmitter. It can not only carry on the data computation, storage and data processing, but also through a feedback loop to adjust to the sensor, data acquisition to achieve the best. The microprocessor has a variety of software and hardware function, so it can complete the traditional transducer difficult task. So intelligent transmitter reduces sensor manufacturing difficulty, and largely improves the performance of the sensor lord. In addition, intelligent transmitter also has the following characteristics:1 with automatic compensation ability, through the software on the sensor's nonlinear, temperature drift, drift and automatic compensation.Self diagnosis, after power for the sensor to check all parts of self, the sensor is normal, and make judgments.Data processing is convenient and accurate, according to internal procedures, automatic data processing, such as statistical processing, removal of abnormal value.2 with two-way communication function. The microprocessor can receive and process the sensor data, can also be information feedback to the sensor, thus the process of measurement adjustment and control.The information can be stored and can be stored in memory, the characteristics of sensor data, configuration information and compensation characteristics.3 has a digital interface output function, the output of the digital signal conveniently and computer or field bus connectionThe difference between the transmitter and sensorIn editing software in the process of joining the watchdog circuit. Theapplication of watchdog circuit, so that the chip can be in no condition to realize continuous work. But there are still some problems:1the watchdog circuit at run-time, meaning, system error. 2circulation process error too many times, the watchdog can not effectively resolved3 in measurement and control system in the period of time in one-chip, computer peripheral devices such as a large amount of time, is not running, waiting for orders. In these cases, the hardware watchdog is to use a timer, to monitor the main program operation, that is to say in the main program of the operatio n process, we will in time to time before the timer is reset if the dead cycle, or PC pointers can't come back. Then time to time will make chip reset.SCM is the main computer components are integrated on a single chip microcomputer. It is a collection of counting and many interfaces in one microcontroller, is widely used in intelligent products and industrial automation, and51 SCM SCM is the most typical and the most representative one.Signal generator in the teaching, testing, monitoring and other fields have a very wide range of applications, but also with the modern electronic communications technology development, often requires high precision and adjustable frequency signal generator.The design of direct use A T89C51 SCM as an important component of the wave generator, coupled with clever software design and simple external circuit, a frequency, adjustable amplitude sine wave, triangle wave, sawtooth wave and Fang Bo and other signals. Signal frequency, amplitude, through the keyboard input directly, by the LED display. And various types of existing waveform generator comparison, ATMEL AT89C51 is a highly effective micro controller, which produces a small number of signal interference, output stability, high reliability, especially the simple and convenient operation, low cost, very suitable for teaching and experimental physics laboratory use.Microchip security, SCM and technology development department vice president Steve Drehobl said:" Microchip continuously expand 8microcontroller applications, creating a new generation of ultra compact flash memory device, using PIC MCU into non-traditional applications. These6pin device with high cost-effectiveness replaces the discrete logic or mechanical function, reduces the number of components and board space, also give engineers more design flexibility.The United States of America microchip technology company ( Microchip Technology ) recently launched the world 's smallest6 pin package chip ( MCU ), thePIC microcontroller architecture powerful functions into ultra small volume of the SOT-23 package, the single chip microcomputer application domain expands further, in some space is extremely limited and cost requirements for lower application field is expected to have a brilliant future.Traditional single chip market, MCU products can be used on a number of different fields, such as home appliances to the automotive, communications, office automation and industrial control. According to market analysis firm IC Insight global MCU market data,2003total sales of $10400000000, at $12200000000 in2004. Although each main MCU suppliers have already introduced 16bit,32 bit single chip, but the market is still used in most8 bit single chip microcomputer products, accounted for the overall market of about 40%. Therefore8 bits single chip computer still has large application market, mainly in such products in the ease of use, cost advantages, while performance can meet most of the needs of applications. This Steve Drehobl said:"8 bit single chip has the advantages of easy operation and use characteristics, design staff will soon be able to master the principles and methods of using8 bit single chip microcomputer; design cycle is short, design tool is more than 16,32design tool much cheaper; third, in reality, we are more according to what kind of application can produce what kind of performance to determine how many bits MCU used. If in those using8 bit single chip can meet the needs of the application, you must use 16 bit and 32 bit, from the function, more abundant, but the cost rise. Again, the current problems should not be ignored. If the excessive use of electric current, battery power consumption is relatively large单片机理论与最小MCU问世随着自动化技术的发展和微电子技术的进步，以及现场总线技术的日益成熟，数控技术在生产过程中的应用越来越广泛，对现场信号的采集、传输和数据处理提出更高的要求。

数据通信毕业论文外文文献英文翻译

郑州轻工业学院本科毕业设计（论文）——英文翻译题目差错控制编码解决加性噪声的仿真学生姓名专业班级通信工程05-2 学号 12院（系）计算机与通信工程学院指导教师完成时间 2009年4月26日英文原文:Data communicationsGildas Avoine and Philippe OechslinEPFL, Lausanne, Switzerlandfgildas.avoine, philippe.oechsling@ep.chAbstractData communications are communications and computer technology resulting from the combination of a new means of communication. To transfer information between the two places must have transmission channel, according to the different transmission media, there is wired data communications and wireless data communications division. But they are through the transmission channel data link terminals and computers, different locations of implementation of the data terminal software and hardware and the sharing of information resources.1 The development of data communicationsThe first phase: the main language, through the human, horsepower, war and other means of transmission of original information.Phase II: Letter Post. (An increase means the dissemination of information)The third stage: printing. (Expand the scope of information dissemination)Phase IV: telegraph, telephone, radio. (Electric to enter the time)Fifth stage: the information age, with the exception of language information, there are data, images, text and so on.1.1 The history of modern data communicationsCommunication as a Telecommunications are from the 19th century, the beginning Year 30. Faraday discovered electromagnetic induction in 1831. Morse invented telegraph in 1837. Maxwell's electromagnetic theory in 1833. Bell invented the telephone in 1876. Marconi invented radio in 1895. Telecom has opened up in the new era. Tube invented in 1906 in order to simulate the development of communications.Sampling theorem of Nyquist criteria In 1928. Shannong theorem in 1948. The invention of the 20th century, thesemiconductor 50, thereby the development of digital communications. During the 20th century, the invention of integrated circuits 60. Made during the 20th century, 40 the concept of geostationary satellites, but can not be achieved. During the 20th century, space technology 50. Implementation in 1963 first synchronized satellite communications. The invention of the 20th century, 60 laser, intended to be used for communications, was not successful. 70 The invention of the 20th century, optical fiber, optical fiber communications can be developed.1.2 Key figuresBell (1847-1922), English, job in London in 1868. In 1871 to work in Boston. In 1873, he was appointed professor at Boston University. In 1875, invented many Telegram Rd. In 1876, invented the telephone. Lot of patents have been life. Yes, a deaf wife.Marconi (1874-1937), Italian people, in 1894, the pilot at his father's estate. 1896, to London. In 1897, the company set up the radio reported. In 1899, the first time the British and French wireless communications. 1916, implementation of short-wave radio communications. 1929, set up a global wireless communications network. Kim won the Nobel Prize. Took part in the Fascist Party.1.3 Classification of Communication SystemsAccording to type of information: Telephone communication system, Cable television system ,Data communication systems.Modulation by sub: Baseband transmission,Modulation transfer.Characteristics of transmission signals in accordance with sub: Analog Communication System ,Digital communication system.Transmission means of communication system: Cable Communications,Twisted pair, coaxial cable and so on.And long-distance telephone communication. Modulation: SSB / FDM. Based on the PCM time division multiple coaxial digital base-band transmission technology. Will gradually replace the coaxial fiber.Microwave relay communications:Comparison of coaxial and easy to set up, low investment, short-cycle. Analog phone microwave communications mainly SSB / FM /FDM modulation, communication capacity of 6,000 road / Channel. Digital microwave using BPSK, QPSK and QAM modulation techniques. The use of 64QAM, 256QAM such as multi-level modulation technique enhance the capacity of microwave communications can be transmitted at 40M Channel 1920 ~ 7680 Telephone Rd PCM figure.Optical Fiber Communication: Optical fiber communication is the use of lasers in optical fiber transmission characteristics of long-distance with a large communication capacity, communication, long distance and strong anti-interference characteristics. Currently used for local, long distance, trunk transmission, and progressive development of fiber-optic communications network users. At present, based on the long-wave lasers and single-mode optical fiber, each fiber road approach more than 10,000 calls, optical fiber communication itself is very strong force. Over the past decades, optical fiber communication technology develops very quickly, and there is a variety of applications, access devices, photoelectric conversion equipment, transmission equipment, switching equipment, network equipment and so on. Fiber-optic communications equipment has photoelectric conversion module and digital signal processing unit is composed of two parts.Satellite communications: Distance communications, transmission capacity, coverage, and not subject to geographical constraints and high reliability. At present, the use of sophisticated techniques Analog modulation, frequency division multiplexing and frequency division multiple access. Digital satellite communication using digital modulation, time division multiple road in time division multiple access.Mobile Communications: GSM, CDMA. Number of key technologies for mobile communications: modulation techniques, error correction coding and digital voice encoding. Data Communication Systems.1.4 Five basic types of data communication system:（1）Off-line data transmission is simply the use of a telephone or similar link to transmit data without involving a computer system.The equipment used at both ends of such a link is not part of a computer, or at least does not immediately make the data available for computer process, that is, the data when sent and / or received are 'off-line'.This type of data communication is relatively cheap and simple.（2）Remote batch is the term used for the way in which data communication technology is used geographically to separate the input and / or output of data from the computer on which they are processed in batch mode.（3）On-line data collection is the method of using communications technology to provide input data to a computer as such input arises-the data are then stored in the computer (say on a magnetic disk) and processed either at predetermined intervals or as required.（4）Enquiry-response systems provide, as the term suggests, the facility for a user to extract information from a computer.The enquiry facility is passive, that is, does not modify the information stored.The interrogation may be simple, for example, 'RETRIEVE THE RECORD FOR EMPLOYEE NUMBER 1234 'or complex.Such systems may use terminals producing hard copy and / or visual displays.（5）Real-time systems are those in which information is made available to and processed by a computer system in a dynamic manner so that either the computer may cause action to be taken to influence events as they occur (for example as in a process control application) or human operators may be influenced by the accurate and up-to-date information stored in the computer, for example as in reservation systems.2 Signal spectrum with bandwidthElectromagnetic data signals are encoded, the signal to be included in the data transmission. Signal in time for the general argument to show the message (or data) as a parameter (amplitude, frequency or phase) as the dependent variable. Signal of their value since the time variables are or not continuous, can be divided into continuous signals and discrete signals; according to whether the values of the dependent variable continuous, can be divided into analog signals and digital Signal.Signals with time-domain and frequency domain performance of the two most basic forms and features. Time-domain signal over time to reflect changing circumstances. Frequency domain characteristics of signals not only contain the same information domain, and the spectrum of signal analysis, can also be a clear understanding of the distribution ofthe signal spectrum and share the bandwidth. In order to receive the signal transmission and receiving equipment on the request channel, Only know the time-domain characteristics of the signal is not enough, it is also necessary to know the distribution of the signal spectrum. Time-domain characteristics of signals to show the letter .It’s changes over time. Because most of the signal energy is concentrated in a relatively narrow band, so most of our energy focused on the signal that Paragraph referred to as the effective band Bandwidth, or bandwidth. Have any signal bandwidth. In general, the greater the bandwidth of the signal using this signal to send data Rate on the higher bandwidth requirements of transmission medium greater. We will introduce the following simple common signal and bandwidth of the spectrum.More or less the voice signal spectrum at 20 Hz ~ 2000 kHz range (below 20 Hz infrasound signals for higher than 2000 KHz. For the ultrasonic signal), but with a much narrower bandwidth of the voice can produce an acceptable return, and the standard voice-frequency signal gnal 0 ~ 4 MHz, so the bandwidth of 4 MHz.As a special example of the monostable pulse infinite bandwidth. As for the binary signal, the bandwidth depends on the generalThe exact shape of the signal waveform, as well as the order of 0,1. The greater the bandwidth of the signal, it more faithfully express the number of sequences.3 The cut-off frequency channel with bandwidthAccording to Fourier series we know that if a signal for all frequency components can be completely the same through the transmission channel to the receiving end, then at the receiving frequency components of these formed by stacking up the signal and send the signal side are exactly the same, That is fully recovered from the receiving end of the send-side signals. But on the real world, there is no channel to no wear and tear through all the Frequency components. If all the Fourier components are equivalent attenuation, then the signal reception while Receive termination at an amplitude up Attenuation, but the distortion did not happen. However, all the transmission channel and equipment for different frequency components of the degree of attenuation is differentSome frequency components almost no attenuation, and attenuation of some frequency components by anumber, that is to say, channel also has a certain amount of vibrationIncrease the frequency characteristics, resulting in output signal distortion. Usually are frequency of 0 Hz to fc-wide channel at Chuan harmonic lost during the attenuation does not occur (or are a very small attenuation constant), whereas in the fc frequency harmonics at all above the transmission cross Decay process a lot, we put the signal in the transmission channel of the amplitude attenuation of a component to the original 0.707(that is, the output signal Reduce by half the power) when the frequency of the corresponding channel known as the cut-off frequency (cut - off frequency).Cut-off frequency transmission medium reflects the inherent physical properties. Other cases, it is because people interested in Line filter is installed to limit the bandwidth used by each user. In some cases, because of the add channel Two-pass filter, which corresponds to two-channel cut-off frequency f1 and f2, they were called up under the cut-off frequency and the cut-off frequency.This difference between the two cut-off frequency f2-f1 is called the channel bandwidth. If the input signal bandwidth is less than the bandwidth of channel, then the entire input signal Frequency components can be adopted by the Department of channels, which the letter Road to be the output of the output waveform will be true yet. However, if the input signal bandwidth greater than the channel bandwidth, the signal of a Frequency components can not be more on the channel, so that the signal output will be sent with the sending end of the signal is somewhat different, that is produced Distortion. In order to ensure the accuracy of data transmission, we must limit the signal bandwidth.4 Data transfer rateChannel maximum data transfer rate Unit time to be able to transfer binary data transfer rate as the median. Improve data transfer rate means that the space occupied by each Reduce the time that the sequence of binary digital pulse will reduce the cycle time, of course, will also reduce the pulse width.The previous section we already know, even if the binary digital pulse signal through a limited bandwidth channel will also be the ideal generated wave Shape distortion, and when must the input signal bandwidth, the smaller channel bandwidth, output waveformdistortion will be greater. Another angle Degree that when a certain channel bandwidth, the greater the bandwidth of the input signal, the output signal the greater the distortion, so when the data transmissionRate to a certain degree (signal bandwidth increases to a certain extent), in the on-channel output signal from the receiver could not have been Distortion of the output signal sent to recover a number of sequences. That is to say, even for an ideal channel, the limited bandwidth limit System of channel data transfer rate.At early 1924, H. Nyquist (Nyquist) to recognize the basic limitations of this existence, and deduced that the noise-free Limited bandwidth channel maximum data transfer rate formula. In 1948, C. Shannon (Shannon) put into the work of Nyquist 1 Step-by-step expansion of the channel by the random noise interference. Here we do not add on to prove to those now seen as the result of a classic.Nyquist proved that any continuous signal f (t) through a noise-free bandwidth for channel B, its output signal as a Time bandwidth of B continuous signal g (t). If you want to output digital signal, it must be the rate of g (t) for interval Sample. 2B samples per second times faster than are meaningless, because the signal bandwidth B is higher than the high-frequency component other than a letter has been Road decay away. If g (t) by V of discrete levels, namely, the likely outcome of each sample for the V level of a discrete one, The biggest channel data rate Rm ax as follows:Rmax = 2Blog 2 V (bit / s)For example, a 3000 Hz noise bandwidth of the channel should not transmit rate of more than 6,000 bits / second binary digital signal.In front of us considered only the ideal noise-free channel. There is noise in the channel, the situation will rapidly deteriorate. Channel Thermal noise with signal power and noise power ratio to measure the signal power and noise power as the signal-to-noise ratio (S ignal - to -- Noise Ratio). If we express the signal power S, and N express the noise power, while signal to noise ratio should be expressed as S / N. However, people Usually do not use the absolute value of signal to noise ratio, but the use of 10 lo g1 0S / N to indicate the units are decibels (d B). For the S / N equal 10 Channel, said its signal to noise ratio for the 1 0 d B; the same token, if the channel S / N equal to one hundred, then the signal to noiseratio for the 2 0 d B; And so on. S hannon noise channel has about the maximum data rate of the conclusions are: The bandwidth for the BH z, signal to noise ratio for the S / N Channel, the maximum data rate Rm ax as follows:Rmax = Blog 2 (1 + S / N) (bits / second)For example, for a bandwidth of 3 kHz, signal to noise ratio of 30 dB for the channel, regardless of their use to quantify the number of levels, nor Fast sampling rate control, the data transfer rate can not be greater than 30,000 bits / second. S h a n n o n the conclusions are derived based on information theory Out for a very wide scope, in order to go beyond this conclusion, like you want to invent perpetual motion machine, as it is almost impossible.It is worth noting that, S hannon conclusions give only a theoretical limit, and in fact, we should be pretty near the limit Difficult.SUMMARYMessage signals are (or data) of a magnetic encoder, the signal contains the message to be transmitted. Signal according to the dependent variable Whether or not a row of values, can be classified into analog signals and digital signals, the corresponding communication can be divided into analog communication and digital communication.Fourier has proven: any signal (either analog or digital signal) are different types of harmonic frequencies Composed of any signal has a corresponding bandwidth. And any transmission channel signal attenuation signals will, therefore, Channel transmission of any signal at all, there is a data transfer rate limitations, and this is Chengkui N yquist (Nyquist) theorem and S hannon (Shannon) theorem tells us to conclusions.Transmission medium of computer networks and communication are the most basic part of it at the cost of the entire computer network in a very Large proportion. In order to improve the utilization of transmission medium, we can use multiplexing. Frequency division multiplexing technology has many Road multiplexing, wave division multiplexing and TDM three that they use on different occasions.Data exchange technologies such as circuit switching, packet switching and packetswitching three have their respective advantages and disadvantages. M odem are at Analog phone line for the computer's binary data transmission equipment. Modem AM modulation methods have, FM, phase modulation and quadrature amplitude modulation, and M odem also supports data compression and error control. The concept of data communications Data communication is based on "data" for business communications systems, data are pre-agreed with a good meaning of numbers, letters or symbols and their combinations.参考文献[1]C.Y.Huang and A.Polydoros,“Two small SNR classification rules for CPM,”inProc.IEEE Milcom,vol.3,San Diego,CA,USA,Oct.1992,pp.1236–1240.[2]“Envelope-based classification schemes for continuous-phase binary Frequency-shift-keyed modulations,”in Pr oc.IEEE Milcom,vol.3,Fort Monmouth,NJ,USA,Oct.1994,pp. 796–800.[3]A.E.El-Mahdy and N.M.Namazi,“Classification of multiple M-ary frequency-shift keying over a rayleigh fading channel,”IEEE m.,vol.50,no.6,pp.967–974,June 2002.[4]Consulative Committee for Space Data Systems(CCSDS),Radio Frequency and Modulation SDS,2001,no.401.[5]E.E.Azzouz and A.K.Nandi,“Procedure for automatic recognition of analogue and digital modulations,”IEE mun,vol.143,no.5,pp.259–266,Oct.1996.[6]A.Puengn im,T.Robert,N.Thomas,and J.Vidal,“Hidden Markov models for digital modulation classification in unknown ISI channels,”in Eusipco2007,Poznan,Poland, September 2007,pp.1882–1885.[7]E.Vassalo and M.Visintin,“Carrier phase synchronization for GMSK signals,”I nt.J.Satell. Commun.,vol.20,no.6,pp.391–415,Nov.2002.[8]J.G.Proakis,Digital Communications.Mc Graw Hill,2001.[9]L.Rabiner,“A tutorial on hidden Markov models and selected applications in speechrecognition,”Proc.IEEE,vol.77,no.2,pp.257–286,1989.英文译文：数据通信Gildas Avoine and Philippe OechslinEPFL, Lausanne, Switzerlandfgildas.avoine, philippe.oechsling@ep.ch摘要数据通信是通信技术和计算机技术相结合而产生的一种新的通信方式。

英文文献科技类原文及翻译1

英文文献科技类原文及翻译1On the deployment of V oIP in Ethernet networks:methodology and case studyAbstractDeploying IP telephony or voice over IP (V oIP) is a major and challenging task for data network researchers and designers. This paper outlines guidelines and a step-by-step methodology on how V oIP can be deployed successfully. The methodology can be used to assess the support and readiness of an existing network. Prior to the purchase and deployment of V oIP equipment, the methodology predicts the number of V oIP calls that can be sustained by an existing network while satisfying QoS requirements of all network services and leaving adequate capacity for future growth. As a case study, we apply the methodology steps on a typical network of a small enterprise. We utilize both analysis and simulation to investigate throughput and delay bounds. Our analysis is based on queuing theory, and OPNET is used for simulation. Results obtained from analysis and simulation are in line and give a close match. In addition, the paper discusses many design and engineering issues. These issues include characteristics of V oIP traffic and QoS requirements, V oIP flow and call distribution, defining future growth capacity, and measurement and impact of background traffic. Keywords: Network Design，Network Management，V oIP，Performance Evaluation，Analysis，Simulation，OPNET1 IntroductionThese days a massive deployment of V oIP is taking place over data networks. Most of these networks are Ethernet based and running IP protocol. Many network managers are finding it very attractive and cost effective to merge and unify voice and data networks into one. It is easier to run, manage, and maintain. However, one has to keep in mind that IP networks are best-effort networks that were designed for non-real time applications. On the other hand, V oIP requires timely packet delivery with low latency, jitter, packet loss, andsufficient bandwidth. To achieve this goal, an efficient deployment of V oIP must ensure these real-time traffic requirements can be guaranteed over new or existing IP networks. When deploying a new network service such as V oIP over existing network, many network architects, managers, planners, designers, and engineers are faced with common strategic, and sometimes challenging, questions. What are the QoS requirements for V oIP? How will the new V oIP load impact the QoS for currently running network services and applications? Will my existing network support V oIP and satisfy the standardized QoS requirements? If so, how many V oIP calls can the network support before upgrading prematurely any part of the existing network hardware? These challenging questions have led to the development of some commercial tools for testing the performance of multimedia applications in data networks. A list of the available commercial tools that support V oIP is listed in [1,2]. For the most part, these tools use two common approaches in assessing the deployment of V oIP into the existing network. One approach is based on first performing network measurements and then predicting the network readiness for supporting V oIP. The prediction of the network readiness is based on assessing the health of network elements. The second approach is based on injecting real V oIP traffic into existing network and measuring the resulting delay, jitter, and loss. Other than the cost associated with the commercial tools, none of the commercial tools offer a comprehensive approach for successful V oIP deployment. I n particular, none gives any prediction for the total number of calls that can be supported by the network taking into account important design and engineering factors. These factors include V oIP flow and call distribution, future growth capacity, performance thresholds, impact of V oIP on existing network services and applications, and impact background traffic on V oIP. This paper attempts to address those important factors and layout a comprehensive methodology for a successful deployment of any multimedia application such as V oIP and video conferencing. However, the paper focuses on V oIP as the new service of interest to be deployed. The paper also contains many useful engineering and design guidelines, and discusses many practical issues pertaining to the deployment of V oIP. These issues include characteristics of V oIP traffic and QoS requirements, V oIP flow and call distribution, defining future growth capacity, and measurement and impact of background traffic. As a case study, we illustrate how ourapproach and guidelines can be applied to a typical network of a small enterprise. The rest of the paper is organized as follows. Section 2 presents a typical network topology of a small enterprise to be used as a case study for deploying V oIP. Section 3 outlines practical eight-step methodology to deploy successfully V oIP in data networks. Each step is described in considerable detail. Section 4 describes important design and engineering decisions to be made based on the analytic and simulation studies. Section 5 concludes the study and identifies future work.2 Existing network3 Step-by-step methodologyFig. 2 shows a flowchart of a methodology of eight steps for a successful V oIP deployment. The first four steps are independent and can be performed in parallel. Before embarking on the analysis and simulation study, in Steps 6 and 7, Step 5 must be carried out which requires any early and necessary redimensioning or modifications to the existing network. As shown, both Steps 6 and 7 can be done in parallel. The final step is pilot deployment.3.1. VoIP traffic characteristics, requirements, and assumptionsFor introducing a new network service such as V oIP, one has to characterize first the nature of its traffic, QoS requirements, and any additional components or devices. For simplicity, we assume a point-to-point conversation for all V oIP calls with no call conferencing. For deploying V oIP, a gatekeeper or Call Manager node has to be added to the network [3,4,5]. The gatekeeper node handles signaling for establishing, terminating, and authorizing connections of all V oIP calls. Also a V oIP gateway is required to handle external calls. A V oIP gateway is responsible for converting V oIP calls to/from the Public Switched Telephone Network (PSTN). As an engineering and design issue, the placement of these nodes in the network becomes crucial. We will tackle this issue in design step 5. Otherhardware requirements include a V oIP client terminal, which can be a separate V oIP device, i.e. IP phones, or a typical PC or workstation that is V oIP-enabled. A V oIP-enabled workstation runs V oIP software such as IP Soft Phones .Fig. 3 identifies the end-to-end V oIP components from sender to receiver [9]. The first component is the encoder which periodically samples the original voice signal and assigns a fixed number of bits to each sample, creating a constant bit rate stream. The traditional sample-based encoder G.711 uses Pulse Code Modulation (PCM) to generate 8-bit samples every 0.125 ms, leading to a data rate of 64 kbps . The packetizer follows the encoder and encapsulates a certain number of speech samples into packets and adds the RTP, UDP, IP, and Ethernet headers. The voice packets travel through the data network. An important component at the receiving end, is the playback buffer whose purpose is to absorb variations or jitter in delay and provide a smooth playout. Then packets are delivered to the depacketizer and eventually to the decoder which reconstructs the original voice signal. We will follow the widely adopted recommendations of H.323, G.711, and G.714 standards for V oIP QoS requirements.Table 1 compares some commonly used ITU-T standard codecs and the amount ofone-way delay that they impose. To account for upper limits and to meet desirable quality requirement according to ITU recommendation P.800, we will adopt G.711u codec standards for the required delay and bandwidth. G.711u yields around 4.4 MOS rating. MOS, Mean Opinion Score, is a commonly used V oIP performance metric given in a scale of 1–5, with 5 is the best. However, with little compromise to quality, it is possible to implement different ITU-T codecs that yield much less required bandwidth per call and relatively a bit higher, but acceptable, end-to-end delay. This can be accomplished by applying compression, silence suppression, packet loss concealment, queue management techniques, and encapsulating more than one voice packet into a single Ethernet frame.3.1.1. End-to-end delay for a single voice packetFig. 3 illustrates the sources of delay for a typical voice packet. The end-to-end delay is sometimes referred to by M2E or Mouth-to-Ear delay. G.714 imposes a maximum total one-way packet delay of 150 ms end-to-end for V oIP applications . In [22], a delay of up to 200 ms was considered to be acceptable. We can break this delay down into at least three different contributing components, which are as follows (i) encoding, compression, and packetization delay at the sender (ii) propagation, transmission and queuing delay in the network and (iii) buffering, decompression, depacketization, decoding, and playback delay at the receiver.3.1.2. Bandwidth for a single callThe required bandwidth for a single call, one direction, is 64 kbps. G.711 codec samples 20 ms of voice per packet. Therefore, 50 such packets need to be transmitted per second. Each packet contains 160 voice samples in order to give 8000 samples per second. Each packet is sent in one Ethernet frame. With every packet of size 160 bytes, headers of additional protocol layers are added. These headers include RTP+UDP+IP+Ethernet with preamble of sizes 12+8+20+26, respectively. Therefore, a total of 226 bytes, or 1808 bits, needs to be transmitted 50 times per second, or 90.4 kbps, in one direction. For both directions, the required bandwidth for a single call is 100 pps or 180.8 kbps assuming a symmetric flow.3.1.3. Other assumptionsThroughout our analysis and work, we assume voice calls are symmetric and no voice conferencing is implemented. We also ignore the signaling traffic generated by the gatekeeper. We base our analysis and design on the worst-case scenario for V oIP call traffic. The signaling traffic involving the gatekeeper is mostly generated prior to the establishment of the voice call and when the call is finished. This traffic is relatively small compared to the actual voice call traffic. In general, the gatekeeper generates no or very limited signaling traffic throughout the duration of the V oIP call for an already established on-going call. In this paper, we will implement no QoS mechanisms that can enhance the quality of packet delivery in IP networks.A myriad of QoS standards are available and can be enabled for network elements. QoS standards may i nclude IEEE 802.1p/Q, the IETF’s RSVP, and DiffServ.Analysis of implementation cost, complexity, management, and benefit must be weighed carefully before adopting such QoS standards. These standards can be recommended when the cost for upgrading some network elements is high and the network resources are scarce and heavily loaded.3.2. VoIP traffic flow and call distributionKnowing the current telephone call usage or volume of the enterprise is an important step for a successful V oIP deployment. Before embarking on further analysis or planning phases for a V oIP deployment, collecting statistics about of the present call volume and profiles is essential. Sources of such information are organization’s PBX, telephone records and bills. Key characteristics of existing calls can include the number of calls, number of concurrent calls, time, duration, etc. It is important to determine the locations of the call endpoints, i.e. the sources and destinations, as well as their corresponding path or flow. This will aid in identifying the call distribution and the calls made internally or externally. Call distribution must include percentage of calls within and outside of a floor, building, department, or organization. As a good capacity planning measure, it is recommended to base the V oIP call distribution on the busy hour traffic of phone calls for the busiest day of a week or a month. This will ensure support of the calls at all times with high QoS for all V oIP calls.When such current statistics are combined with the projected extra calls, we can predict the worst-case V oIP traffic load to be introduced to the existing network.Fig. 4 describes the call distribution for the enterprise under study based on the worst busy hour and the projected future growth of V oIP calls. In the figure, the call distribution is described as a probability tree. It is also possible to describe it as a probability matrix. Some important observations can be made about the voice traffic flow for inter-floor and external calls. For all these type of calls, the voice traffic has to be always routed through the router. This is so because Switchs 1 and 2 are layer 2 switches with VLANs configuration. One can observe that the traffic flow for inter-floor calls between Floors 1 and 2 imposes twice the load on Switch 1, as the traffic has to pass through the switch to the router and back to the switch again. Similarly, Switch 2 experiences twice the load for external calls from/to Floor 3.3.3. Define performance thresholds and growth capacityIn this step, we define the network performance thresholds or operational points for a number of important key network elements. These thresholds are to be considered when deploying the new service. The benefit is twofold. First, the requirements of the new service to be deployed are satisfied. Second, adding the new service leaves the network healthy and susceptible to future growth. Two important performance criteria are to be taken into account.First is the maximum tolerable end-to-end delay; and second is the utilization bounds or thresholds of network resources. The maximum tolerable end-to-end delay is determined by the most sensitive application to run on the network. In our case, it is 150 ms end-to-end for V oIP. It is imperative to note that if the network has certain delay sensitive applications, the delay for these applications should be monitored, when introducing V oIP traffic, such that they do not exceed their required maximum values. As for the utilization bounds for network resources, such bounds or thresholds are determined by factors such as current utilization, future plans, and foreseen growth of the network. Proper resource and capacity planning is crucial. Savvy network engineers must deploy new services with scalability in mind, and ascertain that the network will yield acceptable performance under heavy and peak loads, with no packet loss. V oIP requires almost no packet loss. In literature, 0.1–5% packet loss was generally asserted. However, in [24] the required V oIP packet loss was conservatively suggested to be less than 105 . A more practical packet loss, based on experimentation, of below 1% was required in [22]. Hence, it is extremely important not to utilize fully the network resources. As rule-of-thumb guideline for switched fast full-duplex Ethernet, the average utilization limit of links should be 190%, and for switched shared fast Ethernet, the average limit of links should be 85% [25]. The projected growth in users, network services, business, etc. must be all taken into consideration to extrapolate the required growth capacity or the future growth factor. In our study, we will ascertain that 25% of the available network capacity is reserved for future growth and expansion. For simplicity, we will apply this evenly to all network resources of the router, switches, and switched-Ethernet links. However, keep in mind this percentage in practice can be variable for each network resource and may depend on the current utilization and the required growth capacity. In our methodology, the reservation of this utilization of network resources is done upfront, before deploying the new service, and only the left-over capacity is used for investigating the network support of the new service to be deployed.3.4. Perform network measurementsIn order to characterize the existing network traffic load, utilization, and flow, networkmeasurements have to be performed. This is a crucial step as it can potentially affect results to be used in analytical study and simulation. There are a number of tools available commercially and noncommercially to perform network measurements. Popular open-source measurement tools include MRTG, STG, SNMPUtil, and GetIF [26]. A few examples of popular commercially measurement tools include HP OpenView, Cisco Netflow, Lucent VitalSuite, Patrol DashBoard, Omegon NetAlly, Avaya ExamiNet, NetIQ Vivinet Assessor, etc. Network measurements must be performed for network elements such as routers, switches, and links. Numerous types of measurements and statistics can be obtained using measurement tools. As a minimum, traffic rates in bits per second (bps) and packets per second (pps) must be measured for links directly connected to routers and switches. To get adequate assessment, network measurements have to be taken over a long period of time, at least 24-h period. Sometimes it is desirable to take measurements over several days or a week. One has to consider the worst-case scenario for network load or utilization in order to ensure good QoS at all times including peak hours. The peak hour is different from one network to another and it depends totally on the nature of business and the services provided by the network.Table 2 shows a summary of peak-hour utilization for traffic of links in both directions connected to the router and the two switches of the network topology of Fig. 1. These measured results will be used in our analysis and simulation study.外文文献译文以太网网络电话传送调度：方法论与案例分析摘要对网络数据研究者与设计师来说，IP电话或者语音IP电话调度是一项重大而艰巨的任务。

脉冲宽度调制(PWM)大学毕业论文外文文献翻译及原文

毕业设计（论文）外文文献翻译文献、资料中文题目：脉冲宽度调制（PWM）文献、资料英文题目：文献、资料来源：文献、资料发表（出版）日期：院（部）：专业：班级：姓名：学号：指导教师：翻译日期： 2017.02.14外文原文Pulse-width modulationPulse-width modulation (PWM)is a modulation technique that conforms the width of the pulse, formally the pulse duration, based on modulator signal information. Although this modulation technique can be used to encode information for transmission, its main use is to allow the control of the power supplied to electrical devices, especially to inertial loads such as motors. In addition, PWM is one of the two principal algorithms used in photovoltaic solar battery chargers,[1]The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off periods, the higher the power supplied to the load is.The PWM switching frequency has to be much faster than what would affect the load, which is to say the device that uses the power. Typically switchings have to be done several times a minute in an electric stove, 120 Hz in a lamp dimmer, from few kilohertz (kHz) to tens of kHz for a motor drive and well into the tens or hundreds of kHz in audio amplifiers and computer power supplies.The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time; a low duty cycle corresponds to low power, because the power is off for most of the time. Duty cycle is expressed in percent, 100% being fully on.The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there is practically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being the product of voltage and current, is thus in both cases close to zero. PWM also works well with digital controls, which, because of their on/off nature, can easily set the needed duty cycle.PWM has also been used in certain communication systems where its duty cycle has been used to convey information over a communications channel.HistoryIn the past, when only partial power was needed (such as for a sewing machine motor), a rheostat (located in the sewing machine's foot pedal) connected in series with the motor adjusted the amount of current flowing through the motor, but also wasted power as heat in the resistor element. It was an inefficient scheme, but tolerable because the total power was low. This was one of several methods of controlling power. There were others—some still in use—such as variable autotransformers, including thetrademarked 'Autrastat' for theatrical lighting; and the Variac, for general AC power adjustment. These were quite efficient, but also relatively costly.For about a century, some variable-speed electric motors have had decent efficiency, but they were somewhat more complex than constant-speed motors, and sometimes required bulky external electrical apparatus, such as a bank of variable power resistors or rotating converter such as Ward Leonard drive.However, in addition to motor drives for fans, pumps and robotic servos, there was a great need for compact and low cost means for applying adjustable power for many devices, such as electric stoves and lamp dimmers.One early application of PWM was in the Sinclair X10, a 10 W audio amplifier available in kit form in the 1960s. At around the same time PWM started to be used in AC motor control.Fig. 1: a pulse wave, showing the definitions of , and D.Pulse-width modulation uses a rectangular pulse wave whose pulse width is modulated resulting in thevariation of the average value of the waveform. If we consider a pulse waveform , with period ,low value , a high value and a duty cycle D (see figure 1), the average value of thewaveform is given by:As is a pulse wave, its value is for and for. The above expression then becomes:This latter expression can be fairly simplified in many cases where as. From this, it is obvious that the average value of the signal () is directly dependent on the duty cycle DFig. 2: A simple method to generate the PWM pulse train corresponding to a given signal is the intersective PWM: the signal (here the red sinewave) is compared with a sawtooth waveform (blue). When the latter is less than the former, the PWM signal (magenta) is in high state (1). Otherwise it is in the low state (0).The simplest way to generate a PWM signal is the intersective method, which requires only a sawtooth or atriangle waveform (easily generated using a simple oscillator) and a comparator. When the value of the reference signal (the red sine wave in figure 2) is more than the modulation waveform (blue), the PWM signal (magenta) is in the high state, otherwise it is in the low state.Time proportioningMany digital circuits can generate PWM signals (e.g., many microcontrollers have PWM outputs). They normally use a counter that increments periodically (it is connected directly or indirectly to the clock of the circuit) and is reset at the end of every period of the PWM. When the counter value is more than the reference value, the PWM output changes state from high to low (or low to high).[3]This technique is referred to as time proportioning, particularly as time-proportioning control[4]– which proportion of a fixed cycle time is spent in the high state.The incremented and periodically reset counter is the discrete version of the intersecting method's sawtooth. The analog comparator of the intersecting method becomes a simple integer comparison between the current counter value and the digital (possibly digitized) reference value. The duty cycle can only be varied in discrete steps, as a function of the counter resolution. However, a high-resolution counter can provide quite satisfactory performance.PWM sampling theoremThe process of PWM conversion is non-linear and it is generally supposed that low pass filter signal recovery is imperfect for PWM. The PWM sampling theorem[6] shows that PWM conversion can be perfect. The theorem states that "Any bandlimited baseband signal within ±0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level."Power deliveryPWM can be used to control the amount of power delivered to a load without incurring the losses thatwould result from linear power delivery by resistive means. Potential drawbacks to this technique are the pulsations defined by the duty cycle, switching frequency and properties of the load. With a sufficiently high switching frequency and, when necessary, using additional passive electronic filters, the pulse train can be smoothed and average analog waveform recovered.High frequency PWM power control systems are easily realisable with semiconductor switches. As explained above, almost no power is dissipated by the switch in either on or off state. However, during the transitions between on and off states, both voltage and current are nonzero and thus power is dissipated in the switches. By quickly changing the state between fully on and fully off (typically less than 100 nanoseconds), the power dissipation in the switches can be quite low compared to the power being delivered to the load.Modern semiconductor switches such as MOSFETs or Insulated-gate bipolar transistors (IGBTs) are well suited components for high efficiency controllers. Frequency converters used to control AC motors may have efficiencies exceeding 98%. Switching power supplies have lower efficiency due to low output voltage levels (often even less than 2 V for microprocessors are needed) but still more than 70–80% efficiency can be achieved.Variable-speed fan controllers for computers usually use PWM, as it is far more efficient when compared to a potentiometer or rheostat. (Neither of the latter is practical to operate electronically; they would require a small drive motor.)Light dimmers for home use employ a specific type of PWM control. Home-use light dimmers typically include electronic circuitry which suppresses current flow during defined portions of each cycle of the AC line voltage. Adjusting the brightness of light emitted by a light source is then merely a matter of setting at what voltage (or phase) in the AC halfcycle the dimmer begins to provide electrical current to the light source (e.g. by using an electronic switch such as a triac). In this case the PWM duty cycle is the ratio of the conduction time to the duration of the half AC cycle defined by the frequency of the AC line voltage (50 Hz or 60 Hz depending on the country).V oltage regulationMain article: Switched-mode power supplyPWM is also used in efficient voltage regulators. By switching voltage to the load with the appropriate duty cycle, the output will approximate a voltage at the desired level. The switching noise is usually filtered with an inductor and a capacitor.One method measures the output voltage. When it is lower than the desired voltage, it turns on the switch. When the output voltage is above the desired voltage, it turns off the switch.Audio effects and amplificationPWM is sometimes used in sound (music) synthesis, in particular subtractive synthesis, as it gives a sound effect similar to chorus or slightly detuned oscillators played together. (In fact, PWM is equivalent to the difference of two sawtooth waves with one of them inverted.[1]) The ratio between the high and low level is typically modulated with a low frequency oscillator. In addition, varying the duty cycle of a pulse waveform in a subtractive-synthesis instrument creates useful timbral variations. Some synthesizers have a duty-cycle trimmer for their square-wave outputs, and that trimmer can be set by ear; the 50% point (true square wave) was distinctive, because even-numbered harmonics essentially disappear at 50%. Pulse waves, usually 50%, 25%, and 12.5%, make up the soundtracks of classic video games.A new class of audio amplifiers based on the PWM principle is becoming popular. Called "Class-D amplifiers", they produce a PWM equivalent of the analog input signal which is fed to the loudspeaker via a suitable filter network to block the carrier and recover the original audio. These amplifiers arecharacterize d by very good efficiency figures (≥ 90%) and compact size/light weight for large power outputs. For a few decades, industrial and military PWM amplifiers have been in common use, often for drivingservo motors. Field-gradient coils in MRI machines are driven by relatively high-power PWM amplifiers.Historically, a crude form of PWM has been used to play back PCM digital sound on the PC speaker, which is driven by only two voltage levels, typically 0 V and 5 V. By carefully timing the duration of the pulses, and by relying on the speaker's physical filtering properties (limited frequency response, self-inductance, etc.) it was possible to obtain an approximate playback of mono PCM samples, although at a very low quality, and with greatly varying results between implementations.In more recent times, the Direct Stream Digital sound encoding method was introduced, which uses a generalized form of pulse-width modulation called pulse density modulation, at a high enough sampling rate (typically in the order of MHz) to cover the whole acoustic frequencies range with sufficient fidelity. This method is used in the SACD format, and reproduction of the encoded audio signal is essentially similar to the method used in class-D amplifiers.中文翻译一、脉冲宽度调制脉冲宽度调制（PWM），是一种在一定的脉冲持续时间内，基于调制信号来追踪所希望达到的脉冲宽度的调制方式。

毕业论文英语翻译及原文

in the station orthogonal coordinate system origin of a random point can begotthrough the translation androtation of its WGS-84 position vector
=H（ - ）（1）
respectively, the expression can be easily gained as follows
Then, the relation equation between the two baseline vectors is expressedas
There are two steps in the GPS observation data processing course. They are baseline calculationand network adjustment. The baseline vectors in WGS-84 can be firstly got using baseline calculation.Secondly, the baseline vector transformation from WGS-84 to the station orthogonal coordinatesystem can be done with (3). At last, the adjustment of GPS deformatihestation orthogonal coordinate system can be successfully finished.
If the position vector of the station orthogonal coordinate system originP0inWGS-84 isexpressed as = , according to thegeodetic latitude and longitude（，）, theposition vector

数字信号处理英文文献及翻译

英文原文The simulation and the realization of the digital filterWith the information age and the advent of the digital world, digital signal processing has become one of today's most important disciplines and door technology. Digital signal processing in communications, voice, images, automatic control, radar, military, aerospace, medical and household appliances, and many other fields widely applied. In the digital signal processing applications, the digital filter is important and has been widely applied.1、 figures Unit on :Analog and digital filtersIn signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range.The following block diagram illustrates the basic idea.There are two main kinds of filter, analog and digital. They are quitedifferent in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equalisers in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. Adigital filter uses a digital processor to perform numerical calculations on sampled values of the signal. The processor may be a general-purpose computersuch as a PC, or a specialised DSP (Digital Signal Processor) chip. The analog input signal must first be sampled and digitised using an ADC (analog todigital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to theprocessor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form.Note that in a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current.The following diagram shows the basic setup of such a system.Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y.According to figures filter function 24-hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIRfilters have the advantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables mayfacilitate simple. It is the shortcomings of the nonlinear phase; Linear phase if required, will use the entire network phase-correction. Image processing and transmission of data collection is required with linear phase filters identity. And FIR linear phase digital filter to achieve, but an arbitrary margincharacteristics. Impact from the digital filter response of the units can be divided into two broad categories : the impact of the limited response (FIR) filters, and unlimited number ofshocks to (IIR) digital filters.FIR filters can be strictly linear phase, but because the system FIR filter function extremity fixed at the original point, it can only use the higher number of bands to achieve their high selectivity for the same filter design indicators FIR filter called band than a few high-IIR 5-10 times, the cost is higher, Signal delay is also larger. But if the same linear phase, IIR filters must be network-wide calibration phase, the same section also increase the number of filters and network complexity. FIR filters can be used to achieve non-Digui way, not in a limited precision of a shock, and into the homes and quantitative factors of uncertainty arising from the impact of errors than IIR filter small number, and FIR filter can be used FFT algorithms, the computational speed. But unlike IIR filter can filter through the simulation results, there is no ready-made formula FIR filter must use computer-aided design software (such as MATLAB) to calculate. So, a broader application of FIR filters, and IIR filters are not very strict requirements on occasions.Unit from sub-functions can be divided into the following four categories :(1) Low-filter (LPF);(2) high-filter (HPF);(3) belt-filter (BPF);(4) to prevent filter (BSF).The following chart dotted line for the ideals of the filter frequency characteristics :A1(f) A2(f)10 c2f c2 f(a) (b)A3(f) A4(f)0 c1c2f c1c2 f(c) (d)(a)LPF (b)HPF (c)BPF (d)BSF2、 MATLAB introducedMATLAB is a matrix laboratory (Matrix Laboratory) is intended. In addition to an excellent value calculation capability, it also provides professional symbols terms, word processing, visualization modeling, simulation and real-time control functions. MATLAB as the world's top mathematical software applications, with a strong engineering computing, algorithms research, engineering drawings, applications development, data analysis and dynamic simulation, and other functions, in aerospace, mechanical manufacturing and construction fields playing an increasingly important role. And the C language function rich, the use of flexibility, high-efficiency goals procedures. High language both advantages as well as low level language features. Therefore, C language is the most widely used programming language. Although MATLAB is a complete, fully functional programming environment, but in some cases, data and procedures with the external environment of the world is very necessary and useful. Filter design using Matlab, could be adjusted with the design requirements and filter characteristics of the parameters, visual simple, greatly reducing the workload for the filter design optimization.In the electricity system protection and secondary computer control, many signal processing and analysis are based on are certain types Yeroskipou and the second harmonics of the system voltage and current signals (especially at D process), are mixed with a variety of complex components, the filter has been installed power system during the critical components. Current computer protection and the introduction of two digital signal processing software main filter. Digital filter design using traditional cumbersome formula, the need to change the parameters after recalculation, especially in high filters, filter design workload. Uses MATLAB signal processing boxes can achieve rapid and effective digital filter design and simulation.MATLAB is the basic unit of data matrix, with its directives Biaodashi mathematics, engineering, commonly used form is very similar, it is used to solve a problem than in MATLAB C, Fortran and other languages End precision much the same thing. The popular MATLAB 5.3/Simulink3.0 including hundreds of internal function with the main pack and 30 types of tool kits (Toolbox). kits can be divided into functional tool kits and disciplines toolkit. MATLAB tool kit used to expand the functional symbols terms, visualization simulation modelling, word processing and real-time control functions. professional disciplines toolkit is a stronger tool kits, tool kits control, signal processing tool kit, tool kits, etc. belonging to such communicationsMATLAB users to open widely welcomed. In addition to the internal function, all the packages MATLAB tool kits are readable document and the document could be amended, modified or users through Yuanchengxu the construction of new procedures to prepare themselves for kits.3、 Digital filter designDigital filter design of the basic requirementsDigital filter design must go through three steps :(1) Identification of indicators : In the design of a filter, there must be some indicators. These indicators should be determined on the basis of the application. In many practical applications, digital filters are often used to achieve the frequency operation. Therefore, indicators in the form of general jurisdiction given frequency range and phase response. Margins key indicators given in two ways. The first is absolute indicators. It provides a function to respond to the demands of the general application of FIR filter design. The second indicator is the relative indicators. Its value in the form of answers to decibels. In engineering practice, the most popular of such indicators. For phase response indicators forms, usually in the hope that the system with a linear phase frequency bands human. Using linear phase filter design with thefollowing response to the indicators strengths：①it only contains a few algorithms, no plural operations；②there is delay distortion, only a fixed amount of delay; ③the filter length N (number of bands for N-1), the volume calculation for N/2 magnitude.(2) Model approach : Once identified indicators can use a previous study of the basic principles and relationships, a filter model to be closer to the target system.(3) Achieved : the results of the above two filters, usually by differential equations, system function or pulse response to describe. According to this description of hardware or software used to achieve it.4、 Introduced FPGA Programmable logic device is a generic logic can use a variety of chips, which is to achieve ASIC ASIC (Application Specific Integrated Circuit) semi-customized device, Its emergence and development of electronic systems designers use CAD tools to design their own laboratory in the ASIC device. Especially FPGA (Field Programmable Gate Array) generated and development, as a microprocessor, memory, the figures for electronic system design and set a new industry standard (that is based on standard product sales catalogue in the market to buy). Is a digital system for microprocessors, memories, FPGA or three standard building blocks constitute their integration direction.Digital circuit design using FPGA devices, can not only simplify the design process and can reduce the size and cost of the entire system, increasing system reliability. They do not need to spend the traditional sense a lot of time and effort required to create integrated circuits, to avoid the investment risk and become the fastest-growing industries of electronic devices group. Digital circuit design system FPGA devices using the following main advantages (1) Design flexibleUse FPGA devices may not in the standard series device logic functional limitations. And changes in system design and the use of logic in any one stage of the process, and only through the use of re-programming the FPGA device can be completed, the system design provides for great flexibility.(2) Increased functional densityFunctional density in a given space refers to the number of functional integration logic. Programmable logic chip components doors several high, a FPGA can replace several films, film scores or even hundreds of small-scale digital IC chip illustrated in the film. FPGA devices using the chip to use digital systems in small numbers, thus reducing the number of chips used to reduce the number of printed size and printed, and will ultimately lead to a reduction in the overall size of the system.(3) Improve reliabilityPrinting plates and reduce the number of chips, not only can reduce system size, but it greatly enhanced system reliability. A higher degree ofintegration than systems in many low-standard integration components for the design of the same system, with much higher reliability. FPGA device used to reduce the number of chips required to achieve the system in the number printed on the cord and joints are reduced, the reliability of the system can be improved.(4) Shortening the design cycleAs FPGA devices and the programmable flexibility, use it to design a system for longer than traditional methods greatly shortened. FPGA device master degrees high, use printed circuit layout wiring simple. At the same time, success in the prototype design, the development of advanced tools, a high degree of automation, their logic is very simple changes quickly. Therefore, the use of FPGA devices can significantly shorten the design cycle system, and speed up the pace of product into the market, improving product competitiveness.(5) Work fastFPGA/CPLD devices work fast, generally can reach several original Hertz, far larger than the DSP device. At the same time, the use of FPGA devices, the system needed to achieve circuitclasses and small, and thus the pace of work of the entire system will be improved.(6) Increased system performance confidentialityMany FPGA devices have encryption functions in the system widely used FPGA devices can effectively prevent illegal copying products were others(7) To reduce costsFPGA device used to achieve digital system design, if only device itself into the price, sometimes you would not know it advantages, but there are many factors affecting the cost of the system, taken together, the cost advantages of using FPGA is obvious. First, the use of FPGA devices designed to facilitate change, shorten design cycles, reduce development costs for system development; Secondly, the size and FPGA devices allow automation needs plug-ins, reducing the manufacturing system to lower costs; Again, the use of FPGA devices can enhance system reliability, reduced maintenance workload, thereby lowering the cost of maintenance services for the system. In short, the use of FPGA devices for system design to save costs.FPGA design principles :FPGA design an important guiding principles : the balance and size and speed of exchange, the principles behind the design of the filter expression of a large number of certification.Here, "area" means a design exertion FPGA/CPLD logic resources of the FPGA can be used to the typical consumption (FF) and the search table (IUT) to measuremore general measure can be used to design logic equivalence occupied by the door is measured. "pace" means stability operations in the chip design can achieve the highest frequency, the frequency of the time series design situation, and design to meet the clock cycle -- PADto pad, Clock Setup Time, Clock Hold Beijing, Clock-to-Output Delay, and other characteristics of many time series closely related. Area (area) and speed (speed) runs through the two targets FPGA design always is the ultimate design quality evaluation criteria. On the size and speed of the two basic concepts : balance of size and speed and size and speed of swap.One pair of size and speed is the unity of opposites contradictions body. Requirements for the design of a design while the smallest, highest frequency of operation is unrealistic. More scientific goal should be to meet the design requirements of the design time series (includes requirements for the design frequency) premise, the smallest chip area occupied. Or in the specified area, the design time series cushion greater frequency run higher. This fully embodies the goals of both size and speed balanced thinking. On the size and speed requirements should not be simply interpreted as raising the level and design engineers perfect sexual pursuit, and should recognize that they are products and the quality and cost of direct relevance. If time series cushion larger design, running relatively high frequency, that the design Jianzhuangxing stronger, more quality assurance system as a whole; On the other hand, the smaller size of consumption design is meant to achieve in chip unit more functional modules, the chip needs fewer, the entire system has been significantly reduced cost. As a contradiction of the two components, the size and speed is not the same status. In contrast, meet the timetables and work is more important for some frequency when both conflicts, the use of priority guidelines.Area and the exchange rate is an important FPGA design ideas. Theoretically, if a design time series cushion larger, can run much higher than the frequency design requirements, then we can through the use of functional modules toreduce the consumption of the entire chip design area, which is used for space savings advantages of speed; Conversely, if the design of a time series demanding, less than ordinary methods of design frequency then generally flow through the string and data conversion, parallel reproduction of operational module, designed to take on the whole "string and conversion" and operate in the export module to chip in the data "and string conversion" from the macro point of view the whole chip meets the requirements of processing speed, which is equivalent to the area of reproduction - rate increase.For example. Assuming that the digital signal processing system is 350Mb/s input data flow rate, and in FPGA design, data processing modules for maximum processing speed of 150Mb/s, because the data throughput processing module failed to meet requirements, it is impossible to achieve directly in the FPGA. Such circumstances, they should use "area-velocity" thinking, at least three processing modules from the first data sets will be imported and converted, and then use these three modules parallel processing of data distribution, then the results "and string conversion," we have complete data rate requirements. We look at both ends of the processing modules, data rate is 350Mb/s, and in view of the internal FPGA, each sub-module handles the data rate is 150Mb/s, in fact, all the data throughput is dependent on three security modules parallel processing subsidiary completed, that is used by more chip area achieve high-speed processing through "the area of reproduction for processing speed enhancement" and achieved design.FPGA is the English abbreviation Field of Programmable Gate Array for the site programmable gate array, which is in Pal, Gal, Epld, programmable device basis to further develop the product. It is as ASIC (ASIC) in the field of a semi-customized circuit and the emergence of both a customized solution to the shortage circuit, but overcome the original programmable devices doors circuit few limited shortcomings.FPGA logic module array adopted home (Logic Cell Array), a new concept of internal logic modules may include CLB (Configurable Logic Block), export import module IOB (Input Output Block) and internal links (Interconnect) 3. FPGA basic features are :(1) Using FPGA ASIC design ASIC using FPGA circuits, the chip can be used,while users do not need to vote films production.(2) FPGA do other customized or semi-customized ASIC circuits throughout the Chinese specimen films.3) FPGA internal capability and rich I/O Yinjue.4) FPGA is the ASIC design cycle, the shortest circuit, the lowest development costs, risks among the smallest device5) FPGA using high-speed Chmos crafts, low consumption, with CMOS, TTL low-power compatibleIt can be said that the FPGA chip is for small-scale systems to improve system integration, reliability one of the bestCurrently FPGA many varieties, the Revenue software series, TI companies TPC series, the fiex ALTERA company series FPGA is stored in films from theinternal RAM procedures for the establishment of the state of its work, therefore, need to programmed the internal Ram. Depending on the different configuration, users can use a different programming methodsPlus electricity, FPGA, EPROM chips will be read into the film, programming RAM 中 data, configuration is completed, FPGA into working order. Diaodian, FPGA resume into white films, the internal logic of relations disappear, FPGA to repeated use. FPGA's programming is dedicated FPGA programming tool, using generic EPROM, prom programming device can. When the need to modify functional FPGA, EPROM can only change is. Thus, with a FPGA, different programming datato produce different circuit functions. Therefore, the use of FPGA very flexible.There are a variety of FPGA model : the main model for a parallel FPGA plus a EPROM manner; From the model can support a number of films FPGA; serial prom programming model could be used serial prom FPGA programming FPGA; The external model can be engineered as microprocessors from its programming microprocessors.Verilog HDL is a hardware description language for the algorithm level, doors at the level of abstract level to switch-level digital system design modelling. Modelling of the target figure by the complexity of the system can be something simple doors and integrity of electronic digital systems. Digital system to the levels described, and in the same manner described in Hin-time series modelling.Verilog HDL language with the following description of capacity : design behaviour characteristics, design data flow characteristics, composition and structure designed to control and contain the transmission and waveform design a certification mechanism. All this with the use of a modelling language. In addition, Verilog HDL language programming language interface provided by the interface in simulation, design certification from the external design of the visit, including specific simulation control and operation.Verilog HDL language grammar is not only a definition, but the definition of each grammar structure are clear simulation, simulation exercises. Therefore, the use of such language to use Verilog simulation models prepared by a certification. From the C programming language, the language inherited multiple operating sites and structures. Verilog HDL provides modelling capacity expansion, many of the initial expansion would be difficult to understand. However, the core subsets of Verilog HDL language very easy to learn and use, which is sufficient for most modelling applications. Of course, the integrityof the hardware description language is the most complex chips from theintegrity of the electronic systems described.historyVerilog HDL language initially in 1983 by Gateway Design Automation companies for product development simulator hardware modelling language. Then it is only a dedicated language. Since their simulation, simulation devices widely used products, Verilog HDL as a user-friendly and practical language for many designers gradually accepted. In an effort to increase the popularity of the language activities, Verilog HDL language in 1990 was a public area. Open Verilog International (OVI) is to promote the development of Verilog international organizations. 1992, decided to promote OVI OVI standards as IEEE Verilog standards. The effort will ultimately succeed, a IEEE1995 Verilog language standard, known as IEEE Std 1364-1995. Integrity standards in Verilog hardware description language reference manual contains a detailed description.Main capacity：Listed below are the main Verilog hardware description language ability*Basic logic gate, and, for example, or have embedded in the language and nand * Users of the original definition of the term (UDP), the flexibility. Users can be defined in the original language combinations logic original language, the original language of logic could also be time series* Switches class infrastructure models, such as the nmos and pmos also be embedded in the language* Hin-language structure designated for the cost of printing the design and trails Shi Shi and design time series checks.* Available three different ways to design or mixed mode modelling. These methods include : acts described ways - use process of structural modelling; Data flow approach - use of a modelling approach Fuzhi expression; Structured way - using examples of words to describe modular doors and modelling.* Verilog HDL has two types of data : data types and sequence data line network types. Line network types that the physical links between components and sequence types that abstract data storage components.* To describe the level design, the structure can be used to describe any level module example * Design size can be arbitrary; Language is design size (size) impose any restrictions* Verilog HDL is no longer the exclusive language of certain companies but IEEE standards. * And the machine can read Verilog language, it may as EDA tools and languages of the world between the designers* Verilog HDL language to describe capacity through the use of programming language interface (PLI) mechanism further expansion. PLI is to allow external functions of the visit Verilog module information, allowing designers and simulator world Licheng assembly* Design to be described at a number of levels, from the switch level, doors level, register transfer level (RTL) to the algorithm level, including thelevel of process and content* To use embedded switching level of the original language in class switch design integrity modelling* Same language can be used to generate simulated incentive and certification by the designated testing conditions, such as the value of imports of the designated*Verilog HDL simulation to monitor the implementation of certification, the certification process of implementing the simulation can be designed to monitorand demonstrate value. These values can be used to compare with the expectations that are not matched in the case of print news reports.* Acts described in the class, not only in the RTL level Verilog HDL design description, and to describe their level architecture design algorithm level behavioural description* Examples can use doors and modular structure of language in a class structure described* Verilog HDL mixed mode modelling capabilities in the design of a different design in each module can level modelling* Verilog HDL has built-in logic function, such as*Structure of high-level programming languages, such as conditions of expression, and the cycle of expression language, language can be used* To it and can display regular modelling* Provide a powerful document literacy* Language in the specific circumstances of non-certainty that in the simulator, different models can produce different results; For example, describing events in the standard sequence of events is not defined.5、In troduction of DSPToday, DSP is w idely used in the modern techno logy and it has been the key part of many p roducts and p layed more and mo re impo rtant ro le in our daily life.Recent ly, Northw estern Po lytechnica lUniversity Aviation Microelect ronic Center has comp leted the design of digital signal signal p rocesso r co re NDSP25, w h ich is aim ing at TM S320C25 digital signal p rocesso r of Texas Inst rument TM S320 series. By using top 2dow n design flow , NDSP25 is compat ible w ith inst ruct ion and interface t im ing of TM S320C25.Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital signal processors Lane. Digital signal processing is a cover many disciplines applied to many areas and disciplines, refers to the use of computers or specialized processing equipment, the signals in digital form for the collection, conversion, recovery, valuation, enhancement, compression, identification, processing, the signals are compliant form. Digital signal processors for digital signal processing devices, it is accompanied by a digital signal processing to produce. DSP development process is broadly divided into three phases : the 20th century to the 1970s theorythat the 1980s and 1990s for the development of products. Before the emergence of the digital signal processing in the DSP can only rely on microprocessors (MPU) to complete. However, the advantage of lower high-speed real-time processing can not meet the requirements. Therefore, until the 1970s, a talent made based DSP theory and algorithms. With LSI technology development in 1982 was the first recipient of the world gave birth to the DSP chip. Years later, the second generation based on CMOS工艺 DSP chips have emerged. The late1980s, the advent of the third generation of DSP chips. DSP is the fastest-growing 1990s, there have been four successive five-generation and the generation DSP devices. After 20 years of development, the application of DSP products has been extended to people's learning, work and all aspects of life and gradually become electronics products determinants.中文翻译。

Digital-Signal-Processing数字信号处理大学毕业论文英文文献翻译及原文

毕业设计（论文）外文文献翻译文献、资料中文题目：数字信号处理文献、资料英文题目：Digital Signal Processing 文献、资料来源：文献、资料发表（出版）日期：院（部）：专业：班级：姓名：学号：指导教师：翻译日期： 2017.02.14数字信号处理一、导论数字信号处理（DSP）是由一系列的数字或符号来表示这些信号的处理的过程的。

数字信号处理与模拟信号处理属于信号处理领域。

DSP包括子域的音频和语音信号处理，雷达和声纳信号处理，传感器阵列处理，谱估计，统计信号处理，数字图像处理，通信信号处理，生物医学信号处理，地震数据处理等。

由于DSP的目标通常是对连续的真实世界的模拟信号进行测量或滤波，第一步通常是通过使用一个模拟到数字的转换器将信号从模拟信号转化到数字信号。

通常，所需的输出信号却是一个模拟输出信号，因此这就需要一个数字到模拟的转换器。

即使这个过程比模拟处理更复杂的和而且具有离散值，由于数字信号处理的错误检测和校正不易受噪声影响，它的稳定性使得它优于许多模拟信号处理的应用（虽然不是全部）。

DSP算法一直是运行在标准的计算机，被称为数字信号处理器（DSP）的专用处理器或在专用硬件如特殊应用集成电路（ASIC）。

目前有用于数字信号处理的附加技术包括更强大的通用微处理器，现场可编程门阵列（FPGA），数字信号控制器（大多为工业应用，如电机控制）和流处理器和其他相关技术。

在数字信号处理过程中，工程师通常研究数字信号的以下领域：时间域（一维信号），空间域（多维信号），频率域，域和小波域的自相关。

他们选择在哪个领域过程中的一个信号，做一个明智的猜测（或通过尝试不同的可能性）作为该域的最佳代表的信号的本质特征。

从测量装置对样品序列产生一个时间或空间域表示，而离散傅立叶变换产生的频谱的频率域信息。

自相关的定义是互相关的信号本身在不同时间间隔的时间或空间的相关情况。

二、信号采样随着计算机的应用越来越多地使用，数字信号处理的需要也增加了。

翻译文献

数控振荡器来自文献：Digitally Controlled 0scillator IEEE JOURNAL ok SOLID-STATE CIRCUITS. VOL. 24. NO. 6. JUNE 1989译文：摘要本文提出了一种新型的单片集成数控振荡器，这款振荡器的振荡频率的变化范围可以从19.09Hz到超过20MHz的变化，它的分辨率可以达到19.07Hz。

在它的数字控制范围之内是完全线性的。

它拥有一个具有长期稳定的石英晶振，输出的时钟边沿的不确定的标准差小于0.5ns。

电路只需要石英作为外部组件的引用。

它的工作电压为5V，它制作在一个1.5um的双层金属中，利用单晶硅标准CMOS工艺，需要大约4.1mm^2。

一、引言：在许多器件应用中，一个好的时钟发生器，不仅需要一个稳定的频率，而且需要一个比较大的频率变化范围，来配合锁相环的正常工作，良好的频率稳定性通常是通过使用石英参考压控振荡器，特征频率是由不同的反馈路径的相位和石英电容的负载决定的。

然而，这种锁相环的缺点就是，它的频率的变化范围比较小，只有在特征频率百分之一的范围内变化，除此之外，这种锁相环的另一个缺点是，他们通常是非线性电压控制的，在锁相环中，这是很麻烦的。

可变电容的解决方案还有另外一个弊端，它不适合集成在一个正常的CMOS 工艺中。

这种振荡器已经被用于彩色副载波锁定数字电视系统，但是他们的线锁系统的范围是不够的。

在本文中，数控振荡器的提出解决的上述问题。

数控振荡器有一个非常大的频率变化范围（从19.07Hz到超过20MHz），拥有一个长期稳定的石英晶振，它的时钟沿很短，不确定因素小于50ns，振荡器在完全线性的频率范围变化，来完成数字控制。

它的分辨率是19.07Hz，而且是很容易被改善的，这将在后面的叙述中被讨论。

此外，电路是由标准的1.5um CMOS工艺制作而成，这种工艺用于制作超大规模集成电路设计。

二、工作原理：这种振荡器用于产生主时钟信号为所有的数字集成电路在数字2000数字电路系统中。

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毕业设计（论文）外文文献翻译文献、资料英文题目：文献、资料来源：文献、资料发表（出版）日期：院（部）：专业：班级：姓名：学号：指导教师：翻译日期： 2017.02.14英文文献Technology of digital modulation and demodulation plays a important role in digital communication system, the combination of digital communication technology and FPGA is a certainly trend . With the development of software radio, the requirement for technology of modulation and demodulation is higher and higher. This paper starts with studying digital modulation and demodulation theory at first, and analyses basic principle of three kinds of important modulation and demodulation way ( FSK, MSK, GMSK ).The Rohde &Schwarz SME03, Signal Generator, provides AM modulation and External FSK digital modulation required for the development and testing of digital mobile radio receivers.The application of PWM in digital modulation and demodulation for analog communication signals in several modulation modes Research results prove that the design of digital IF modulator and demodulator of Software Radio appeases the capability and requirement of Software Radio.A transfusion speed monitor system is designed based on infrared technology with modulation and demodulation.It's the combination of modulator and demodulator.Time synchronization that is key technology of digital demodulation is cc allied by software.The paper provides the design of hardware of digital IF modulator and demodulator of Software Radio which includes Digital Signal Processor、Micro Control Unit and AD/DA convertor etc.Digital Down/Up Converter(DDC/DUC), modulation and demodulation are discussed in the dissertation as some essencial parts of SDR platform. Two Way Automatic Communication System(TWACS) is a new valuable communication technology for distribution networks,which has special of modulation and demodulation. In this paper, we study the OFDM technology based on 802.16a, realize the baseband modulation and demodulation by using TMS320C6201, and optimize the software module. The paper introduces the principle of QPSK modulation and demodulation, the circuit are also be realized based on FPGA.With the improvement of the technology, especially in the fields such as computer technology , data coding and compress , digital modulation and VLSI, the world electronic information industry enter into the digital era. First, the features of fax communication and the mode of modulation and demodulation aredescribed.In automatic classification of digital modulation signal,computing envelope variance after difference has important meaning to distinguish PSK and FSK signal.The science and technology of space flight.The effect on modulation and demodulation of QPSK via carrier phase noise can not be ignored, and it is difficult to analyze.Digital modulation error parameters, such as error vector magnitude EVM, is important in test and measurement of information system. This paper introduces the technology research progress in the metrology of digital modulation error parameters. First, we point out the basic problems existing in the field, which is about traceability and parameter range of calibration, and describe the relevant research, such as the thinking and technology of the `RF waveform metrology'. Then, we highlight the research progress of our team: 1). The metrology method and system for digital demodulation error parameter based on CW combination, which fits BPSK, QPSK, 8PSK, 16QAM, 64QAM modulation: this method can achieve traceability and error setting ability in a wide range, when standard EvmRms is 1.585%, the expanded uncertainty (k=2) is 0.009%. 2). The metrology method and system for digitaldemodulation error parameter based on analog AM or PM. 3). The metrology method and system for digital demodulation error parameter based on IQ gain imbalance and phase imbalance. 4). The metrology method and system for digital demodulation error parameter based on analog PM in the aspect of GMSK and FSK modulation. 5). The metrology method and system for digital demodulation error parameter based on Baseband waveform design. Based on these methods, our proposal are given as follows: first, establish public metrology standard for digital modulation error parameters; second, develop a new type of instrument "vector signal analyzer calibrator".In this paper, we propose a novel method of chaotic modulation based on the combination of Chaotic Pulse Position Modulation (CPPM) and Chaotic Pulse WidthModulation (CPWM). This combination looks very promising for the improvement of information privacy in chaos-based digital communications. In the CPPM+CPWM method, each pulse is a chaotic symbol which carries binaryinformation of two bits corresponding to its position and width, where the position is determined by the interval between rising edge of the current pulse compared to the previous one and the width is determined by the duration between the rising edge and the falling edge of the same pulse. This offers the increase of bit rate, bandwidth efficiency and privacy in comparison with the method of CPPM. The schemes of Modulation andDemodulation (MoDem) of CPPM+CPWM are proposed, designed and analyzed that based on the conventional schemes of CPPM. The numerical simulation in time domain of the system of CPPM+CPWM MoDem is implemented in Matlab/Simulink.It gives a summary of theoretical and practical studies on the properties of pulse-phase modulation, developed mainly in 1943. The properties of pulse-phasemodulation are studied by means of Fourier transformations. Although some approximations are introduced, the calculations lead to the following definite conclusions: (1) Pulse-phase modulation introduces no amplitude distortion except at sub-multiples of the recurrent frequency. (2) The harmonic distortion, if any, is negligible and this method of modulation can be used for high-quality broadcasting. (3) Pulse-phase modulation is subject to a special type of distortion called ?cross-distortion,? produced by side bands of the recurrent frequency appearing in the signal bandwidth. Curves of the approximate amount of this type of distortion are given, and it is shown that, in practical multi-channel systems, this distortion is negligible, provided that the recurrent pulse frequency is at least double the highest signal frequency to be transmitted, and preferably equal to, or greater than, three times this frequency. This study is followed by considerations on the signal/noise ratio in pulse-phase modulation. Pulse-phasemodulation is compared with amplitude modulation and a formula, giving the improvement in the signal/noise ratio due to pulse-phase modulation, is established by very simple considerations. It is shown that this ratio improves as the frequency bandwidth used in pulse-phase modulation. It is shown how an improvement of 3 db in signal/noise ratio can be obtained by suppressing the noise on the synchronizing pulse, and a practical circuit developed and applied in 1943 by the author is described. Finally, a typical example of pulse technique isgiven. In practical circuits the modulator and demodulator pulses are not perfectly shaped, because of the departure from linearity due to finite time-constants. This introduces harmonic distortion. It is shown how this distortion can be practically elimi- nated by designing circuits so that the time constant is equal at modulationand demodulation.It present a novel technique for digital data modulation and demodulationcalled triangular modulation (TM). The modulation technique was developed primarily to maximize the amount of data sent over a limited bandwidth channel while still maintaining very good noise rejection and signal distortion performance. Themodulation technique involves breaking digital data into a series of parallel words. Each word is then represented by one half period of a triangular waveform whose slope is proportional to the value of the parallel word it represents. Thedemodulation technique for this uniquely defined waveform involves first digitizing the waveform at a higher constant sampling rate. A linear regression algorithm using the method of least squares is then used to compute the slope of the digitized waveform to a very high precision. This process is repeated for each rising and falling edge of the triangular modulated waveform. All encoded data is extracted by precise slope computation since each slope uniquely defines the encoded data word it represents. The ability of the demodulation algorithm to compute the exact slope of the modulated waveform determines how many bits can be represented by the modulated waveform. Transmission channel bandwidth limitations determine the allowable range of slopes used. Several simulations are performed to provide a sample of how the modulation method will perform in various real world environments. The paper also discusses several application areas where themodulation technique will provide superior results over other modulation methods.The theory of constant envelope orthogonal frequency division multiplexing (CE-OFDM) is analyzed in this paper, along with the introduction of the implementation method of CE-OFDM technique. Besides, the modulation and demodulation process is simulated and analyzed. And theresults indicate that CE-OFDM conducts phasemodulation on the basis of OFDM modulation. Thus, FFT/IFFT is implemented in the transmitting and receiving terminals. Furthermore, the method of equalization applied in the demodulation process can optimize system performance. And also, CE-OFDM solves the problem of high peak-to-average power ratio (PAPR) in OFDM, reducing PAPR to 0Db.High efficient modulation technology is a hot research topic. UNB modulation, for its good performance, is paid to more attention. First, the article introduces EBPSK modulation scheme as UNB modulation method, gives its time and frequency domain characteristics and presents its optimized form in the same time, which can lower the sideband power level, while keeping the modulation information un-lost. Then, filter design is discussed about two zero and two pole digital filter, which shows narrower bandwidths and a fast response speed to the EBPSK based UNB modulated signals, although the filter bandwidth is much narrower, the modulationinformation still can be seen after the modulated signals filtered using it. Last, simulation is done about EBPSK based UNB modulation and demodulation, and experimental results show that EBPSK based UNB modulation has high bandwidth efficiency and a good, even better BER performance using the filters.。