数字集成电路分析与设计 第六章答案

CHAPTER 6P6.1. The on-resistance of a unit-sized NMOS device.LINEAR | SATURATIONOn-resistance of a unit-sized NMOS device051015202500.20.40.60.811.2V DSR D SThe average on-resistance is approximately 15kΩ. The expression for the average resistance value between DD V and 2DDV .()()()()()()()()222,,22,2223344V DD DSV DS DD DDDD DDV DDDS DD DS D satD satV V V V V I V I I ON DD ON ON DD GS T CN N DDD sat sat ox GS T R V R R V V VE L V I Wv C V V +++===-+==-P6.2. Since the signal must go around the ring twice for one oscillation, the period is :()()()()()()()()()()()()()()331531517301012.51021100.32727.5103100.3173ps TOT PLH PHL P LOAD N LOAD P N W EQP EQN g eff P N P N t N t t N R C R C N R R C W L L N R R C C W W W W --=+=+=+⎛⎫=+++ ⎪⎝⎭⎛⎫=⨯+⨯+ ⎪⎝⎭=⨯⨯=115.77GHz 173TOTf t ps=== Independent of inverter size.P6.3. SPICE.P6.4. The self-capacitance in these cases are the capacitances that will make the transition from0 to DD V or vice versa.a. In this case, all the internal nodes will be charged so the self-capacitance is :()2233313SELF eff eff C C W W W W W C W =++++=b. In this case, all the internal nodes but the one above the bottom NMOS transistor will be charged:()223310SELF eff eff C C W W W W C W =+++=c. If we assume a worst-case scenario, this node will be charged up to DD V from 0.()2233313SELF eff eff C C W W W W W C W =++++=d. The node above the bottom-most NMOS transistor has already been discharged.()223310SELF eff eff C C W W W W C W =+++=P6.5. SPICEP6.6. For optimum sizing given four inverters.()()()()()()()()()()()()44332214111111120012005.8911200203.895.891203.8934.645.89134.64 5.895.8915.8915.8945.890.525.5OUT NPE LE FO SE LE C C SE LE C C SE LE C C SE LE C C SE D LE FO P SE P =⨯=====⨯===⨯===⨯===⨯====⨯+=+=+=∏∑∑For the number of devices for optimum delay:log log log log log log12005.11log log 4N N SE SE PE SE PE N SE PEPE N SE =======Setting 5N =gives:()()()()()()()()5544332215114.1211200290.634.121290.6370.394.12170.3917.054.12117.05 4.124.1214.1214.1244.120.518.5OUT N SE LE C C SE LE C C SE LE C C SE LE C C SE LE C C SE D LE FO P SE P ===⨯===⨯===⨯===⨯===⨯====⨯+=+=+=∑∑P6.7. Solution for NAND3For the first NAND3, LE=5W/3W=5/3. For the second NAND3, the delay is not the same asthe basic inverter. So use the more general formula:310/25/33nand W R LE WR⨯== Same as the first case.a.For equal rise and fall time, we double the sizes of the transistors which leads to:313LE==b.For the pseudo-NMOS, we must first calculate the currents, which are different forpull-up and pull-down in the case of a pseudo-NMOS.For the case of the pull-up, only the PMOS is charging the output, for equal delays,we double the size of the PMOS and NMOS to obtain:23LE=P6.9.a.53 LE=b.53 LE=c.82,33 R FLE LE==d.4,23R FLE LE==P6.10.a.813RLE st gate =b.523FLE nd gate =()()()()()()()()()()()()()()45343433221411451110002222336.8711000145.656.87145.6535.366.8735.36 6.876.871 6.8716.8746.870.51 1.50.5OUT NN N PE LE FO SE LE C C SE LE C C SE LE C C SE LE C C SE D SE P SE P ⎛⎫⎛⎫=⨯== ⎪⎪⎝⎭⎝⎭===⨯===⨯===⨯===⨯====+=+=++++∏∑∑31=P6.12.()()()()()()()()()()()()()()()6345434332211546410001777833311.5510001173.2111.55173.2112511.5525411.5511.55111.551111.55OUT N N PE LE FO BE SE LE C BE C SE LE C BE C SE LE C BE C SE LE C BE C SE D SE P ⎛⎫⎛⎫⎛⎫=⨯⨯== ⎪⎪⎪⎝⎭⎝⎭⎝⎭===⨯⨯===⨯⨯===⨯⨯===⨯⨯====+∏()()41411.550.51 1.5251.2N SE P =+=++++=∑∑()()()()()()()()()()()635735445712(2)(4)800066730333314.6800011095.814.610951175.114.64512(4175.1500)533533OUT PE LE FO BE SE LE C BE C SE LE C BE C SE PE LE FO BE SE ⎛⎫⎛⎫⎛⎫=⨯⨯== ⎪⎪⎪⎝⎭⎝⎭⎝⎭===⨯⨯===⨯⨯===⎛⎫⎛⎫=⨯⨯=⨯+= ⎪⎪⎝⎭⎝⎭==∏∏()()()()()()()()()()()5343322151117.4712001114.317.54114.32317.517.5117.51117.53(17.5)214.60.51 1.5 2.25288.9NN N LE C BE C SE LE C BE C SE LE C BE C SE D SE P SE P =⨯⨯===⎛⎫⎪⨯⨯⎝⎭===⨯⨯====+=+=++++++=∑∑To minimize the delay, a estimate of the number of needed stages can be performed :log log 6637049.610log log 4SE PE N SE =∴===≈ The additional stages can be implemented as inverters attached at the input.P6.14. Consider the following situations :C LV inC LV outOutput high-to-low Output low-to-highIn the first case, the output is making a transition from high to low. The next inverter (not shown) has the PMOS in the cutoff region and the NMOS in the linear region. In these regions, the input capacitance of the next gate can be computed as follows:PMOS: C GP =C g x 2W x (1/2) NMOS: C GN =C g x WFor the output low-to-high transition, we have the PMOS linear and the NMOS cutoff: PMOS: C GP =C g x 2W NMOS: C GN =C g x W (1/2)Clearly, the second case has a larger total capacitance and hence a larger effective C g .P6.15. For this problem we examine ramp inputs as compared to step inputs. In both cases below,the transistors being driven enter the linear region and experience larger gate capacitances than the step input case. Therefore, C g is always larger for ramp inputs.C LC LV outpositive-going input ramp negative-going input rampV V DDP6.16. The FO4 delay for 0.18um is approximately 75ps. For 0.13um it is 55ps. Therefore, theconstant for the equation is roughly 420ps/um.。