Xilinx网站资源导读(绝对有用)
XilinxISE软件功能简介与IPCore（IP核）
Xilinx ISE软件功能简介与IP Core（IP核）1 Xilinx ISE软件简要介绍Xilinx是全球领先的可编程逻辑完整解决方案的供应商，研发、制造并销售应用范围广泛的高级集成电路、软件设计工具以及定义系统级功能的IP （Intellectual Property）核长期以来一直推动着FPGA技术的发展。
Xilinx的开发工具也在不断升级，集成了FPGA开发需要的所有功能，其主要特点有：①包含了Xilinx新型Smart Compile技术，可以将实现时间缩减2.5倍，能在最短的时间内提供最高的性能，提供了一个功能强大的设计收敛环境；②全面支持最新FPGA系列器件；③集成式的时序收敛环境有助于快速、轻松地识别FPGA设计的瓶颈；④可以节省一个或多个速度等级的成本，并在逻辑设计中实现最低的总成本。
Foundation Series ISE具有界面友好、操作简单的特点，再加上Xilinx的FPGA芯片占有很大的市场，使其成为非常通用的FPGA工具软件。
ISE作为高效的EDA设计工具集合，与第三方软件扬长避短，使软件功能越来越强大，为用户提供了更加丰富的Xilinx平台[19]。
2 Xilinx ISE软件功能简介ISE 的主要功能包括设计输入、综合、仿真、实现和下载，涵盖了FPGA开发的全过程，从功能上讲，其工作流程无需借助任何第三方EDA软件。
设计输入：ISE提供的设计输入工具包括用于HDL代码输入和查看报告的ISE文本编辑器，用于原理图编辑的工具ECS，用于生成IP Core Generator，用于状态机设计的StateCAD以及用于约束文件编辑的Constraint Editor等。
综合：ISE的综合工具不但包含了Xilinx自身提供的综合工具XST，同时还可以内嵌Mentor Graphics公司的LeonardoSpectrum和Synplicity公司的Synplify，实现无缝链接。
XilinxVivadozynq7000入门笔记剖析
IP Integrator flow1.创建RTL工程2.创建IP Integrator Block Design3.添加zynq 处理器ip中搜索zynq，添加zynq7 Processing System，其中的BFM版本为先前的IP处理器版本。
鼠标右键点击FIXED_IO和DDR接口，选择make external，连接到芯片外部。
但此时处理是完全未经过配置的，双击处理器进行配置。
自动添加的外部接口：（参考ug585文档）FIXED_IO, 是专用的内部固化的外设IO，作用？54个MIO口，DDR_VRN,DDR_VRP: DDR DCI voltage reference pins, refer to UG933, Zynq-7000 AP SoC PCB Design and Pin Planning Guide.PS_SRSTB: Debug system reset, active Low. Forces the system to enter a reset sequence.PS_CLK: System reference clockPS_PORB: Power on reset, active lowDDR接口，处理器ddr内存寻址接口；M_AXI_GP0_ACLK,M_AXI_GP0,在PS-PL Configuration中可取消对GP Master AXI Tnterface的选择FCLK_CLK0：PL Pabric Clocks，不使用可在Clock Configuration 中disable。
FCLK_RESET0_N：时钟复位使能，可在General中disable 。
4.配置processing System，配置处理器内部控制模块的详细功能与特性查看：Soc Technical Reference manual/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf通用配置：（1）MIO配置：Bank0与Bank1分区的IO对应FPGA处理器可配置的IO，由硬件决定电平还是芯片已经指定电平？由硬件决定。
Xilinx Notes
7 Series FPGAs Overview参考ds180_7Series_Overview.pdf。
1.General Description7系列包括Artix 7、Kintex 7和Virtex 7。
其中Artix 7面向较低端应用，功耗低，价格低，封装小；Kintex 7面向中端应用，性价比更高，性能约比Artix 7提高2倍；Virtex 7面向高端应用。
采用28nm工艺。
2.Summary of 7 Series FPGA Features●Real 6-input look-up table(LUT) technology configurable as distributed memory.●SelectIO technology with support for DDR3 interfaces up to 1866Mb/s.●600Mb/s to 6.6Gb/s up to 28.05Gb/s.●包括一个用户可配置的ADC（双12位，1MSPS的ADC），芯片内部集成热和电源传感器。
●DSP slices with 25×18 multiplier, 48-bit accumulator, and pre-adder.●Powerful clock management tiles(CMT), combining phase-locked loop(PLL) andmixed-mode clock manager(MMCM) blocks for high precision and low jitter.●支持PCIe的endpoint和root port，支持gen3。
● 1.0V核电压，当需要达到更低的功耗时，可配置0.9V核电压。
3.CLBs, Slices, and LUTs7系列的FPGA可将任意一个查找表配置为6输入查找表（64bit ROM），或配置为2个5输入查找表（32bit ROM）。
Xilinx 入门
Xilinx CPLD 带来了极大的设计优势 了解 CPLD 使用的特性与优势， 有助于简化设计、降低开发成本并加速产品上市进程。 CPLD 优势概览: 简化设计 降低开发成本 实现产品创收增长 缩小板级空间 提高系统可靠性 加速产品上市进程 立即按照下列 4 个简单步骤着手设计： 第 1 步：选择 CPLD 器件 在为设计选择合适的 CPLD 的过程中，需要考虑以下几个方面（其优先次序依设计的不同而不同）： 密度与 I/O 通过将您的设计提交到免费下载的 ISE® WebPACK™ 软件，您可确定您的设计所需要的 Xilinx CPLD 的规模（逻辑密度和 I/O）。 性能 Xilinx CPLD 有多种速度级别，因此您只需购买您所需性能的 CPLD 器件。利用 ISE WebPACK 确定器件的速度级别以满足您系统的 时序要求。 电压和功耗 不同的 Xilinx CPLD 系列具有不同的电压（电源和 I/O）和功耗（静态和动态）要求。 封装 Xilinx CPLD 采用廉价的 QFP 封装、超小型芯片级封装， 以及 I/O 数量较多的 BGA 封装等多种封装形式。 Xilinx CPLD 系列 CoolRunner™ Series Xilinx CoolRunner 系列 CPLD 是业界功耗最低、性能最高 的器件。这些 CPLD 提供了诸如 I/O banking 、高级时钟控制，以及出色 的设计安全性等高级功能来支持系统级设计。 XC9500 系列 提供 5.0V (XC9500 系列) 和 3.3V (XC9500XL 系列) 版本，这些低成本 CPLD 系列产品提供了当今尖端系统设计所需的高性能、丰富 特性集和 灵活性 。 第 2 步：选择软件包 CPLD 和简单的 FGPA 设计 要实现基本的 CPLD 或 FPGA 设计，您需要下载免费的ISE WebPACK 软件工具。 任何 CPLD/ FPGA 设计 除了 ISE WebPACK 软件工具外，Xilinx 还提供了多种软件包，以满足不同的设计要求点击这里来确定最适合您的设计需求的软件包。 第 3 步：实现设计 选好 CPLD 器件并下载了必要的软件后，下一步就是设计的实现。设计实现包括：设计实现包括： 设计输入 对原型进行编程和测试 技术文档 每个 CPLD 产品页面都提供了应用指南、参考设计、开发板、配置工具及其它有用信息的链接，可帮助设计人员快速、轻松地完成设计。 第 4 步：购买 CPLD 有几种购买 Xilinx 解决方案的方法：
精品课件-Xilinx FPGA设计基础-第2章
Hale Waihona Puke 第2章 开发软件与开发流程 图2.13 选择创建新的源文件
(5) 单击图2.6中的Install按钮，开始ISE的安装过程。 安装的过程中，安装界面显示了ISE的一些新特性，安装完成 后，双击桌面的ISE9.1图标就可以打开ISE开发环境界面，如 图2.7所示。
第2章 开发软件与开发流程 图2.7 ISE开发环境界面
第2章 开发软件与开发流程
2.1.3 ModelSim仿真软件简介 ModelSim是Mentor公司开发的一款功能强大的仿真软件，
实验目标： 通过这个实验将学会以下几点：
编写简单门电路的RTL级描述程序； 创建简单电路的结构级VHDL描述程序； 用VHDL语言建立电路的层级描述； 熟悉ISE集成环境； 使用ISE集成环境的HDL编辑器； 熟悉ISE第三方集成的仿真工具ModelSim SE的使用； 熟悉一般项目开发的步骤。
第2章 开发软件与开发流程
第2章 开发软件与开发流程 图2.18 查看原理图
第2章 开发软件与开发流程 图2.19 AND_OR对应的电路图
第2章 开发软件与开发流程
实验过程： (1) 创建一个新的工程，工程命名为“lab1”。 双击桌面的Xilinx ISE图标或者单击“开始→Xilinx ISE 9.1i→Project Navigator”打开ISE开发环境。 在ISE开发环境中单击“File→New Project”，如图 2.10所示，弹出一个建立新工程的对话框，如图2.11所示。 在Project Location框中填写工程文件保存路径；在Project Name框中，填写新建工程的名字“lab1”；在Top-Level Source Type框中选择HDL。然后单击Next按钮。
Xilinx_FPGA中文教程
Xilinx_FPGA中文教程Spartan-3E Starter Kit Board User GuideChapter 1: Introduction and Overview Chapter 2: Switches, Buttons, and Knob Chapter 3: Clock SourcesChapter 4: FPGA Configuration Options Chapter 5: Character LCD ScreenChapter 6: VGA Display PortChapter 7: RS-232 Serial PortsChapter 8: PS/2 Mouse/Keyboard Port Chapter 9: Digital to Analog Converter (DAC) Chapter 10: Analog Capture CircuitChapter 11: Intel StrataFlash Parallel NOR Flash PROM Chapter 12: SPI Serial FlashChapter 13: DDR SDRAMChapter 14: 10/100 Ethernet Physical Layer Interface Chapter 15: Expansion ConnectorsChapter 16: XC2C64A CoolRunner-II CPLDChapter 17: DS2432 1-Wire SHA-1 EEPROMChapter 1：Introduction and OverviewSpartan-3E 入门实验板使设计人员能够即时利用Spartan-3E 系列的完整平台性能。
设备支持设备支持：：Spartan-3E 、CoolRunner-II关键特性关键特性：：Xilinx 器件: Spartan-3E (50万门，XC3S500E-4FG320C), CoolRunner?-II (XC2C64A-5VQ44C)与Platform Flash(XCF04S-VO20C)时钟时钟：：50 MHz 晶体时钟振荡器存储器: 128 Mbit 并行Flash, 16 Mbit SPI Flash, 64 MByte DDR SDRAM连接器与接口: 以太网10/100 Phy, JTAG USB 下载,两个9管脚RS-232串行端口, PS/2类型鼠标/键盘端口, 带按钮的旋转编码器, 四个滑动开关,八个单独的LED 输出, 四个瞬时接触按钮, 100管脚hirose 扩展连接端口与三个6管脚扩展连接器显示器: VGA 显示端口，16 字符- 2 线式 LCD电源电源：：Linear Technologies 电源供电，TPS75003三路电源管理IC 市场: 消费类, 电信/数据通信, 服务器, 存储器应用: 可支持32位的RISC 处理器，可以采用Xilinx 的MicroBlaze 以及PicoBlaze 嵌入式开发系统；支持DDR 接口的应用；支持基于Ethernet 网络的应用；支持大容量I/O 扩展的应用。
5.1.2 时钟资源_Xilinx可编程逻辑器件设计与开发（基础篇）_[共5页]
第5章 Virtex-6系列FPGA130三、多路复用器（MUX）在一个SLICE中，除了包含LUT外，还包含三个多路复用器（F7AMUX、F7BMUX和F8MUX），用户可以将4个函数发生器组合在一起，构成7输入或者8输入的函数。
多于8个输入的函数，可以用多个SLICE实现。
多路复用器F7AMUX、F7BMUX和F8MUX通常和函数发生器或者片上逻辑一起实现多种多路复用器。
可以实现以下几种多路复用器。
∙1个LUT实现4:1多路复用器。
∙2个LUT实现8:1多路复用器。
∙4个LUT实现16:1多路复用器。
四、快速先行进位逻辑（Carry Logic）Virtex-6每个CLB有2条独立的进位链，用于实现快速算术加减运算，它解决了多位宽加法、乘法从最低位向最高位进位的延时问题。
先行进位逻辑有专用的进位通路和进位多路复用器（MUXCY），可用来级联函数发生器（LUT），以实现更宽更复杂的逻辑函数，提高CLB模块的处理速度。
Virtex-6中的进位链是上行进位链，每个SLICE具有4位的高度。
考虑到进位链的上行结构特点，在设计中，要特别注意进位链的长度，因为如果当进位链的长度超出一列时，进位链会导致延时变长很多，影响时序。
五、算术逻辑（MULT_AND）算术逻辑包括一个异或门（XOR）和一个专用与门（MULT_AND），一个异或门可以使一个SLICE实现2位全加操作，专用与门可提高乘法器的效率。
5.1.2 时钟资源为了更好地控制时钟，Virtex-6器件分成若干个时钟区域，最小器件有6个区域，最大器件有18个区域。
每个时钟区域高40个CLB。
在时钟设计中，推荐使用片上专用的时钟资源，不推荐使用本地时钟（如逻辑产生的时钟）。
每个Virtex-6的中间列包含了专门配置引脚（CFG），该列的其余区域为CLB。
其右边排列着一个CMT列。
每个区域（40个CLB高）对应一个CMT。
一个CMT包含2个混合模式时钟管理单元（MMCM），还有32个垂直全局时钟树。
（完整版）XilinxSDK使用教程
（完整版）XilinxSDK使用教程Xilinx SDK使用教程本文参考Xilinx SDK软件内置的教程，打开方法：打开SDK->Help->Cheet Sheets...->Xilinx SDK Tutorials，这里有6篇文档。
本文详细介绍其中的4篇（与Application相关）如何创建一个新的软件应用1.打开SDK，切换到c/c++界面下。
（有两个界面，还有一个是Debug界面，在软件右上角处切换）2.指定一个新的硬件平台项目在SDK开发软件时，需要指定硬件平台。
（如果你打开一个现成的SDK工作空间，这一步可以省略）如果SDK工作空间中没有指定，BSP新建窗口会弹出，询问你硬件平台。
---File > New > Other > Xilinx > Hardware Platform Specification---Next, 显示新的硬件项目对话框。
---设定项目名称，以及由Vivado产生的硬件平台。
---Finish.3.创建一个独立的板级支持包（Board Support Package ）---File > New > Board Support Package,打开对话框。
---指定新项目的名字（已初始一个默认的名称）---从CPU下拉列表中，选择目标处理器---从BSP OS下拉列表中，选择操作系统，默认是standalone(没有操作系统)---Finish.弹出BSP设置对话框---配置参数，生成一个BSP---OK4.创建应用项目---File > New > Application Project---指定项目名称---选择OS---选择目标硬件平台---选择目标处理器---选择编程语言---选择一个现有的BSP，或者新建一个---Next---选择一个模板，生成一个可直接运行的软件工程---Finish如何调试一个软件应用1.配置目标连接如果你想用本地设备，你可以跳过这个步骤。
Xilinx开发工具手册
Xilinx 开发工具手册目录1ISE的介绍和使用 (3)1.1 简介 (3)1.2 软件使用 (4)1.2.1 创建工程 (4)1.2.2 设计输入 (6)1.2.3 引脚分配 (10)1.2.4 仿真 (12)1.2.5 器件编程 (16)2常用第三方EDA工具 (20)2.1 最常用的FPGA仿真工具——ModelSim (20)2.1.1 建立Xilinx器件仿真库 (20)2.1.2在ISE中链接ModelSim (21)2.2 最常用的FPGA仿真工具——Synplify (23)3ISE高级调试工具——ChipScope (25)3.1 简介 (25)3.1.1 ChipScope的安装 (25)3.1.2 ChipScope的软件分类 (26)3.1.3 使用方法 (26)3.2 软件使用 (27)3.2.1生成正确的ChipScope文件 (27)3.2.2正确的配置ChipScope相关选项 (29)3.2.3分析ChipScope信号 (33)Xilinx在可编程逻辑器件市场中雄居领先地位。
本文立足工程实践，介绍了Xilinx的FPGA/CPLD开发工具ISE在进行FPGA设计时的使用方法。
1ISE的介绍和使用1.1 简介使用Xilinx的FPGA时，ISE是必备的设计工具。
ISE可以完成FPGA开发的全部流程，包括设计输入、仿真、综合、布局布线、生成bit文件、配置以及在线调试等，功能非常强大。
ISE是一个集成的开发环境，集成了大量实用工具，包括HDL Editor、IP核生成器CORE Generator System、约束编辑器Constraints Editor、静态时序分析工具Static Timing Analyzer、布局规划工具FloorPlanner、FPGA编辑工具FPGA Editor和功耗分析工具Xpower等，这些工具可以帮助设计人员完成设计任务，或者提高工作效率。
Xilinx手册
Xilinx® Virtex™-5 FXT Evaluation KitUser GuideTable of Contents1.0Introduction (4)1.1Description (4)1.2Board Features (4)1.3Test Files (4)1.4Reference Designs (5)1.5Ordering Information (5)2.0Functional Description (6)2.1Xilinx Virtex-5 FX30T FPGA (6)2.2Memory (6)2.2.1DDR2 SDRAM Interface (7)2.2.2Flash Memory (10)2.3Clock Sources (10)2.4Communication (12)2.4.1.110/100/1000 Ethernet PHY (12)2.4.1.2Universal Serial Bus (USB) to UART Bridge Transceiver (14)2.4.1.3RS232 (14)2.5User Switches (15)2.6User LEDs (16)2.7Configuration and Debug Ports (16)2.7.1Configuration Modes (16)2.7.2System ACE™ Module Connector (17)2.7.3JTAG Port (PC4) (18)2.7.4CPU Debug Port (19)2.7.5CPU Trace Port (19)2.8Power (20)2.8.1FPGA I/O Voltage (Vcco) (20)2.8.2FPGA Reference Voltage (Vref) (21)2.9Expansion Connectors (21)2.9.1EXP Interface (21)3.0Test Designs (24)3.1Factory Test (24)3.2Ethernet Test (24)3.3USB UART Test (24)4.0Revisions (25)Appendix A (26)FiguresFigure 1 - Virtex-5 FXT Evaluation Board Picture (5)Figure 2 - Virtex-5 FXT Evaluation Board Block Diagram (6)Figure 3 - Virtex-5 FXT Evaluation Board Memory Interfaces (7)Figure 4 - DDR2 SDRAM Interface (7)Figure 5 - Clock Nets Connected to Global Clock Inputs (11)Figure 6 - 10/100/1000 Mb/s Ethernet Interface (12)Figure 7 - USB to UART Transceiver Interface (14)Figure 8 - RS232 Interface (15)Figure 9 - SAM Interface (50-pin header) (17)Figure 10 - PC4 JTAG Port Connector (18)Figure 11 - CPU Debug Connector (19)Figure 12 - CPU Trace Connector (19)Figure 13 – Virtex-5 FXT Evaluation Board Power (20)Figure 14 - EXP I/O Voltage Jumpers (21)Figure 15 - Virtex-5 FXT Evaluation Board Placement (26)TablesTable 1 - Ordering Information (5)Table 2 - XC5FX30T Features (6)Table 3 - DDR2 SDRAM Timing Parameters (8)Table 4 - Virtex-5 FXT DDR2 FPGA Pinouts (9)Table 5 - Virtex-5 Flash Memory Pinout (10)Table 6 - On-Board Clock Sources (11)Table 7 - Clock Socket "U12" Pin-out (11)Table 8 - User Clock Input (12)Table 9 - Ethernet PHY Hardware Strapping Options (13)Table 10 - Ethernet PHY Pin Assignments (14)Table 11 - USB to UART Interface FPGA Pin-out (14)Table 12 - RS232 Signals (15)Table 13 - Push-Button Pin Assignments (15)Table 14 - DIP Switch Pin Assignments (16)Table 15 - LED Pin Assignments (16)Table 16 - FPGA Configuration Modes (16)Table 17 - SAM Interface Signals (18)Table 18 - V5FX30T I/O Bank Voltages (20)Table 19 - EXP Connector Signals (22)Table 20 - EXP Connector "JX1" Pin-out (23)1.0 IntroductionThe purpose of this manual is to describe the functionality and contents of the Virtex-5 FXT Evaluation Kit from Avnet Electronics Marketing. This document includes instructions for operating the board, descriptions of the hardware features and explanations of the test code programmed in the on-board flash.1.1 DescriptionThe Virtex-5 FXT Evaluation Kit provides a complete hardware environment for designers to accelerate their time to market.The kit delivers a stable platform to develop and test designs targeted to the advanced Xilinx FPGA family. The installed Virtex-5 FX30T device offers a prototyping environment to effectively demonstrate the enhanced benefits of leading edge Xilinx FPGA solutions. Reference designs are included with the kit to exercise standard peripherals on the development board for a quick start to device familiarization.Features1.2 BoardFPGA— Xilinx Virtex-5 XC5VFX30T-FF665 FPGAI/O Connectors— One EXP general-purpose I/O expansion connectors— One 50-pin 0.1” Header supports Avnet System ACE Module (SAM)— 16-pin 0.1” CPU debug header— Mictor CPU Trace Port— User Clock Inputs via Differential SMA ConnectorsMemory— 64 MB DDR2 SDRAM— 16 MB FLASHCommunication— RS-232 serial port— USB-RS232 Port— 10/100/1000 Ethernet PHYPower— Regulated 3.3V, 2.5V, and 1.0V supply voltages derived from an external 5V supply— DDR2 termination (0.9V) and supply/reference voltage (1.8V) regulator.Configuration— Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration— 16MB Intel BPI FlashFiles1.3 TestThe flash memory on the Virtex-5 FX30T Evaluation Board comes programmed with a factory test design that can be used as base tests for some of the peripherals on the board. The test designs listed below are discussed in Section 3.0. The factory test will test the following interfaces/peripherals:— DDR2 memory— Flash memory— User LEDs— User push-buttonsOther factory test designs for testing the Ethernet and USB-RS232 interfaces are available on the Avnet Design Resource Center web site (/drc).1.4 ReferenceDesignsReference designs that demonstrate some of the potential applications of the board can be downloaded from the Avnet Design Resource Center (/drc). The reference designs include all of the source code and project files necessary to implement the designs. See the PDF document included with each reference design for a complete description of the design and detailed instructions for running a demonstration on the evaluation board. Check the DRC periodically for updates and new designs.Figure 1 - Virtex-5 FXT Evaluation Board Picture1.5 OrderingInformationThe following table lists the development kit part number.Internet link at /drcPart Number HardwareAES-V5FXT-EVL30-G Xilinx Virtex-5 FXT Kit populated with an XC5VFX30T-1 speed grade deviceTable 1 - Ordering Information2.0 Functional DescriptionA high-level block diagram of the Virtex-5 FXT Evaluation board is shown below followed by a brief description of each sub-section.Figure 2 - Virtex-5 FXT Evaluation Board Block Diagram2.1 Xilinx Virtex-5 FX30T FPGAThe Virtex-5 FX30T FPGA features 4 DCMs, 2 PLLs, and 1.25 Gbps LVDS I/O. The following table shows some other main features of the FF676 package.Device Number ofSlices BlockRAM(Kb)DSP48ESlicesXC5VFX30T 5,120 2,448 64Table 2 - XC5FX30T FeaturesPlease refer to the Virtex-5 FX30T Data sheet for a complete detailed summary of all device features.324 of the 360 available I/O on the Virtex-5 FX30T device are used in the design.2.2 MemoryThe Virtex-5 FXT Evaluation Board is populated with both high-speed RAM and non-volatile Flash to support various types of applications. The board has 64 Megabytes (MB) of DDR2 SDRAM and 16 MB of Flash. The following figure shows a high-level block diagram of the memory interfaces on the evaluation board. If additional memory is necessary for development, check the Avnet Design Resource Center (DRC) for the availability of EXP compliant daughter cards with expansion memory (sold separately). Here is the link to the DRC web page: /drc.Figure 3 - Virtex-5 FXT Evaluation Board Memory Interfaces2.2.1 DDR2 SDRAM InterfaceTwo Micron DDR2 SDRAM devices, part number MT47H16M16BG-5E, make up the 32-bit data bus. Each device provides 32MB of memory on a single IC and is organized as 4 Megabits x 16 x 4 banks (256 Megabit). The device has an operating voltage of 1.8V and the interface is JEDEC Standard SSTL_2 (Class I for unidirectional signals, Class II for bidirectional signals). The -5E speed grade supports 5 ns cycle times with a 3 clock read latency (DDR2-400). DDR2 On-Die-Termination (ODT) is also supported. The following figure shows a high-level block diagram of the DDR SDRAM interface on the Virtex-5 FXT Evaluation Board.Figure 4 - DDR2 SDRAM InterfaceThe following table provides timing and other information about the Micron device necessary to implement a DDR2 memory controller.MT47H16M16BG-5E: Timing Parameters Time (ps) orNumberLoad Mode Register time (TMRD) 25000Write Recovery time (TWR) 15000Write-to-Read Command Delay (TWTR) 1Delay between ACT and PRE Commands (TRAS) 90000Delay after ACT before another ACT (TRC) 65000Delay after AUTOREFRESH Command (TRFC) 115000Delay after ACT before READ/WRITE (TRCD) 25000Delay after ACT before another row ACT (TRRD) 15000Delay after PRECHARGE Command (TRP) 20000Refresh Command Interval (TREFC) 115000Avg. Refresh Period (TREFI) 7800000Memory Data Width (DWIDTH) (x2 devices) 32Row Address Width (AWIDTH) 13Column Address Width (COL_AWIDTH) 9Bank Address Width (BANK_AWIDTH) 2Memory Range (64 MB total) 0x3FFFFFFTable 3 - DDR2 SDRAM Timing ParametersThe following guidelines were used in the design of the DDR2 interface to the Virtex-5 FX30T FPGA. These guidelines are based on Micron recommendations and board level simulation.•Dedicated bus with matched trace lengths (+/- 100 mils)•Memory clocks routed differentially•50 ohm* controlled trace impedance•Series termination on bidirectional signals at the memory device•Parallel termination following the memory device connection on all signals•100 ohm* pull-up resistor to the termination supply on each branch of shared signals (control, address)•Termination supply that can source both termination and reference voltages.* Ideal impedance values. Actual may vary.Some of the design considerations were specific to the Virtex-5 architecture. For example, the data strobe signals (DQS) were placed on Clock Capable I/O pins in order to support data capture techniques utilizing the SERDES function of the Virtex-5 I/O blocks. The appropriate DDR2 memory signals were placed in the clock regions that correspond to these particular Clock Capable I/O pins.The DDR2 signals are connected to I/O Banks 11 and 13 of the Virtex-5 FX30T FPGA. The output supply pins (VCCO) for Banks 11 and 13 are connected to 1.8 Volts. This supply rail can be measured at test point TP5, which can be found in the area around the power modules. The reference voltage pins (VREF) for Banks 11 and 13 are connected to the reference output of the Texas Instruments TPS51116 DDR2 Power Solution Regulator. This rail provides the voltage reference necessary for the SSTL_2 I/O standard as well as the termination supply rail. The termination voltage is 0.9 Volts and can be measured at test point TP6.The following table contains the FPGA pin numbers for the DDR2 SDRAM interface.Signal Name Virtex-5 pin Signal Name Virtex-5 pinDDR_A0 U25 DDR_D0 R22DDR_A1 T25 DDR_D1 R23DDR_A2 T24 DDR_D2 P23DDR_A3 T23 DDR_D3 P24DDR_A4 U24 DDR_D4 R25DDR_A5 V24 DDR_D5 P25DDR_A6 Y23 DDR_D6 R26DDR_A7 W23 DDR_D7 P26DDR_A8 AA25 DDR_D8 M26DDR_A9 AB26 DDR_D9 N26DDR_A10 AB25 DDR_D10 K25DDR_A11 AB24 DDR_D11 L24DDR_A12 AA23 DDR_D12 K26DDR_D13J26J25 DDR_D14DDR_BA0 U21 DDR_D15 N21DDR_BA1 V22M21 DDR_D16DDR_CS# AD24 DDR_D17 J23ODT AF24 DDR_D18 H23H22 DDR_D19DDR_WE# AA22 DDR_D20 G22DDR_RAS# Y22 DDR_D21 F22DDR_CAS# W24 DDR_D22 F23DDR_CLKEN T22 DDR_D23 E23G24DM0 U26 DDR_D24F24DM1 N24 DDR_D25G25DM2 M24 DDR_D26DM3 M25 DDR_D27H26G26 DDR_D28DQS0 P,N W26, W25 DDR_D29 F25DQS1 P,N L23, L22 DDR_D30 E25DQS2 P,N K22, K23 DDR_D31 E26DDR2_CLK0 P,N V21, W21DDR2_CLK1 P,N N22, M22Table 4 - Virtex-5 FXT DDR2 FPGA PinoutsMemory2.2.2 FlashThe Virtex-5 FXT Evaluation Board has 16 MB of non-volatile flash memory on board. The flash device is made by Intel,part number: PC28F128P30T85. The flash memory interface utilizes a 16-bit data bus and can be accessed directly without any external hardware settings or jumpers. See the following table for the flash memory to Virtex-5 pinout.Signal Name Virtex-5 Pin Signal Name Virtex-5 PinFLASH_A0 Y11 FLASH_D0 AA15FLASH_A1 H9 FLASH_D1 Y15FLASH_A2 G10 FLASH_D2 W14FLASH_A3 H21 FLASH_D3 Y13FLASH_A4 G20 FLASH_D4 W16FLASH_A5 H11 FLASH_D5 Y16FLASH_A6 G11 FLASH_D6 AA14FLASH_A7 H19 FLASH_D7 AA13FLASH_A8 H18 FLASH_D8 AB12FLASH_A9 G12 FLASH_D9 AC11FLASH_A10 F13 FLASH_D10 AB20FLASH_A11 G19 FLASH_D11 AB21FLASH_A12 F18 FLASH_D12 AB11FLASH_A13 F14 FLASH_D13 AB10FLASH_A14 F15 FLASH_D14 AA20FLASH_A15 F17 FLASH_D15 Y21FLASH_A16 G17FLASH_A17 G14 FLASH_CE# Y12FLASH_A18 H13 FLASH_OE# AA12FLASH_A19 G16 FLASH_WE# AA17FLASH_A20 G15 FLASH_RST# D13FLASH_A21 Y18 FLASH_BYTE# Y17FLASH_A22 AA18 FLASH_WAIT# D16FLASH_A23 Y10 FLASH_ADV# F19FLASH_A24 W11Table 5 - Virtex-5 Flash Memory PinoutSources2.3 ClockThe Virtex-5 FXT Evaluation Board includes all of the necessary clocks on the board to implement designs as well as providing the flexibility for the user to supply their own application specific clocks. The clock sources described in this section are used to derive the required clocks for the memory and communications devices, and the general system clocks for the logic design. This section also provides information on how to supply external user clocks to the FPGA via the on-board connectors and oscillator socket.The following figure shows the clock nets connected to the I/O banks containing the global clock input pins on the Virtex-5 FX30T FPGA. Ten out of the twenty global clock inputs of the Virtex-5 FPGA are utilized on the board as clock resources. The other global clock inputs are used for user I/O. It should be noted that single-ended clock inputs must be connected to the P-side of the pin pair because a direct connection to the global clock tree only exists on this pin. The I/O voltage (VCCO) for Bank 3 is set at 3.3V. Bank 4 is jumper selectable via JP2 to either 2.5V or 3.3V. In order to use the differential clock inputs as LVDS inputs, the VCCO voltage for the corresponding bank must be set for 2.5V since the Virtex-5 FPGA does not support 3.3V differential signaling. Single-ended clock inputs do not have this restriction and may be either 2.5V or 3.3V. The interface clocks and other I/O signals coming from 3.3V devices on the board are level-shifted to the appropriate VCCO voltage by CB3T standard logic devices prior to the Virtex-5 input pins.Figure 5 - Clock Nets Connected to Global Clock InputsThe on-board 100MHz oscillator provides the system clock input to the global clock tree. This single-ended, 100 MHz clock can be used in conjunction with the Virtex-5 Digital Clock Managers (DCMs) to generate the various processor clocks and the clocks forwarded to the DDR SDRAM devices. The interface clocks supplied by the communications devices are derived from dedicated crystal oscillators.Reference# Frequency Derived InterfaceClock Derived Frequency Virtex-5 pin#U11 100 MHz CLK_100MHZ 100 MHz E18 U12 (sckt) User defined User Defined User Defined E13 J2, J5User DefinedUser Defined User Defined AB15. AB16GMII_RX_CLK E20GMII_TX_CLK 2.5, 25, 125 MHzE17 Y125 MHz GBE_MCLK 125 MHz F20Table 6 - On-Board Clock SourcesThe clock socket is an 8-pin DIP clock socket that allows the user to select an oscillator of choice. The socket is a single-ended, LVTTL or LVCMOS compatible clock input to the FPGA that can be used as an alternate source for the system clock.Signal Name Socket pin#Enable 1 GND 4 Output 5 VDD 8 Table 7 - Clock Socket "U12" Pin-outNet Name Input Type Connector.pin# Virtex-5 pin#clock U16.5 E13CLK_SOCKET GlobalTable 8 - User Clock Input2.4 CommunicationThe Virtex-5 FX30T FPGA has access to Ethernet and RS232 physical layer transceivers for communication purposes. Network access is provided by a 10/100/1000 Mb/s Ethernet PHY, which is connected to the Virtex-5 via a standard GMII interface. The PHY connects to the outside world with a standard RJ45 connector (J1) and is located in the upper right corner of the board.A USB compatible RS232 transceiver is available for use as well. The USB Type B peripheral connector (JR1) is mounted on the top right corner of the board. A second, standard DB9 Serial port (P1) to the embedded processor or FPGA fabric is provided through a dual-channel RS232 transceiver.2.4.1 10/100/1000 Ethernet PHYThe PHY is a National DP83865DVH Gig PHYTER® V. The DP83865 is a low power version of National’s Gig PHYTER V with a 1.8V core voltage and 3.3V I/O voltage. The PHY also supports 2.5V I/O, but the 2.5V option is used on the board. The PHY is connected to a Tyco RJ-45 jack with integrated magnetics (part number: 1-6605833-1). The jack also integrates two LEDs and their corresponding resistors as well as several other passive components. External logic is used to logically OR the three link indicators for 10, 100 and 1000 Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the default strap options and may not work if the strap options are changed. Four more LEDs are provided on the board for status indication. These LEDs indicate lnk at 10 Mb/s, link at 100 Mb/s, link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated from its own 25 MHz crystal. The following figure shows a high-level block diagram of the interface to the DP83865 Tri-mode Ethernet PHY.Figure 6 - 10/100/1000 Mb/s Ethernet InterfaceThe PHY address is set to 0b00001 by default. PHY address 0b00000 is reserved for a test mode and should not be used. Three-pad resistor jumpers are used to set the strapping options. These jumper pads provide the user with the ability to change the settings by moving the resistors. The strapping options are shown in the following table. The dual-function pins that are used for both a strapping option and to drive an LED, have a set of two jumpers per pin. The dual-function pins are indicated by an asterisk in the table.Function Jumper InstallationResistorMode EnabledJT4: pins 1-2 JT5: pins 1-2 0 ohm 0 ohm Auto-negotiation enabled (default) Auto-Negotiation*JT4: pins 2-3 JT5: pins 2-3 0 ohm 0 ohm Auto-negotiation disabled JT8: pins 1-2 JT9: pins 1-2 0 ohm 0 ohm Full Duplex (default) Full/Half Duplex*JT8: pins 2-3 JT9: pins 2-30 ohm 0 ohm Half DuplexSpeed 1*JT1: pins 1-2 JT2: pins 1-20 ohm 0 ohmSpeed 0*JT1: pins 1-2 JT2: pins 1-20 ohm 0 ohm Speed Selection: (Auto-Neg enabled) Speed1 Speed0 Speed Advertised1 1 1000BASE-T, 10BASE-T 1 0 1000BASE-T0 1 1000BASE-T, 100BASE-TX0 0 1000BASE-T, 100BASE-TX, 10BASE-TDefault: 1000BASE-T, 100BASE-TX, 10BASE-T JT9: pins 1-2 JT10: pins 1-2 0 ohm 0 ohm PHY Address 0b00001 (default) PHY address 0*JT9: pins 2-3 JT10: pins 2-3 0 ohm 0 ohm PHY Address 0b00000JT6: pins 1-2 Compliant and Non-comp. Operation (default) Non-IEEE Compliant Mode JT6: pins 2-3 1 K 1 K Inhibits Non-compliant operation JT10: pins 1-2 Straight Mode (default) Manual MDIX Setting JT10 pins 2-3 1 K 1 K Cross-over ModeJT11: pins 1-2 Automatic Pair Swap – MDIX (default)Auto MDIX Enable J11: pins 2-3 1 K 1 K Set to manual preset – Manual MDIX Setting (JT12) JT7: pins 1-2 Single node – NIC (default)Multiple Node Enable JT7: pins 2-3 1 K 1 K Multiple node priority – switch/hubJT3: pins 1-2 CLK_TO_MAC output enabled (default) Clock to MAC EnableJT3: pins 2-31 K 1 KCLK_TO_MAC output disabledTable 9 - Ethernet PHY Hardware Strapping OptionsThe default options as indicated in Table 23 are Auto-Negotiation enabled, Full Duplex mode, speed advertised as 10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant and Non-compliant support, straight cable in non-MDIX mode, auto-MDIX mode enabled, Single node (NIC) and CLK_TO_MAC enabled. The pin-out for a jumper pad is shown below.The auto-MDIX mode provides automatic swapping of the differential pairs. This allows the PHY to work with either a straight-through cable or crossover cable. Use a CAT-5e or CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The boundary-scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal operation. This active low reset pin of the TAP (TRST) is pulled low through a 1K resistor on the board. The following table provides the Virtex-5 pin assignments for the Ethernet PHY interface.Net Name Virtex-5 pin Net Name Virtex-5 pin GBE_MDC D26 GBE_INT# C24 GBE_MDIO D25GBE_RST# B26 GBE_MCLK F20 GMII_CRS A25 GMII_GTC_CLK A19 GMII_COL A24 GMII_TXD0 D19 GMII_RXD0 D24 GMII_TXD1 C19 GMII_RXD1 D23 GMII_TXD2 A20 GMII_RXD2 D21 GMII_TXD3 B20 GMII_RXD3 C26 GMII_TXD4 B19 GMII_RXD4 D20 GMII_TXD5 A15 GMII_RXD5 C23 GMII_TXD6 B22 GMII_RXD6 B25 GMII_TXD7 B21 GMII_RXD7 C22 GMII_TX_EN A23 GMII_RX_DV C21 GMII_TX_ER A22 GMII_RX_ER B24 GMII_TX_CLK E17GMII_RX_CLK E20Table 10 - Ethernet PHY Pin Assignments2.4.2 Universal Serial Bus (USB) to UART Bridge TransceiverThe Virtex-5 FXT Evaluation Board utilizes a SiLabs CP2120 USB to UART transceiver to support PC’s that do not support the standard DB9 serial COM port. The diagram below shows how the CP2120 interfaces to the FPGA.CP2102USB ConnectorFigure 7 - USB to UART Transceiver InterfaceSignal Name Virtex-5 PinUSB_RS232_TXD AA19 USB_RS232_RXD AA10 USB_RS232_RST# Y20Table 11 - USB to UART Interface FPGA Pin-out2.4.3 RS232The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This transceiver operates at 3.3V with an internal charge pump to create the RS232 compatible output levels. This level converter supports two channels. The primary channel is used for transmit and receive data (TXD and RXD). The secondary channel may be connected to the FPGA by installing jumpers on “J3” and “J4” for use as CTS and RTS signals. The RS232 console interface is brought out on the DB9 connector labeled “P1”.Figure 8 - RS232 InterfaceA male-to-female serial cable should be used to plug “P1” into a standard PC serial port (male DB9). The following table shows the FPGA pin-out and jumper settings for the RS232 interface.Net Name Description Virtex-5 PinRS232_RXD Received Data, RD K8Data,TD L8RS232_TXD TransmitRS232_RTS Request To Send, RTS N8RS232_CTS Clear To Send, CTS R8Table 12 - RS232 Signals2.5 UserSwitchesFour momentary closure push buttons have been installed on the board and connected to the FPGA. These buttons can be programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low until the switch closure pulls it high (active high signals).Net Name Reference Virtex-5 PinSWITCH_PB1 SW1 AF20SWITCH_PB2 SW2 AE20SWITCH_PB3 SW3 AD19SWITCH_PB4 SW4 AD20Table 13 - Push-Button Pin AssignmentsAn eight-position dipswitch (SPST) has been installed on the board and connected to the FPGA. These switches provide digital inputs to user logic as needed. The signals are pulled low by 1K ohm resistors when the switch is open and tied high to 1.8V when flipped to the ON position.Net Name Reference Virtex-5 PinSWITCH0 SW5 – 0 AD13SWITCH1 SW5 – 1 AE13SWITCH2 SW5 – 2 AF13SWITCH3 SW5 – 3 AD15SWITCH4 SW5 – 4 AD14SWITCH5 SW5 – 5 AF14SWITCH6 SW5 – 6 AE15SWITCH7 SW5 – 7 AF15Table 14 - DIP Switch Pin Assignments2.6 UserLEDsEight discrete LEDs are installed on the board and can be used to display the status of the internal logic. These LEDs are attached as shown below and are lit by forcing the associated FPGA I/O pin to a logic ‘0’ or low and are off when the pin is logic level ‘1’ or high.Net Name Reference Virtex-5 Pin#LED0 D6 AF22LED1 D7 AF23LED2 D8 AF25LED3 D9 AE25LED4 D10 AD25LED5 D11 AE26LED6 D12 AD26LED7 D13 AC26Table 15 - LED Pin Assignments2.7 Configuration and Debug Ports2.7.1 ConfigurationModesThe Virtex-5 FXT Evaluation Board supports three methods of configuring the FPGA. The possible configuration methods include Boundary-scan (JTAG cable), BPI Flash, and the System ACE Module (SAM) header. The Virtex-5 device also supports configuration from BPI Flash. The blue LED labeled “DONE” on the board illuminates to indicate when the FPGA has been successfully configured.JP5 is the mode jumper that is used to tell the FPGA to configure in JTAG mode or Flash BPI mode. In JTAG mode a Xilinx parallel JTAG cable must be used (PC4 or USB). When the jumper is set for BPI mode, the flash must be programmed with a BPI-UP image in order for the FPGA to successfully configure. For configuration from a System ACE Module, the JTAG setting must be used.The Virtex-5 FXT Evaluation Board come pre-programmed with the factory test image in the BPI flash. The table below shows the correct jumper configuration for each configuration mode.ConfigurationModeJP5 PositionJTAG 2-3 System ACE 2-3BPI-UP * 1-2Table 16 - FPGA Configuration Modes*Default assembled state2.7.2 System ACE™ Module ConnectorThe Virtex-5 FXT Evaluation Board provides support for the Avnet System ACE Module (SAM) via the 50-pin connector labeled “JP6” on the board. The SAM can be used to configure the FPGA or to provide bulk Flash to the processor. This interface gives software designers the ability to run real-time operating systems (RTOS) from removable CompactFlash cards. The Avnet System ACE module (DS-KIT-SYSTEMACE) is sold separately. The figure below shows the System ACE Module connected to the header on the Virtex-5 FXT Evaluation Board.JTAG Configuration PortMPUInterfaceReset &ClockPower &GroundMiscSignals Figure 9 - SAM Interface (50-pin header)The following table shows the System ACE ports that are accessible over the SAM header. The majority of the pins on this header may be used as general purpose I/O when not using a System ACE Module. The Virtex-5 pin numbers are provided for these general purpose pins.Virtex-5 PinSystem ACE Signal Name SAM Connector Pin # (JP11) System ACESignal NameVirtex-5 Pin- 3.3V 1 2 3.3V - - JTAG_TDO 3 4 GND - - JTAG_TMS 5 6 SAM_CLK F12 - JTAG_TDI7 8 GND - - FPGA_PROG# 9 10 JTAG_TCK - - GND 11 12 GND - Y6 SAM_OE# 13 14 FPGA_INIT# - Y5 SAM_A0 15 16 SAM_WE# Y4 W6 SAM_A2 17 18 SAM_A1 V7 - 2.5V 19 20 SAM_A3 W5 F5 SAM_D0 21 22 2.5V - V6 SAM_D2 23 24 SAM_D1 U7 U6 SAM_D4 25 26 SAM_D3 U5 T7 SAM_D6 27 28 SAM_D5 T5 R7 SAM_D8 29 30 SAM_D7 R6 P6 SAM_D10 31 32 SAM_D9 R5 N6 SAM_D12 33 34 SAM_D11 P8 K5 SAM_D14 35 36 SAM_D13 M7 K6 SAM_A4 37 38 SAM_D15 L7 J6 SAM_A6 39 40 SAM_A5 J5 H4 SAM_IRQ 41 42 GND - H6 SAM_RESET# 43 44 SAM_CE# G4 - FPGA_DONE 45 46 SAM_BRDY G5 - FPGA_CCLK 47 48 FPGA_D_IN - - GND 49 50 GND -Table 17 - SAM Interface Signals2.7.3JTAG Port (PC4)The Virtex-5 FXT Evaluation Board provides a JTAG port (PC4 type) connector (J9) for configuration of the FPGA. The following figure shows the pin assignments for the PC4 header on this development board.Figure 10 - PC4 JTAG Port Connector2.7.4 CPU Debug PortThe Virtex-5 FXT Evaluation Board provides a CPU Debug header for connection of a debug probe to the integrated PowerPC processor.CPU Debug connector JP4 can be used to download code into the Virtex-5 FXT integrated PowerPC processor. The JTAG port can also be used as the processor debug port. The FPGA general-purpose I/O pins are used for this interface. The following figure shows the CPU Debug Connector.Figure 11 - CPU Debug Connector2.7.5 CPU Trace PortThe Virtex-5 FXT Evaluation Board provides a CPU Trace header for connection of a trace probe to the integrated PowerPC processor. The FPGA general-purpose I/O pins are used for this interface.The processor uses the trace interface when operating in real-time trace-debug mode. Real-time trace-debug mode supports real-time tracing of the instruction stream executed by the processor. In this mode, debug events are used to cause external trigger events. An external trace tool uses the trigger events to control the collection of trace information. The broadcast of trace information on the trace interface occurs independently of external trigger events (trace information is always supplied by the processor). Real-time trace-debug does not affect processor performance. The following figure shows the CPU Trace connector on the Virtex-5 FXT Evaluation Board.NC NC NCNC Mictor_5NCNCNC NCCPU_HALTCPU_TDOCPU_TCK CPU_TMS CPU_TDI CPU_TRST Mictor_23Mictor_25Mictor_27Mictor_29Mictor_31Mictor_33Mictor_35Mictor_37Mictor_16Mictor_18Mictor_20Mictor_22TRACE.TS10TRACE.TS20TRACE.TS1E NCVref (pullup )TRACE.CLK TRACE.TS2E TRACE.TS3TRACE.TS4TRACE.TS5TRACE.TS6Mictor ConnectorFigure 12 - CPU Trace Connector。
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Topics:1. Xilinx软件介绍2. 软件版本和软件更新3. 软件教程哪里找4. 硬件资料5. 参考设计6. 问题解决7.总结1.Xilinx软件介绍用Xilinx的软件做FPGA开发，主要涉及到得软件是Xilinx自家的ISE, EDK, ChipScope Pro, System Generator, PlanAhead 和第三方的ModelSim和Synplify。
ISE是主要的逻辑设计软件，其他软件的具体实现功能都依附于ISE。
ISE有Foundation版和WebPack版。
WebPack版免费，Foundation版收费。
两者的区别是支持的器件不同。
功能是相同的。
WebPack版支持的功能可以看这里：/ise/products/webpack_config.htm。
Foundation当然支持所有功能，功能列表可以在这里找到：/ise/logic_design_prod/foundation.htm。
说这些的目的是，如果开发所使用的器件是WebPack版支持的，那么就从网上下载免费版就好了，不用费劲心机地找Fondation版却用不到他支持的功能。
ChipScope Pro 是片内的逻辑分析仪。
可以让用户方便地抓取片内信号进行debug。
ChipScope支持的Trig方式非常多样，用熟悉了以后几乎是想要观察什么内部信号都可以观察到，即使他有BRAM深度的限制。
/chipscopePlanAhead工具自从ISE7时代被开发出来并发展了这么多年之后，已经成为了提高设计效率和提高产品性能的有力工具。
它可以帮我们在布局布线之前做好管脚定位和DRC检查、规划区域约束、查看综合网表，并且可以跑多次实现，找出最佳的布局并分析时序。
/planaheadEDK - Embedded Development Kit，顾名思义就是用来做嵌入式系统的。
它提供对PowerPC 硬核和MicroBlaze软核的支持，免费提供一些常用的硬件IP Core，比如各种Memory Controller、各种外设如IIC, SPI, GPIO，并集成了GNU工具链，使之成为软硬件设计一体化的设计工具。
设计出的嵌入式系统集标准性与灵活性于一身，可以支持Linux等操作系统，也可让用户自己设计用户IP用作模块接口或硬件加速。
/edkSystem Generator借助Matlab Simulink的框架使DSP算法用图形化的数据流来说明，在Sysgen的帮助下DSP算法可以轻易在FPGA上实现。
特别是它的Hardware Co-simulation功能大大降低了Debug的难度。
/sysgenISE 产品现在被包装为ISE Design Suite 发布。
Suite 分为Logic Edition, Embedded Edtion 和DSP Edition。
每个套装都包含了必要的设计和调试工具。
任何套装都可以从网站上下载30天免费评估版。
/ise_eval/index.htm除了Xilinx的软件，我们通常还会用到一些第三方的软件，比如Synopsys (曾经Synplicity) 的Synplify 综合工具，Mentor Graphic 的ModelSim 工具等。
Synplify 可以替代ISE 自带的XST。
他的优势是编译速度快，编译产生的网表质量可能更高（面积小，频率高）；缺点是1.贵2.对新器件的支持比原厂慢一拍。
ModelSim 是一款常用的仿真工具。
其他和ISE搭配使用的仿真工具有Cadence的NC-Sim 和Synopsys的VCS。
ModelSim根据价格高低和支持功能的多少分为SE, PE, XE 等版本。
其中XE是Xilinx Edition的意思，也就是Xilinx定制版。
ModelSim MX有免费的starter version，也有付费取得License的版本。
ModelSim XE 可以和ISE WebPack 一起下载，安装以后在开始里面点licens_e request就可以申请starter的使用权了。
另外，可以VHDL和Verilog各申请一个，那么就可以仿真两种语言了，不过不支持mix language。
/ise/verification/mxe_details.html不过那一页说的ModelSim XE的use case不准，XE,PE,SE的差别还是仔细看这里吧。
/support/answers/24506.htmModelSim XE自带有Xilinx的仿真库。
如果ISE软件升级，可以从Download Center下载更新的仿真库。
如果使用ModelSim PE/SE，那么就需要使用compxlib工具编译仿真库。
2. 软件版本和软件更新Xilinx的软件工具更新很频繁。
自从IDS10以后，基本是三个月出一次升级包(Service Pack)，一年出一个新版本(Major Version)。
如此高的升级速度，一方面是为了更上新器件的支持要求，一方面是为了修补前期版本的bug。
那么我们是否需要以最快的速度更上更新的速度呢？我的建议通常是：- 正在进行中的项目，如果不是需要新功能或绕过某些已经存在的Bug，那么就不要盲目升级大版本，但是一定要勤快地升级到最新的升级包。
- 新设计尽量用新版本的最稳定版本。
比如现在最近版本是11的时候，还是不要急于追新，用最稳定的10.1.03来做开发。
对于操作系统，建议也是类似的：- 习惯使用Windows的用户还是用Windows XP SP2，最好还是英文版- 公司最好能有一台大内存64位服务器跑RHEL Linux，提供多用户使用，也更适合跑大器件(操作系统支持参考/ise/ossupport/index.htm)所有以上的建议，目的归根到底可以总结为：1. 以最大努力保证设计平台的稳定（Windows XP 用的人最多；Linux的内存管理比Windows好，64位系统上的软件业更成熟）2. 避免陷入已知的Bug中浪费时间3. 减小遇到未知的Bug的可能性在产品开发过程中，设计软件总是稳定比功能多来得重要，操作系统总是稳定比好看来得重要。
Xilinx所有的软件下载都可以在Download Center找到(/download) 。
其内容包括：- IDS的完整版下载- IDS更新包的下载- CAE Vendor Library 就是第三方工具需要使用到的库文件，比如Cadence/Synopsys的综合工具、形式验证工具等。
- ModelSim XE 版本的仿真库更新（记得我们上面说过ModelSim XE不需要自己编译仿真库吗？）- Device Models 可以下载用于第三方仿真工具(HSpice, HyperLinks等)所需要使用的IBIS、HSpice、BSDL模型等。
过往版本的ISE WebPack，可以到ISE Classic页面下载，但是不再提供付费软件的Evaluation。
/tools/classics.htm过往版本的最终Update，也可以在Download Center找到，但是中间版本需要在以下这些Answer Record中查找：/support/answers/10959.htm/support/answers/31741.htm3. 软件教程作为入门教程来说，Xilinx的Free Course视频教程应该是最合适的了。
访问/support/training/free-courses.htm可以找到关于Architecture, Software tools, HDL Coding technique等各方面的视频教程，内容丰富，且原汁原味，属于自我学习最好的参考资料。
放在Demosondemond网站上的那些视频教程的链接现在在主页上找不到了，但是可以从下面的链接进入：/clients/xilinx/001/page/index.asp里面的视频教程内容有关于最新的硬件的，也有各种软件的，也算齐全，只不过不再有新内容更新了。
最近要查看demosondemand网站的录像需要注册了，dod的注册比较严格，注册需要公司邮件地址或者学校带edu的邮件地址。
视频资料还有一类，就是WebCast（网上研讨会录像）。
WebCast不是Tutorial，它最主要不是说明工具怎么用，解释FPGA的具体结构等，而是根据当前的热门问题告诉大家你可以尝试哪些Solution来解决设计问题。
看了WebCast后可以知道我可以再继续读哪方面资料来了解更详细的情况。
Xilinx网站上登录的过往的WebCast：/events/webcasts_od.htm 以前在TechOnline上搞过的WebCast：/electronics_directory/webinar/896最新的WebCast都是可以与演讲者实时互动的。
就像我在这篇文章中提到的，曾经WebCast只在美国开设，时区跟我们有差异，中国用户很难参与到互动环节，但是中国的WebCast也逐渐多起来了。
最新的中文研讨会信息，可以查询/china/company/ch_events.htm。
参加研讨会不仅有机会抽奖得到小礼品，活跃互动者更有可能得到比较丰厚的礼品（看着IPOD就口水~~）。
接下来应该看的是Tutorial。
/support/techsup/tutorials/主要是ISE, EDK, PlanAhead的，还有Timing Constraint的。
ISE做了Tutorial基本操作应该没问题了。
ChipScope比较简单看了Demosondemond的视频教程应该就会了。
还不清楚的话看看安装目录里的UG029。
PlanAhead虽然比ChipScope复杂，但是视频教程还是很不错的，再加上Tutorial，应该也够了。
时序约束的那篇文档算是讲得比较全的，还有可以深入阅读的一篇文档就是wp237，关于offset约束的。
更进阶地了解ISE，需要阅读ISE的Manual。
打开Manual可以从开始菜单中ISE->Documentation->Software Manuals；也可以在开始菜单中的ISE --> Documentation中找到。
列出几个重要的Manual：XST User Guide (xst.pdf)：关于XST的开关选项等Command Tool and Development System Reference Guide (dev.pdf) ：除了XST外的实现工具比如map, par, trce等的实用指南Constraint Guide (cgd.pdf) ：约束的指南。