数字逻辑课程设计

第一题part1： 1. 问题的描述： Using the Xilinx Verilog tools and the Nexys3 board, create and download a circuit that can connect the lower four slide switches to logic functions driving the lower four LEDs, the upper four slide switches directly to the upper four LEDs, and the pushbuttons to the seven-segment display anodes through inverters. The lower four slide switches should use the logic functions: assign LD0 = ~SW0; assign LD1 = SW1 & ~SW2; assign LD3 = SW2 & SW3; assign LD2 = LD1 | LD3; Note that a logic '0' on the seven-segment cathode connection will turn that cathode "on", and likewise, a logic '0' on an anode signal will turn the corresponding anode "on" (i.e., both the anode and cathode signals are active low). After completing the source file to describe the circuit, but before implementing or downloading the design to the Nexys3 bociate the logic signals in your design with physical pins on the FPGA. This association can be created using a “.ucf” file. Guidance and instructions on creating and using a .ucf file can be found in the ISE tutorial, and will be presented during an in-class discussion. 2.verilog语言描述 (1) . module test_sj1(

input wire[7:0]Lw, input wire[3:0]Bn, output wire[7:0]Lk, output wire[3:0]Ag, output wire[6:0]Gf ); assign Lk[0]=~Lw[0]; assign Lk[1]=Lw[1]&~Lw[2]; assign Lk[3]=Lw[2]&Lw[3]; assign Lk[2]=Lk[1]&Lk[3]; assign Lk[4]=Lw[4]; assign Lk[5]=Lw[5]; assign Lk[6]=Lw[6]; assign Lk[7]=Lw[7]; assign Ag[0]=~Bn[0]; assign Ag[1]=~Bn[1]; assign Ag[2]=~Bn[2]; assign Ag[3]=~Bn[3]; assign Gf=7'b0000000; endmodule

(2).测试仿真代码： module test1; // Inputs reg [7:0] Lw; reg [3:0] Bn; // Outputs wire [7:0] Lk; wire [3:0] Ag; wire [6:0] Gf; // Instantiate the Unit Under Test (UUT) project1_1uut ( .Lw(Lw), .Bn(Bn), .Lk(Lk), .Ag(Ag), .Gf(Gf) ); initial begin // Initialize Inputs Lw = 0; Bn = 0; // Wait 100 ns for global reset to finish #100; Lw=8'b00000000; Bn=4'b0000; // Add stimulus here以下写测试代码段 #100; Lw=8'b00000001; #100; Lw=8'b00000010; #100; Lw =8'b00000100; #100; Lw =8'b00001000; #100; Lw =8'b00010000; #100; Lw =8'b00100000; #100; Lw =8'b01000000; #100; Lw =8'b10000000; #100; Bn=4'b0001; #100; Bn=4'b0010; #100; Bn=4'b0100; #100; Bn=4'b1000; end endmodule

3.实验结果截屏：

4.约束文件：

NET "Lw[0]" LOC = "T10"; NET "Lw[1]" LOC = "T9"; NET "Lw[2]" LOC = "V9"; NET "Lw[3]" LOC = "M8"; NET "Lw[4]" LOC = "N8"; NET "Lw[5]" LOC = "U8"; NET "Lw[6]" LOC = "V8"; NET "Lw[7]" LOC = "T5"; NET "Bn[0]" LOC = "C4"; NET "Bn[1]" LOC = "D9"; NET "Bn[2]" LOC = "A8"; NET "Bn[3]" LOC = "C9"; NET "Lk[0]" LOC = "U16"; NET "Lk[1]" LOC = "V16"; NET "Lk[2]" LOC = "U15"; NET "Lk[3]" LOC = "V15"; NET "Lk[4]" LOC = "M11"; NET "Lk[5]" LOC = "N11"; NET "Lk[6]" LOC = "R11"; NET "Lk[7]" LOC = "T11"; NET "Ag[0]" LOC = "N16"; NET "Ag[1]" LOC = "N15"; NET "Ag[2]" LOC = "P18"; NET "Ag[3]" LOC = "P17";

5.实验电路图：

Part2： 1.问题描述： Create a shift register that updates at different frequencies, all less than about 50Hz (so you can see the LEDs blinking) according to the logic values present on SW0, SW1, and SW2. Since the Nexys3 board main clock is 100MHz, this design will require a clock divider to create lower frequencies. A clock divider is one of the more common applications for counters. In this application, a higher frequency clock drives a counter’s clock input, and the counter outputs provide lower frequency signals at 1/2n of the input frequency, where n is the counter output bit number (assuming bit #0 is the LSB). Thus, the LSB of the counter provides a frequency of ½ the input frequency, bit #1 provides 1/4th the input frequency, bit #2 1/8th the frequency, and so on. In most technologies, the output of one flip-flop (such as a counter output bit) can directly drive the clock inputs of other flip-flops. This design will use eight different clock sources, all derived from the same counter-divider. The count range of a 26-bit counter is 0 to 2^26, or about 64 million. The main input clock is 100MHz, so a 26-bit counter running from the main clock will produce a most-significant bit with a frequency of 50/33, or about 1.5Hz. Less significant bits will produce clocks that are ½ of the more significant bit frequencies (so for example, counter bit 25 will be about 3Hz, and bit 24 about 6Hz). One of these eight different clock sources can be selected to drive the clock input to the shift register. The figure below shows an 8:1 mux, with the output directly driving the sift registers clock input. This is a poor design practice, and should not be implemented (in fact, the Xilinx tools will issue a warning). A clock signal to a flip-flop should never come from a combinational logic circuit, because glitches are possible, and because the internal resources of the FPGA are not designed for this use (clocks should only come from clock buffers, or directly from other flip-flops). Rather than the design shown below, a flip-flop should be inserted between the mux and shift register.