ESD Protection Techniques in Deep-Submicron CMOS Technology
0_18_mCMOS1_20分频器电路设计
图 7 五分频电路
2 仿真结果
电路仿真采用 S YNOPS YS 公司的 HSPICE 作 为仿真工具 。输入信号为 2. 5 GHz 的正弦时钟信 号 ,如图 8 所示 ,峰峰值为 0. 2V ,仿真的温度范围为 0 - 70 ℃,仿真的 corner 包括 :ff (fast model) 、tt (typi2 cal model) 、ss(slow model) 。各模块的仿真输出波形 如图 9 - 11 所示 。不同 corner 下的仿真输出波形如 图 12 所示 。从仿真的结果可以看出 ,输入数据在 2. 5 Gb/ s 速率上能够较好地实现时钟的分频 ,整个 电路的功耗约为 9. 8mW 。
1. 2 单元电路设计 1. 2. 1 二分频电路
二分频电路由主从 D 触发器构成 ,其具体电路 如图 3 所示 ,可以看出二分频电路主要由结构相同 的两级锁存器构成 ,即主从锁存器实现分频功能 ,所 以锁存器电路的选择是分频器设计的关键 。
图 3 二分频器原理框图
随着 CMOS 工艺的发展 , MOS 器件的工作速 度越来越高 。虽然采用传统的 CMOS 逻辑也能实 现较高速率的电路 ,但是 CML ( Current Mode Log2 ic) 电路更胜任高速率电路 , CML 电路是电流模式 逻辑电路 ,其基本结构如图 4 所示 ,按其功能可分为 下拉逻辑运算部分 、电流源和负载电阻三个部分 。
图 1 锁相环系统框图
1 电路结构及其设计
1. 1 1∶20 分频器结构设计 本文设计的 1∶20 分频器是将压控振荡器输出
的 2. 5 GHz 时钟信号经 20 分频后输出给鉴频鉴相 器进行鉴相 ,其实现框图如图 2 所示 ,该电路由 2 个 二分频电路 ,1 个五分频电路和 1 个由差分到单端 的转换电路级连构成 。其中二分频电路采用 CML 逻辑实现 ,五分频电路用 CMOS 逻辑实现 。
用于ESD分析的传输线脉冲(TLP)测试--元件级
2015.01.23版
Wei Huang, Jerry Tichenor
Web: Email: info@ Tel: (+1) 573-202-6411 Fax: (+1) 877-641-9358 Address: 4000 Enterprise Drive, Suite 103, Rolla, MO, 65401
我们为何关注ESD？
有物理损伤, 但功能正常- ESD造成的IC损伤
Picture 6
ESD浪涌造成的过电压。IC仍然能工作，但已经接近 彻底损坏。
6
我们为何关注ESD？
硬件故障 - ESD造成的IC损伤
Picture 7
电气过应力(Electrostatic Over Stress - EOS)损坏
Semtech uClamp0541Z 数据表
ESDEMC TLP 测试结果
19
什么是TLP测试？
什么是TLP测试？
• 超快TLP测试: TVS二极管的开启特性 （脉冲开始的几个纳秒）
DUT电阻-时间-脉冲电压瀑布图
6V TLP脉冲
DUT电阻值上限取决于绘图 目的
20
什么是TLP测试？
标准TLP的典型应用
• 带电人体接触受试设备(DUT) • ANSI/ANSI/ESDA/JEDEC JS-001-2010 • 对地测试电压4000V, 电流< 3A (也可用8000V ) • 皮肤放电(IEC 61000-4-2标准是手持金属放电)
Picture 9
对地放电，上升时间(tr) – 2 to 10ns
抗辐照工艺器件ESD性能研究
抗辐照工艺器件ESD性能研究谢儒彬;纪旭明;吴建伟;张庆东;洪根深【摘要】基于抗辐照0.18μm CMOS工艺,研究ESD保护器件GGNMOS结构的ESD性能.为提升电路抗辐照性能,采用薄外延衬底材料且引入场区总剂量加固工艺技术,提升电路的抗单粒子闩锁能力SEL使之大于75MeV,同时令抗总剂量辐射能力达到300krad(Si).在抗辐照工艺开发过程中,发现上述工艺加固措施会对器件抗ESD能力产生较大影响,因此在原有的ESD工艺基础上,对器件结构与ESD工艺进行优化.将优化后GGNMOS器件应用于抗辐照电路的开发当中进行实际验证,结果表明,电路的抗ESD能力大于3000V,满足了抗辐照加固工艺的应用需求.【期刊名称】《微处理机》【年(卷),期】2019(040)003【总页数】6页(P1-6)【关键词】辐射加固;总剂量效应;单粒子效应;ESD技术【作者】谢儒彬;纪旭明;吴建伟;张庆东;洪根深【作者单位】中国电子科技集团公司第五十八研究所,江苏无锡214035;中国电子科技集团公司第五十八研究所,江苏无锡214035;中国电子科技集团公司第五十八研究所,江苏无锡214035;中国电子科技集团公司第五十八研究所,江苏无锡214035;中国电子科技集团公司第五十八研究所,江苏无锡214035【正文语种】中文【中图分类】TN386.11 引言随着半导体技术的不断发展，超大规模集成电路（Very Large Scale Integrated circuit,VLSI）的性能在过去的几十年里提高了5 个量级，集成电路芯片不断向小型化、高密度化和多功能化方向发展，相应地，集成度也不断得到提升，目前的集成电路芯片己具备集成数以亿计的晶体管的能力。
然而与此同时，工艺尺寸的缩小也面临着很多障碍，例如器件与电路的可靠性问题。
在可靠性问题方面，静电放电/静电过应力（ElectrostaticDischarge/Electrical Over Stress,ESD/EOS）则是导致集成电路（Integrated Circuit,IC）失效的主要原因[1]。
esd实验标准
esd实验标准
ESD（Electrical Static Discharge）实验标准通常指的是静电释放的实验标准。
这些标准通常由国际或国内的电气和电子工程师协会（IEEE）或其他相关的行业标准组织制定。
以下是一些常见的ESD实验标准：
1. IEEE Std.1012，也称为ESD Protection for Electrical and Electronic Products，这是最早的一版ESD标准，于1993年发布。
2. IEEE Std.1528，也称为ESD Control of Electrostatics in Cleanrooms and Controlled Environments，这是一套关于洁净室和控制环境中的静电控制的标准。
3. ANSI/ESD S20.20-2007，这是一套关于电子设备和产品的静电保护的设计和测试程序的标准。
4. IEC 61340系列标准，这是一套关于静电防护的整体解决方案的标准。
这些标准通常包含了ESD实验的测试方法、测试设备、测试环境、测试结果的分析等内容。
A 6-μW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology
With forecasting that more SoC will be implemented by ultra-small-scale technologies in the next decade, the impacts, either positive or negative, of the nano-scale technology on the OCL-LDO design cannot be overlooked anymore. Unfortunately, most of the foregoing OCL-LDO designs are not implemented in nano-scale technologies, except one fully-integrated 50-mA LDO design implemented in 90-nm CMOS technology reported in 2005 [3]. This design consumes a quiescent current of 6 mA and is stabilized by a 0.6-nF on-chip capacitor. The load regulation under voltage positioning is 90 mV/50 mA. The performance of this LDO design reveals that the design challenges of OCL-LDO in nano-scale technology are (1) enhancement of loop gain for better load regulation, (2) optimization of quiescent current for power saving, and (3) minimization of on-chip capacitance for chip-area reduction. The recently reported OCL-LDO structures are based on a LDO reported in [3], [7], [10] and [11], as shown in Fig. 1. The core is a flipped voltage follower (FVF) [12]. The stability of this LDO structure has been proven stable under the absence of an off-chip capacitor. However, the large-signal response under the lowcondition limits the transient response, and thus dynamic biasing was proposed in [7] and [11]. When the LDO is implemented in nano-scale technology, both the small-signal and large-signal responses are expected to be significantly improved due to the much smaller parasitic capacitance associated with nano-devices. However, the FVF-based LDO structure itself does not have a high loop gain due to its simple folded circuit structure, even though it is implemented in a submicron CMOS technology. As a result, the reported load regulation is not outstanding. It can be easily predicted that when
GGNMOS
Gate Grounded NMOS器件的ESD性能分析朱科翰∗摘要：本文基于某0.18μm‐CMOS工艺制程的1.8V NMOS器件，从工艺的角度并用TLP测试系统对栅极接地的NMOS（GGNMOS）ESD器件进行比较分析。
介绍了SAB和ESD注入对GGNMOS 的性能影响。
影响GGNMOS ESD性能的瓶颈是均匀开启性。
在GGNMOS版图等其它特征参数最优的前提下，采用SAB能改善其均匀开启性，从而大大改进ESD性能。
GGNMOS的瞬态触发电压在7V左右，不会造成栅氧可靠性威胁，采用PESD并非必需。
1.引言MOS管作为ESD防护器件广泛被业界采用，代工厂给设计公司提供的ESD版图设计规则文档中一般只有MOS管的规范。
随着工艺的进步，MOS管的特征尺寸缩小了、特征频率的增高了，但是使得器件ESD的抵抗能力减弱了。
由此工艺工程师为提高ESD性能，推出了SAB/SB(Salicide Block)，ESD注入（ESD implant）供客户选择，但不是免费的。
GGNMOS作为ESD器件正向依靠寄生NPN（漏极的N+有源区‐P型衬底‐源极的N+有源区）BJT泄放ESD电流；反向由PN二极管（P型衬底‐N+有源区）和栅源相接的NMOS二极管组成。
在全芯片ESD网络中，当ESD事件来临时，GGNMOS正向和反向都有可能导通，这由潜在的ESD路径决定，ESD电流总会流向低阻路径。
所以在设计时必需考虑GGNMOS的正向和反向ESD性能以绝对保证芯片的可靠性。
通常GGNMOS作为二极管ESD性能很强大，但必需结合电源钳位器件（Power Clamp）一起使用，比如电源对输入发生正ESD应力。
GGNMOS作为BJT 是一种击穿型（Breakdown Device）的工作机理[1, 2]，依靠漏极与衬底之间的雪崩击穿触发后形成低阻通路泄放ESD电流。
然而多指GGNMOS器件通常不能如愿以偿的均匀开启，即ESD性能并不与器件的面积成正比。
3.3VCMOS工艺下5V电源轨的ESD箝位电路
收稿日期:2017-09-28 网络出版时间:2018-03-23基金项目:国家自然科学基金资助项目(61474041)作者简介:陈迪平(1962-),男,教授,E -m a i l :c h d p @h n u .e d u .c n .网络出版地址:h t t p://k n s .c n k i .n e t /k c m s /d e t a i l /61.1076.T N.20180323.0855.002.h t m l d o i :10.3969/j.i s s n .1001-2400.2018.05.0163.3VC MO S 工艺下5V 电源轨的E S D 箝位电路陈迪平,董 刚(湖南大学物理与微电子科学学院,湖南长沙410082)摘要:基于传统栅极接地NMO S 静电放电电源箝位结构,针对5V 供电情况,通过电平移位及低漏电流续流措施,实现了3.3VC MO S 集成电路工艺条件下5V 电源轨的新型静电放电箝位电路,避免了高压工艺造成的成本增加.该电路采用分级驱动及分级泄放措施,降低了正常工作时电源箝位电路的漏电流.采用中芯国际0.18μm C MO S 集成电路工艺库模型,仿真验证了电路的正确性;流片结果通过了人体模型ʃ4000V 测试,该电路可成功用于5V 电源轨静电放电保护.关键词:静电放电;保护电路;分级驱动;泄漏电流中图分类号:T N 495 文献标识码:A 文章编号:1001-2400(2018)05-0096-06E S D p o w e r -r a i l c l a m p c i r c u i tw i t ha 5V p o w e r i n t h e 3.3VC M O S p r o c e s sC H E ND i p i n g ,D O N GG a n g(C o l l e g e o fP h y s i c s a n d M i c r o e l e c t r o n i c sS c i e n c e ,H u n a nU n i v .,C h a n gs h a 410082,C h i n a )A b s t r a c t : C o n s i d e r i n g t h e 5V p o w e r s u p p l y ,a n o v e l E S D (e l e c t r o s t a t i c d i s c h a r g e )c i r c u i tw i t h a 5V p o w e r r a i l b a s e do n a c o n v e n t i o n a lG G -NMO S (G a t e -G r o u n dNMO S )E S D p o w e r -r a i l c l a m p c i r c u i t i s d e s i g n e db y t h em e t h o do f l e v e l s h i f t e r s a n dt h e l o wf o l l o wc u r r e n t i nt h e3.3V C MO S p r o c e s s t oa v o i dah i gh e r c o s t u n d e r t h eh i g h -v o l t a g e p r o c e s s .D u e t o p r o g r e s s i v e l y d r i v i n g a n d r e l e a s i n g s t e p s o f t h e o p t i m i z e d c i r c u i t ,t h e l e a k a g e c u r r e n t i s d e c r e a s e d i na r e g u l a r o pe r a t i o n .M o r e o v e r ,t h e c i r c u i t i s v e r if i e dw i t hs i m u l a t i o n sb a s e d o nm o d e l si nt h eS M I C s0.18μm C MO S p r o c e s st e c h n o l og y l i b r a r y a n dth ef a b ri c a t e d E S D p o w e r -r a i l c l a m p c i r c u i th a s p a s s e dt h e H B M (H u m a n B o d y Mo d e l )E S Dt e s ta t ʃ4000V.T h ec i r c u i t sc a nb e s u c c e s s f u l l y u s e d f o r t h e 5V p o w e r r a i l E S D p r o t e c t i o n .K e y W o r d s : e l e c t r o -s t a t i c d i s c h a r g e ;p r o t e c t i o n c i r c u i t s ;h i e r a r c h i c a l d r i v e r ;l e a k a g e c u r r e n t 随着互补金属氧化物半导体(C o m p l e m e n t a r y M e t a l -O x i d e -S e m i c o n d u c t o r ,C MO S )集成电路工艺发展到深亚微米阶段,静电放电(E l e c t r o S t a t i cD i s c h a r g e ,E S D )保护在可靠性设计方面愈加重要[1].为了准确评估芯片的鲁棒性,在实际测试中创建了不同模型模拟可能存在的威胁形式,主要分为:人体模型(H u m a n B o d y M o d e l ,H B M )㊁机器模型(M a c h i n e M o d e l ,MM )和充电器件模型(C h a r g i n g D e v i c e M o d e l ,C D M )[2].一般民用芯片人体模型耐压标准为2k V ,测试电压抬升率为2k V /10n s .美军军标M I L -S T D -883J /m e t h o d 3015.9规定了军用芯片标准,耐压为4k V ,测试电压抬升率为4k V /10n s [3].全芯片静电放电防护电路分为电源轨静电放电箝位电路和I /O 端口静电放电箝位电路[4].目前,用于I /O 端口的静电放电防护技术已较为成熟.受限于应用场合的特殊性及工艺限制,适于电源轨到地的静电放电箝位电路往往存在触发电压高㊁开启速度慢以及自身易损坏等缺点[5].文献[6]采用0.18μm C MO S 标准工艺,通过对传统静电放电电源箝位电路改进,提出了一种动态侦测防护电路,具有漏电流低的优点;文献2018年10月第45卷 第5期 西安电子科技大学学报(自然科学版)J O UR N A L O F X I D I A N U N I V E R S I T Y O c t .2018V o l .45 N o .5h t t p ://w w w.x d x b .n e t[7]采用0.18μm C MO S 标准工艺,基于传统接地N 沟道金属氧化物半导体(G a t e -G r o u n dN -c h a n n e lM e t a l O x i d eS e m i c o n d u c t o r ,G G -NMO S )结构,提出了一款正常工作电压为3.3V 的静电放电电源箝位电路,具有耐压值高的优点.受工艺限制,上述文献中的设计均不适于5V 电源轨的静电放电箝位保护.对于通用串行总线(U n i v e r s a l S e r i a lB u s ,U S B )等5V 供电情况,利用0.18μm C MO S 标准工艺实现时,需专门设计适于5V 电源轨的静电放电箝位电路和低压差稳压器(L o w D r o p O u t r e g u l a t o r ,L D O )电路.基于此,笔者折中考虑了电源电压㊁工艺㊁耐压值及面积等,从整体静电放电电源轨防护网络[8]出发,利用0.18μm 3.3V C MO S 工艺,通过采用电平移位及低漏电流续流措施,实现了一款适于5V 电源轨的新型静电放电箝位电路,避免了高压工艺造成的成本增加.该电路利用分级驱动措施避免了泄放电路误触发,同时加强了对泄放管的驱动能力,正常工作时关断更彻底,减小了泄放通路的漏电流.1 传统静电放电电源箝位电路1.1 静电放电电源防护简介静电放电是一个瞬态大电流事件,特点是放电电流大㊁速度快.静电放电防护电路设计的目的是在静电放电事件发生时,确保芯片引脚电压有适当的箝位措施,避免静电放电事件对芯片内部电路造成损坏.在设计中,静电放电防护分为器件级防护㊁电路级防护和系统级防护.静电放电电路级防护在保护内部电路的同时,需保证器件本身的鲁棒性,以确保芯片可靠地运行.在高电压脉冲作用下,静电放电电源箝位电路将电源轨电压箝位,避免电压过载而导致内部电路受损,同时其具备足够的电流泄放能力,吸收静电放电事件引起的瞬态大电流.静电放电防护电路在正常工作时需具备高稳定性,保证关闭;在静电放电事件发生时,能迅速响应.静电放电电源箝位电路用于基于电源轨的静电放电系统级防护网络设计和基于P A D 的静电放电系统级防护网络设计,位于电源轨之间,能及时消除电源总线和P A D 高电压脉冲对内部电路的影响[9],有效地实现不同放电模式下全芯片静电放电防护.1.2 传统静电放电电源箝位电路早期静电放电电源防护电路多采用G G -NMO S 结构,通过大尺寸的栅极接地NMO S 管实现电源轨间静电放电脉冲泄放,金属氧化物半导体(M e t a lO x i d eS e m i c o n d u c t o r ,MO S )管栅极㊁源极和衬底同时接地,漏区作为阳极接V D D ,开启电压为漏区和衬底间P N 结的反向击穿电压,漏源电压被箝位于寄生双极晶体管(B i p o l a r J u n c t i o nT r a n s i s t o r ,B J T )回扫电压点上,实现对内部电路的保护.但其存在触发电压高㊁保护能力弱以及G G -NMO S 管工艺特殊/不采用最小间距设计规则等缺点.图1 改进型G G -NMO S 电路实例基于上述不足,目前常用改进型G G -NMO S 静电放电电源箝位结构.较传统结构,加入了静电放电事件动态检测电路,以控制泄放通路通断.因泄放管是由栅极控制导通而非雪崩击穿导通,导通电压较低,能够对静电放电事件迅速响应.图1所示为典型的改进型G G -NMO S静电放电电源箝位电路,其中电阻R 和MO S 电容M 1构成动态检测电路,控制泄放管M 4的导通或关断.图1所示电路的H S p i c e 仿真波形如图2所示.图2(a )对于静电放电脉冲,节点A 电压不能及时跟随电源轨静电放电脉冲的变化,正静电放电脉冲使M 2导通,在保证M 2导通能力强于M 3的情况下,V B 上升,致使M 4导通,静电放电泄放通路打开,完成静电放电脉冲泄放;图2(b )是正常工作时,A 点电压有充足的时间上升,使B 点电压为低,泄放通路关闭,不影响电路正常工作.在U S B 等5V 供电场合,为避免高压工艺所造成的成本增加,采用0.18μm C MO S 标准工艺实现时,因工艺限制,器件正常工作电压多为1.8V 和3.3V ,图1所示结构不适于5V 电源轨的静电放电箝位防护.基于此,笔者在传统静电放电电源箝位电路的基础上,采用电平移位以及低漏电流续流措施完成了一种适于5V 电源轨的静电放电箝位电路设计,同时利用分级驱动强化了正常上电时泄放通路的关闭程度,降低了该电路正常工作时的漏电流,可靠地实现了0.18μm C MO S 标准工艺下5V 电源轨的静电放电箝位设计.79第5期 陈迪平等:3.3VC MO S 工艺下5V 电源轨的E S D 箝位电路h t t p ://w w w.x d x b .n et图2 改进型G G -NMO S 电源箝位电路的瞬态响应2 3.3VC M O S 工艺下5V 电源轨的静电放电箝位电路2.1 电路设计基于工艺限制以及上述电路的不足,笔者设计了一种适于3.3V C MO S 工艺的5V 电源轨静电放电箝位电路,如图3所示.设计分为5个部分:电平移位单元㊁低漏续流单元㊁R C 触发电路㊁分级驱动单元以及静电放电泄放单元.图3 3.3VC MO S 集成电路工艺下5V 电源轨的静电放电箝位电路正常上电响应:MO S 电容M 10两端电压V B 逐渐抬升;当上电完成后,V B 为高电平,经分级驱动单元对B 点电压波形整形,分级驱动单元输出可靠的逻辑低电平(地电位),使M 18关闭,切断了泄放支路漏电流通路.在设计中:(1)工作于亚阈值区的电平移位单元M 1~M 4.完成V D D 5(5V )到3V 左右的电平移位(一般地,亚阈值工作区MO S 场效管过驱动电压约为-100m V ,考虑到实际工艺下P 沟道金属氧化物半导体(P -c h a n n e l M e t a lO x i d eS e m i c o n d u c t o r ,P MO S )阈值电压约为-600m V ,故采用四管予以实现),以确保正常工作时,3.3V 工艺晶体管长期可靠地工作.据文献[10],亚阈值系数为C =I [D I 0(W /L ]) ,(1)其中,I D 为晶体管漏极电流;I 0=2n μC o x V 2T ,是一个只由工艺决定的电流值;W 为MO S 场效管的沟道宽度;L 为MO S 场效管的沟道长度.当C >10时,晶体管工作于强反型区;当C =1时,介于亚阈值区和强反型区的过渡区;当C <0.1时,工作于亚阈值区.施加适当偏置,可确定晶体管工作区域.(2)低漏续流单元M 5~M 8.在电路正常上电时,为电平移位单元提供适当的亚阈值电流.亚阈值区晶体管漏极电流ID 与柵源电压V G S 的近似关系为[11]89 西安电子科技大学学报(自然科学版) 第45卷h t t p ://w w w.x d x b .n e tI D =2n μC o x æèçöø÷W L V 2T e x p V G S -V T H n V æèçöø÷T ,(2)其中,V T =K T /q ,为温度电压;n =1+C d e p Co x ;C o x =ε0εr t o x ,为栅氧化层单位面积电容,ε0为真空介电常数,εr 为栅介质材料相对介电常数,t o x 为栅氧化层厚度;C d e p 为单位面积沟道耗尽层电容;μ为载流子表面迁移率;V T H 为阈值电压.据式(1)和式(2),M 5~M 8采用大比值倒比管实现,以降低正常电源电压下的漏电流.(3)分级驱动单元.完成对泄放管M 18的驱动电压波形整形,产生驱动逻辑电平,使得M 18迅速彻底地关断,降低泄放通路的漏电流.为降低正常上电过程中以及稳态时的漏电流,设计中,M 11和M 16采用长沟道晶体管予以实现.正静电放电脉冲响应:当电源正常工作时,泄放管M 17导通,起分压作用,正脉冲通过电平移位单元M 1~M 4迅速耦合到节点A .由于R C 延迟以及分级驱动单元延迟作用,M 15对正脉冲的响应快于对节点B 电位变化的响应,正脉冲使M 15导通并迅速传输到节点C ,致使泄放管M 18导通,泄放通路形成.为确保泄放通路的响应速度,电平移位单元及晶体管M 15均采用较大的宽长比予以实现,以保证静电放电事件到来时,泄放通路迅速彻底地导通.当电源未上电时,因电平移位单元M 1~M 4的响应速度过慢,采用MO S 电容M 19和M 20,迅速将正静电放电脉冲耦合到节点A 和节点C,以确保泄放通路及时可靠地导通.此举亦有助于正常上电时,静电放电电源箝位电路对正静电放电脉冲的响应.为确保泄放通路电流容量充足,静电放电泄放单元采用大的宽长比予以实现.负静电放电脉冲响应:在负静电放电脉冲作用下,晶体管M 17的漏区 衬底二极管正向导通,形成有效的泄放通路.在设计中,M 17采用宽沟道管予以实现,以确保充足的电流容量,实现对内部电路的保护.此外,负脉冲会通过电平移位单元以及MO S 电容M 19㊁M 20耦合到节点A 和节点C ,在脉冲到来时,该电路形成M 17栅极 P MO S 电阻(M 5) M 6漏极(N ) M 6衬底(P ) A V S S (地)的有效泄放通路,以避免M 17的栅氧化层被击穿.同理,可形成M 18栅极 M 16漏区(N ) M 16衬底(P ) A V S S (地)的有效泄放通路,以避免泄放管M 18的栅氧化层被击穿.文献[12]中提出,测试系统引入的电源轨残留电荷会影响静电放电箝位电路正常工作,导致泄放通路MO S 场效管电压回滞先于R C 触发单元响应而开启.笔者利用二极管D 1消除电源轨残留电荷引起的MO S 场效管回滞电压响应的偏移.在回滞电压响应存在偏移时,正静电放电脉冲作用下D 1反向击穿,负静电放电脉冲作用下D 1正向导通.此举在泄放通道因偏移而未开启的情况下,实现对内部电路保护,避免电源轨残留电荷造成静电放电电源箝位功能失效.相对于多晶硅电阻,P MO S 电阻响应更快,因此笔者采用P MOS 电阻代替多晶硅电阻,以提高电路的灵敏度,此举亦有利于减小芯片的面积.一般地,静电放电事件上升时间约为2~10n s ,持续时间约为150n s ;正常快上电时间约为100μs ,慢上电时间约为1m s .考虑分级驱动单元反相器延时,在设计及仿真模型搭建中,R C 时间常数介于0.5~50μs 之间,以确保电路在正常工作及静电放电事件作用下工作合理.图4 静电放电电源箝位电路版图设计2.2 仿真分析静电放电电源箝位电路版图设计如图4中虚线区域所示.C MO S 集成电路中器件隔离主要由反偏P N 结实现.当负静电放电脉冲放电时,电路中反向隔离的P N 结处于正向偏置,具备很强的泄放能力.因此,在电路设计中主要考虑正静电放电脉冲放电的情况.设计采用H S p i c e 仿真工具,基于S M I C 0.18μm C MO S 工艺库模型,对笔者设计的静电放电电源箝位电路进行了仿真分析.用上升时间为10n s ㊁脉宽为150n s ㊁幅度为0~10V 的方波脉冲模拟静电放电电压.笔者设计的静电放电电源箝位电路中各节点的电压波形如图5(a )所示.正静电放电脉冲作用下,节点A 和节点C 电位迅速上升并超过5V ,使得泄放晶体管打开,形成有效的泄放通路,实现对静电放电脉冲的泄放.用上升时间为100μs ㊁幅度为0~5V 的分段线性电压源模拟电源正常上电的情况,仿真结果如图5(b )所示.当电源电压正常工作时,V A 和V B 约为2.8V ,保证了静电放电电源箝位电路所有器件99第5期 陈迪平等:3.3VC MO S 工艺下5V 电源轨的E S D 箝位电路h t t p ://w w w.x d x b .n e t的正常工作.V C 为地电位,使M 18关断,有效地切断了泄放通路,降低了漏电流.比较图2,图5所示结构在保证静电放电事件和正常上电情况下,在保证电源轨箝位保护电路的正确性和有效性的同时,确保了电路核心节点的电压低于工艺要求,验证了该电路的可靠性.由此可见,笔者所设计的新型5V 电源轨静电放电箝位电路可靠地实现了3.3V C MO S 工艺下,5V 电源轨静电放电箝位防护,并通过H S p i c e 仿真验证了笔者设计的静电放电电源箝位电路的正确性和有效性.图5笔者设计的静电放电电源箝位电路响应波形图6 T L P 测试结果3 测试结果为验证上述5V 电源轨静电放电箝位电路的性能,利用中芯国际集成电路制造(上海)公司(S e m i c o n d u c t o r M a n u f a c t u r i n g In t e r n a t i o n a l C o r p o r a t i o n ,S M I C )0.18μm C MO S 工艺对该电路进行了流片.流片后的整体芯片可正常工作,笔者设计的静电放电电源箝位电路不影响整体芯片的正常工作.图6所示为该电路在传输线脉冲(T r a n s m i s s i o nL i n eP u l s e,T L P )测试平台测得的曲线,其二次击穿电流I t 2约为5.2A ,正常工作时泄漏电流约为28μA.较整体芯片而言,正常工作时该电路静态功耗影响较低,满足设计要求;基于人体模型静电放电标准M I L -S T D -883J /M e t h o d3015.9,对流片后的芯片样品进行测试,结果如表1所示.测试结果表明,笔者设计的静电放电电源箝位电路达到静电敏感等级C l a s s -3A 级,即达到设计要求,适于民用芯片静电放电防护设计.表1 静电放电测试结果测试条件引脚组合样品数灵敏度/V 测试模型:人体模型灵敏度:ʃ4000V静电敏感等级:C l a s s -3A 标准:M I L -S T D -883J /M e t h o d3015.9所有引脚到G N D (+)3+4000所有引脚到G N D (-)3-4000所有引脚到V D D 5(+)3+4000所有引脚到V D D 5(-)3-4000所有引脚到A V D D 33(+)3+4000所有引脚到A V D D 33(-)3-4000所有引脚到A V D D 18(+)3+4000所有引脚到A V D D 18(-)3-4000所有引脚到V D D I O (+)3+4000所有引脚到V D D I O (-)3-4000I O 引脚到I O 引脚(+)3+4000I O 引脚到I O 引脚(-)3-40004 结束语通过对传统静电放电电源箝位电路的结构和工作原理分析,针对其不足及工艺限制,笔者设计了一种适01 西安电子科技大学学报(自然科学版) 第45卷h t t p ://w w w.x d x b .n e t 于3.3V C MO S 工艺的5V 电源轨静电放电箝位电路.基于S M I C 0.18μm C MO S 工艺库模型,使用H S p i c e 工具仿真验证了该电路的正确性.笔者设计的静电放电箝位电路已在一款自主芯片中实际应用.设计采用0.18μmC MO S 工艺下的普通器件,降低了电路成本.流片结果通过了人体模型ʃ4000V 测试,达到静电敏感等级C l a s s -3A 级,满足设计要求.参考文献:[1]L U G Y,WA N G Y,C A OJ ,e t a l .A N o v e lL o w -l e a k a g eP o w e r -r a i lE S D C l a m p C i r c u i tw i t h A d j u s t a b l eT r i g g e r i n g V o l t a g ea n d S u p e r i o r F a l s e -t r i g g e r i n g I mm u n i t y f o r N a n o s c a l e A p p l i c a t i o n s [C ]//P r o c e e d i n g s o ft h e 2016I E E E I n t e r n a t i o n a l S y m p o s i u mo nC i r c u i t s a n dS y s t e m s .P i s c a t a w a y :I E E E ,2016:265-268.[2]S A L MA N A A,F A R B I ZF ,A P P A S WAMY A.S t a t e -o f -t h e -a r tE S DP r o t e c t i o nD e v i c e s a n dT e c h n i q u e s f o rD i g i t a l a n d A n a l o g T e c h n o l o g i e s [C ]//P r o c e e d i n g s o f t h e 2016S o i -3d -S ub t h r e s h o l dM ic r o e l e c t r o n i c sT e c h n o l o g y U n i f i e dC o n f e r e n c e .P i s c a t a w a y:I E E E ,2016:7804383.[3]D E P A R TM E N T O FD E F E N S E O F U S A.M I L -S T D -883J M e t h o d3015.9[S ].W a s h i n g t o n :D e pa r t m e n to fD e f e n s eo f U S A,2013.[4]L I O UJC ,L I N W D.I n t e g r a t e d M u l t i -l e v e l C MO SE l e c t r o s t a t i cD i s c h a r g e (M L C -E S D )P r o t e c t i o n M e d i c a lU l t r a s o u n d C h i p S y s t e m [C ]//P r o c e e d i n g s o ft h e 20163r d I n t e r n a t i o n a l C o n f e r e n c e o n G r e e n T e c h n o l o g y an d S u s t a i n a b l e D e v e l o p m e n t .W a s h i n g t o n :I E E EC o m p u t e r S o c i e t y ,2016:78-81.[5]王怡飞,白雪飞,郭立.一种C MO S I C 片上电源E S D 保护电路[J ].电子器件,2008,31(6):1780-1782.WA N G Y i f e i ,B A IX u e f e i ,G U O L i .P o w e r S y s t e m E S DP r o t e c t i o nC i r c u i tD e s i g n i nC MO S I C [J ].C h i n e s e J o u r n a l o f E l e c t i o nD e v i c e s ,2008,31(6):1780-1782.[6]刘红侠,刘青山.0.18μm C MO S 工艺下的新型E S D 保护电路设计[J ].西安电子科技大学学报,2009,36(5):867-870.L I U H o n g x i a ,L I U Q i n g s h a n .A n a l y s i sa n d D e s i g no fN o v e lE S D P r o t e c t i o nC i r c u i t i n0.18μm C MO SP r o c e s s [J ].J o u r n a l o fX i d i a nU n i v e r s i t y ,2009,36(5):867-870.[7]L I ZG,Y U ESG,S U N YS .G D NMO SD e s i g n f o rE S DP r o t e c t i o n i nS u b m i c r o nC MO SV L S I [C ]//P r o c e e d i n gs o f t h e 20091s t A s i aP a c i f i cC o n f e r e n c eo n P o s t g r a d u a t e R e s e a r c hi n M i c r o e l e c t r o n i c sa n d E l e c t r o n i c s .P i s c a t a w a y:I E E E ,2009:432-435.[8]C A OJ ,Y EZ ,WA N G Y,e t a l .A L o w -l e a k a g eP o w e rC l a m p E S D P r o t e c t i o nC i r c u i tw i t hP r o l o n g e dE S D D i s c h a r g e T i m e a n d C o m p a c tD e t e c t i o n N e t w o r k [C ]//P r o c e e d i n gso ft h e2015I E E E 11t hI n t e r n a t i o n a lC o n f e r e n c eo n A S I C .P i s c a t a w a y :I E E E ,2015:7516982.[9]L E EJH,I Y E RN M,J A I NR,e t a l .N e wV o l t a g eC o n t r o l l e dD i o d e f o r P o w e rR a i l a n dR e gu l a t o r E S DP r o t e c t i o n [C ]//P r o c e e d i n g s o f t h e 2017I E E EI n t e r n a t i o n a lR e l i a b i l i t y P h y s i c sS y m p o s i u m.P i s c a t a w a y :I E E E ,2017:7936299.[10]B I N K L E Y D M,HO P P E R C E ,T U C K E RSD,e ta l .A C A D M e t h o d o l o g y f o rO p t i m i z i n g Tr a n s i s t o rC u r r e n ta n d S i z i n g i nA n a l o g C MO SD e s i g n [J ].I E E E T r a n s a c t i o n so nC o m p u t e r -A i d e dD e s i g no f I n t e g r a t e dC i r c u i t sa n dS y s t e m s ,2003,22(2):225-237.[11]F A R Z E E NS ,R E N GY,C H E NC H.A nU l t r a -l o wP o w e rR i n g O s c i l l a t o r f o r P a s s i v eUH FR F I DT r a n s p o n d e r s [C ]//P r o c e e d i n g s o f t h e2010I E E EI n t e r n a t i o n a l53r d M i d w e s tS y m p o s i u m o n C i r c u i t sa n dS y s t e m s .P i s c a t a w a y:I E E E ,2010:558-561.[12]A S H T O N R A,W E I RBE ,W E I S SG,e t a l .V o l t a g e sb e f o r e a n da f t e rH B M S t r e s s a n dT h e i rE f f e c t o nD y n a m i c a l l yT r i g g e r e dP o w e r S u p p l y C l a m p s [C ]//P r o c e e d i n g s o f t h e 2004E l e c t r i c a lO v e r s t r e s s /E l e c t r o s t a t i cD i s c h a r g e S y m po s i u m.R o m e :E S D A s s o c i a t i o n ,2004:5272616.(编辑:郭 华)101第5期 陈迪平等:3.3VC MO S 工艺下5V 电源轨的E S D 箝位电路。
GGNMOS ESD器件的建模与仿真
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本文的设计目标是人体模型 HBM4 kV，考虑到 ESD 器件的电压高、放电时间短、上升时间快等特点， 导致很难通过电路模拟出具体的 ESD 放电情况。通 常业内直接的做法是设计者根据电路设计要求和设计 经验进行多次流片测试验证，但是大量的流片测试与 验证既耗时又费力而且成功率不高，因此急需一种方 法可简化设计时间与流程，而通过对器件进行模型建 立，进而通过软件进行相应的仿真得到器件的性能参 数，是一种简单而有效的方法 [2]。
摘要：完成了 GGNMOS ESD 器件的建模，提出了 ESD 瞬时大脉冲条件下二次击穿前保护器件 GGNMOS 的理 论模型，并利用 Spectre 工具完成了模型的仿真验证。通过仿真得到二次击穿前保护器件 GGNMOS I-V 特性曲线， 确定设计的 GGNMOS 器件的触发电压 Vt、维持电压 Vp 等电参数能否满足 ESD 器件设计窗口的需要。
2020 年 4 月 25 日第 37 卷第 8 期
doi：10.19399/ki.tpt.2020.08.034
Telecom Power Technology
A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology
A Family of Low-Power Truly Modular Programmable Dividersin Standard0.35- m CMOS TechnologyCicero S.Vaucher,Igor Ferencic,Matthias Locher,Sebastian Sedvallson,Urs V oegeli,and Zhenhua Wang Abstract—A truly modular and power-scalable architecture forlow-power programmable frequency dividers is presented.The ar-chitecture was used in the realization of a family of low-power fullyprogrammable divider circuits,which consists of a17-bit UHF di-vider,an18-bit(a)(b)Fig.2.Programmable prescaler.(a)Basic architecture.(b)With extended division range.B.Programmable Prescaler ArchitecturesThe “basic”programmable prescaler architecture is depicted in Fig.2(a).The modular structure consists of a chain of 2/3di-vider cells connected like a ripple counter [11].The structure of Fig.2(a)is characterized by the absence of long delay loops,as feedback lines are only present between adjacent cells.This “local feedback”enables simple optimization of power dissipa-tion.Another advantage is that the topology of the different cells in the prescaler is the same,therefore facilitating layout work.The architecture of Fig.2(a)resembles the one presented in [12],which is also based on 2/3divider cells.Yet there are two fun-damental differences.First,in [12]all cells operate at the same (high)current level.Second,the architecture of [12]relies on a common strobe signal shared by all cells.This leads to high power dissipation,because of high requirements on the slope of the strobe signal,in combination with the high load presented by all cells in parallel.The programmable prescaler operates as follows.Once in a division period,the last cell on the chain generates thesignalThis signal then propagates “up”the chain,being re-clocked by each cell along the way.An active mod signal en-ables a cell to divide by 3(once in a division cycle),provided that its programminginput2/3cells provides an output signalwith a periodofis the period of the inputsignalLet us introduce the concept of effectivelengthand,but the gap between thisvalue and the continuous division range makes it useless in standard synthesizer applications.Fig.3.Family of truly modular programmable dividers,and corresponding division range of the differentimplementations.Fig.4.Functional blocks and logical implementation of a 2/3divider cell.Three circuits were implemented:an18-bit-band divider was used as the basis for the UHF and for the reference divider.The UHF divider consists of the same cir-cuitry asthe-band di-vider stripped off its six high frequency cells.B.Logic Implementation of the 2/3Divider CellsA 2/3divider cell comprises two functional blocks,as de-picted in Fig.4.The prescaler logic block divides,upon control by the end-of-cycle logic ,the frequency oftheand signal becomes active once in a division cycle.At that moment,the state ofthe=1,the end-of-cycle logic forces theprescalerFig.5.SCL implementation of an AND gate combined with a latch function.to swallow one extra period of the input signal.In other words,the cell divides by 3.Ifinput,the end-of-cyclelogic reclocksthesignal,and outputs it to the preceding cell in thechainFig.6.Transient simulation of optimized L -band divider.used to implement Dlatch1,Dlatch3,Dlatch4and the AND gates of the 2/3cells (see Fig.4).Therefore,six logic functions are achieved,at the expense of three tail currents only.Dlatch2is implemented as a “normal”D latch (without the differential pair connected to the b–bn inputs).The nominal voltage swing is set to 500mV in the high fre-quency (and high current)cells,and to 300mV in the low cur-rent cellsis the period of the cell’s inputsignal.The input frequency for each cell is scaled down by the previous one.As a consequence,the maximum allowed delay increases as one moves “down”the chain.As the delay in a cell is inverse proportional to the cell’s current consumption (which is a property of current mode logic circuits),the currents in the cells may be scaled down as well.The results of a transient simulation with the optimized highfrequency cells of the20dBm),has been split into two differen-tial stages.Each differential pair operates with 50--band inputamplifier is a scaled version of the UHF input amplifier.The tail currents were doubled,and the drain resistances were halved.The nominal low frequency small signal gain of the UHF ampli-fier is 26dB;the gain of theresistances.The feedback provides dc biasing to thefirst stage,and allows AC coupling of the VCO signal to the first differential pair.IV .M EASUREMENTSThe control currents for the UHF andFig.7.Sensitivity of the UHF divider,for different divider current settings.Division ratio =511,nominal current is I =10A.Fig.8.Sensitivity curves of the L -band divider,for a few divider and amplifier current settings.Division ratio =1023.Fig.9.Maximum operation frequency of the UHF and L -band dividers,as function of divider current consumption (excluding input amplifiers).controlled by the inputcurrentis10-band di-vider,for different current settings in the divider and input am-plifier.Such as the UHF divider,thetoground,which were set close to the input leads of the input am-plifiers.The maximum operation frequencies of the UHFandA yields a sensitivity valuein excess of 10mVrms.The influence of the supply voltage on the maximum oper-ating frequency was found to be small(decreased from 2.2V down to 1.8V).It is interesting to mention thatFig.11.Phase noise of the reference and UHF divider,measured at 10MHz.---Reference divider (I =10 ,F =20MHz,010dBm).—Reference divider (I =10 ,F =20MHz,020dBm).parison of power efficiency (GHz/mW).MCML circuits have been demonstrated to operate with supply voltages as low as 1.2V [15],without significant loss of speed.B.Phase NoiseThe phase noise of the UHF and reference dividers was measured with a dedicated phase noise measurement system.We used coherent demodulation techniques (phase-locked loop configuration),and employed a low-noise 10MHz signal source during the evaluation of the circuits.To facilitate the measurements,we implemented signal taps onthe122dBc/Hz (nominalbias,=10=12.5127.5d B c /H z d o w nto-b a n dd i v i de r s ,i n c o m p a r i s o n t o r e c e n t l y p u b l i s h e d d a t a d i v i d e r s a n d t u n i n g s y s t e m s .P o w e r ef f i c i e n c y i s d t h e r a t i o o f t h e d i v i d e r ’s m a x i m u m o p e r a t i o n f r e qIEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.35,NO.7,JULY 20001045power dissipation,with dimensions of GHz/mW.The authors have found that (most of)the dividers presented in the literature do not include an input amplifier.Therefore,only the current consumption of the “core”divider circuits is taken in the calcu-lations.This leads to a fair comparison of the available data.Refs.[2]and [8]describe prescalers implemented in bulk CMOS technology.Reference [16]proposes a new synthe-sizer architecture,where the divider is “powered-down”after lock has been achieved.Ref.[14]describes a fully pro-grammable divider implemented in an ultrathin-film0.25--band divider’s.Ourdivider,however,is implemented in a standard0.35-m CMOS toperformance levels comparable to more expensive technolo-gies,such as bipolar and CMOS/SIMOX processes.V .C ONCLUSIONThis paper presented a truly modular and power-scalable architecture for low-power fully programmable frequency dividers.The flexibility and reusability properties of the architecture were demonstrated with the realization of a family of programmable divider circuits,consisting of the UHF divider (17bits),the-band circuitry.The implementation of the 2/3divider cells was presented,and the power dissipation optimization procedure was described.To cope with EMC considerations,the dividers were implemented in CMOS SCL (current mode logic).The circuits were processed in a standard0.35--band divider,0.57GHz/mW.The measured input sensitivity,including the input amplifiers,is20mVrms forthe [12][13][14][15]。
ANSI-ESD+STM9.1-2006(footwear)
ANSI/ESD STM9.1-2006Reaffirmation of ANSI/ESD STM9.1-2001For the Protection of Electrostatic Discharge Susceptible ItemsFootwear – Resistive Characterization(not to include heel straps and toe grounders)Electrostatic Discharge Association 7900 Turin Road, Bldg. 3 Rome, NY 13440 An American National Standard Approved October 5, 2006ANSI/ESD STM9.1-2006ESD Association Standard for the Protection of Electrostatic Discharge Susceptible Items –Footwear – Resistive Characterization(not to include heel straps and toe grounders)Approved June 11, 2006 ESD Association®ANSI/ESD STM9.1-2006CAUTION NOTICEESD Association standards and publications are designed to serve the public interest by eliminating misunderstandings between manufacturers and purchasers, facilitating the interchangeability and improvement of products and assisting the purchaser in selecting and obtaining the proper product for his particular needs. The existence of such standards and publications shall not in any respect preclude any member or non-member of the Association from manufacturing or selling products not conforming to such standards and publications. Nor shall the fact that a standard or publication is published by the Association preclude its voluntary use by non-members of the Association whether the document is to be used either domestically or internationally. Recommended standards and publications are adopted by the ESD Association in accordance with the ANSI Patent policy. Interpretation of ESD Association Standards: The interpretation of standards in-so-far as it may relate to a specific product or manufacturer is a proper matter for the individual company concerned and cannot be undertaken by any person acting for the ESD Association. The ESD Association Standards Chairman may make comments limited to an explanation or clarification of the technical language or provisions in a standard, but not related to its application to specific products and manufacturers. No other person is authorized to comment on behalf of the ESD Association on any ESD Association Standard.DISCLAIMER OF WARRANTIESThe contents of ESDA’s standards and publications are provided “as-is,” and ESDA makes no representations or warranties, express or implied, of any kind with respect to such contents. ESDA disclaims all representations and warranties, including without limitation, warranties of merchantability, fitness for particular purpose or use, title and noninfrigement. Disclaimer of Guaranty: ESDA standards and publications are considered technically sound at the time they are approved for publication. They are not a substitute for a product seller’s or user’s own judgment with respect to any particular product discussed, and ESDA does not undertake to guaranty the performance of any individual manufacturers’ products by virtue of such standards or publications. Thus, ESDA expressly disclaims any responsibility for damages arising from the use, application or reliance by others on the information contained in these standards or publications. Limitation on ESDA’s Liability: Neither ESDA, nor its members, officers, employees or other representatives will be liable for damages arising out of or in connection with the use or misuse of ESDA standards or publications, even if advised of the possibility thereof. This is a comprehensive limitation of liability that applies to all damages of any kind, including without limitation, loss of data, income or profit, loss of or damage to property and claims of third parties.Published by: Electrostatic Discharge Association 7900 Turin Road, Bldg. 3 Rome, NY 13440 Copyright © 2006 by ESD Association All rights reserved No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. Printed in the United States of America ISBN: 1-58537-117-3ANSI/ESD STM9.1-2006(This foreword is not part of ESD Association Standard Test Method STM9.1-2006)FOREWORD This standard is intended to provide a test method for evaluating the resistance of static control footwear. This standard does not include heel straps, toe grounders and booties. This standard is limited to defining procedures for measuring the electrical resistance of footwear only and does not address electrical resistance through a person or in combination with floor materials. A common source of electrostatic charge in a work environment is the separation of the foot from the floor, resulting in the generation of electrostatic charge that can accumulate on personnel. The effect of this generation and accumulation can be minimized by the appropriate selection of footwear. To effectively control electrostatic charges, footwear must be used in conjunction with ESD floors or floor materials as defined in ANSI/ESD S7.1. Static control footwear may also pose an electrical hazard unless properly designed and worn in appropriate environments. The test method described in this document will not guarantee electrical hazard reduction. This standard was originally designated ESD S9.1-1995 and was approved on June 5, 1995. Standard Test Method ANSI/ESD STM9.1-2001 was a reaffirmation and redesignation of ESD S9.1-1995 and was approved on February 4, 2001. Standard Test Method ANSI/ESD STM9.1-2006 is a reaffirmation of ANSI/ESD STM9.1-2001 and was approved on June 11, 2006. All documents were prepared by the 9.0 Footwear Subcommittee. At the time the S9.1-1995 version was prepared, the 9.0 Footwear Subcommittee had the following members: Peter Freeman Ben Baumgartner Lt. Victoria L. Ambuehl Hewlett Packard Lockheed USAF, Chair Steve Gerken USAF Paul Isenberg H.H. Brown Shoe Co. Don Stella Iron Age Larry Burich Lockheed Ken Dille Red Wing Shoe Co. Ron Gibson Celestica Erling Krog-Jensen Ericsson Telecom AB Anna Maria Steritti David Howlett HY-Test Alan Peters Lehigh Safety Shoe Co. Wayne Tan Advanced Micro Devices Sheryl Zayic BoeingThe following individual made significant contributions to this document: Sharon KaminskasiANSI/ESD STM9.1-2006At the time the STM9.1-2006 version was prepared, the 9.0 Footwear Subcommittee had the following members: Brent Beamer 3M Dale Parkin, Chair IBM Mark Fancourt Lehigh Safety Shoe Co. Kevin Duncan Seagate TechnologyiiANSI/ESD STM9.1-2006TABLE OF CONTENTS1.0 PURPOSE, SCOPE AND APPLICATION.............................................................................. 1 1.1 PURPOSE ............................................................................................................................. 1 1.2 SCOPE ................................................................................................................................. 1 1.3 APPLICATION ........................................................................................................................ 1 2.0 REFERENCED DOCUMENTS ............................................................................................... 1 3.0 DEFINITION OF TERMS ........................................................................................................ 1 4.0 PERSONNEL SAFETY........................................................................................................... 1 5.0 TEST METHOD....................................................................................................................... 2 5.1 APPARATUS REQUIREMENTS ................................................................................................. 2 5.1.1 Resistance Measuring Apparatus (Meter) ................................................................... 2 5.1.2 Electrodes .................................................................................................................... 2 5.1.3 Weight .......................................................................................................................... 2 5.1.4 Environmental Test Chamber ...................................................................................... 2 5.1.5 Calibration Requirements ............................................................................................ 2 5.2 TEST PROCEDURE / CONDITIONING ........................................................................................ 2 5.2.1 Specimen Pre-conditioning .......................................................................................... 2 5.2.2 Test Configuration........................................................................................................ 3 5.2.3 Resistance Measurement Procedure........................................................................... 3 5.2.4 Reporting of Test Results ............................................................................................ 4 FIGURES Figure 1. Test Setup ....................................................................................................................... 5 Figure 2. Test Result Form............................................................................................................. 6 ANNEX A ........................................................................................................................................ 7iiiESD Association Standard Test MethodANSI/ESD STM9.1-2006ESD Association Standard Test Method for Protection of Electrostatic Discharge Susceptible Items – Footwear – Resistive Characterization 1.0 PURPOSE, SCOPE AND APPLICATION 1.1 Purpose This standard provides a test method to measure the electrical resistance of static control footwear. 1.2 Scope This standard relies on electrical resistance measurements utilizing common electrical instruments to provide a means of evaluating footwear. This standard excludes heel straps, toe grounders, etc. 1.3 Application This standard is intended to be used in the qualification of static control footwear. 2.0 REFERENCED DOCUMENTS ESD ADV 1.0, ESD Association Glossary of Terms1 ANSI/ESD S7.1, Floor Materials – Characterization of Materials1 ANSI/ESD S20.20, Development of an Electrostatic Discharge Control Program for – Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices)1 ASTM D-257, Standard Test Methods for D-C Resistance or Conductance of Insulating Materials2 3.0 DEFINITION OF TERMS The following definition shall apply for the purposes of this standard in addition to those specified in the ESD Association Glossary of Terms: Static Control Footwear (Footwear). Coverings for the human foot that have properties to dissipate static charge when used in conjunction with a static control floor or floor surface as defined in ANSI/ESD S7.1. 4.0 PERSONNEL SAFETY 4.1 The procedures and equipment described in this document may expose personnel to hazardous electrical conditions. Users of this document are responsible for selecting equipment that complies with applicable laws, regulatory codes and external and internal policy. Users are cautioned that this document cannot replace or supercede any requirements for personnel safety. The ultimate responsibility for personnel safety resides with the end user of this document. Ground Fault Circuit Interrupters (GFCI) and other safety protection should be considered wherever personnel might come into contact with electrical sources. Electrical hazard reduction practices should be exercised and proper grounding instructions for the equipment must be followed when performing these tests.1 2ESD Association, 7900 Turin Road, Bldg. 3, Rome, NY 13440-2069, 315-339-6937 American Society for Testing and Materials (ASTM), 1916 Race Street, Philadelphia, PA 19103-1187, 215-299-54001ANSI/ESD STM9.1-20064.2 The resistance values obtained using the test method described in this document are not to be used to define the relative electrical hazard reduction afforded by footwear. 5.0 TEST METHOD This section describes the test method for measuring the electrical resistance between the inner and outer sole of footwear prior to wearing. 5.1 Apparatus Requirements 5.1.1 Resistance Measuring Apparatus (Meter) The measurement apparatus, called the meter, whether it is a single meter or a collection of instruments, that are capable of the following: The meter shall have circuit voltage of 100 volts (± 5%) DC while under load for measurements of 1.0 x 106 ohms and above. Both test leads shall be isolated from ground. 5.1.2 Electrodes The positive electrode shall consist of a piece of aluminum foil. It shall uniformly contact the maximum amount of the surface area achievable on the inner sole of the footwear under test. The aluminum foil shall be replaced for each new test cycle, or when torn. The negative electrode shall consist of a stainless steel plate larger than the bottom of the footwear, which is placed on an insulative surface. The resistance of the insulative surface shall be greater than 1 x 1013 when measured per ASTM D-257. 5.1.3 Weight Twenty-five pounds (11.35 kg) of metal shot (# 6 or finer) in a bag or bags sufficiently flexible so that when filled with shot they shall conform to inside of the footwear. 5.1.4 Environmental Test Chamber An enclosed chamber capable of controlling relative humidity to 12% RH (± 3%) and 50% RH (± 5%), and temperature to 23 °C (± 3 °C). The humidity indication instrumentation shall be accurate to ± 3% RH in the operation range and traceable to national standards, such as National Institute of Standards and Technology (NIST) in the United States, or to international standards. 5.1.5 Calibration Requirements The test equipment used shall be calibrated periodically in accordance with the manufacturers' recommendations, with a maximum of one year between calibrations. Calibration shall be traceable to national standards, such as NIST in the United States, or to international standards. 5.2 Test Procedure / Conditioning 5.2.1 Specimen Pre-conditioning 5.2.1.1 Cleaning The bottom and inner sole of the specimen shall be wiped with a dry cloth to remove dust. The negative electrode shall be cleaned with a minimum 70% isopropanol-water solution.2ANSI/ESD STM9.1-20065.2.1.2 Humidity Conditioning Test shall be conducted at humidities specified below. 5.2.1.2.1 Low Humidity After cleaning, the samples shall be placed in an environmental chamber preset to 12% (± 3%) relative humidity and 23 °C (± 3 °C). Pre-conditioning of the samples shall be a period of at least 72 hours. 5.2.1.2.2 Moderate Humidity After cleaning, the samples shall be placed in an environmental chamber preset to 50% (± 3%) relative humidity and 23 °C (± 3 °C). Pre-conditioning of the samples shall be a period of at least 72 hours. 5.2.2 Test Configuration The negative electrode shall be placed on the insulative surface described in 5.1.2 and electrically connected to the negative sensing lead of the meter. The aluminum foil shall be inserted into the footwear ensuring that uniform contact with maximum amount of the inner sole is achieved. Fill the footwear with the flexible bags of shot, ensuring that the shot conforms to the footwear. Since footwear styles and sizes vary, it will be necessary to place the excess shot over the top of the footwear. The footwear shall be placed on the negative electrode such that no part of the footwear overhangs the edge. No part of the shot bags shall touch the negative electrode. Connect the positive source lead of the meter to the aluminum foil. Resistance testing shall be conducted in the environmental chamber (Figure 1). NOTE: The resistance of the support surface will not affect the electrical resistance measurement of the sample under test. 5.2.3 Resistance Measurement Procedure 5.2.3.1 Clean footwear per 5.2.1.1. 5.2.3.2 Condition footwear per 5.2.1.2.1 (Low Humidity). 5.2.3.3 Set up the test configuration per 5.2.2. Set the resistance meter to 100 volts DC. Apply the test voltage and record the resistance of the footwear after the reading has stabilized. Remove test voltage and electrode connection. 5.2.3.4 Clean footwear per 5.2.1.1. 5.2.3.5 Condition footwear per 5.2.1.2.2 (Moderate Humidity). 5.2.3.6 Repeat 5.2.3.3 for all samples.3ANSI/ESD STM9.1-20065.2.4 Reporting of Test Results Report all resistance values in ohms. Also report test date/time, test equipment used, environmental pre-conditioning time, temperature, relative humidity, footwear identification and the location of the test. Figure 2 is provided as an example. NOTE: Refer to ANSI/ESD S20.20 for electrical resistance limit for static control footwear. NOTE: It is recognized that some hygroscopic materials (such as, but not limited to, leather) may have results that fluctuate and do not remain within a specified minimum or maximum resistance range as the environmental conditions change.4ANSI/ESD STM9.1-20065 Figure 1. Test SetupResistanceMeasuringApparatusSteel PlateCut away view of foilinside shoe.Cut away view of sockand foil inside shoe.ANSI/ESD STM9.1-20066ESD FOOTWEAR TESTOperator: Test Method: Pre-conditioning Test Conditions Time: Duration: Date: Temperature: Location: % RH:TEST RESULTSFootwear IDResistance (ohms)Figure 2. Test Result FormANSI/ESD STM9.1-20067ANNEX A Fabrication of Shot BagNumber 6 shot is fine and may fall through the fabric weave, especially knit socks. Constructing 2 to 3 inch (4.68 – 7.02 cm) tubes from a tightly woven fabric is recommended.Use of 25 lbs (11.35 kg) of weight.After considerable research it was determined that while weight is a variable when measuring the resistance of footwear, after 25 lbs (11.35 kg) there is no significant difference in the electrical resistance readings. Therefore 25 lbs (11.35 kg) of weight is required.Number 6 shot was chosen because it would most easily conform to the inside surface of any footwear size and lends itself to even weight distribution.。