A High Resolution, Low Offset And High Speed Comparator

A High Resolution, Low Offset and High Speed Comparator Kliayrollah Hadidi" and Gabor C. Temes"" *Integrated Circuits and Systems Laboratory, University of California, Los Angeles, CA 90024 ""Electrical and Computer Engineering Department, Oregon State University, Corvallis, OR 97331-3211

Abstract This paper describes a CMOS comparator which uses a novel feedforward autozeroing circu- itry to obtain high speed and low threshold uncer- tainty.' Fabricated in a standard 2pm digital CMOS process, it achieved an input resolution of 0.23mV at a comparison speed of 30MS/s. The

residual offset (included in the 0.23 mV resolu- tion) was less than 100pV. The circuit con- sumes 5mW from a single 5Volt supply. The

active area for the circuit is 0.33~ 0.4 mm'.

Introduction An accurate and fast comparator is a key ele- ment in any high-resolution and high-speed data converter. The comparator offset, however, is not tolerable in high-speed high-resolution flash or pipeline AD converters and must be cancelled.

This is due to the fact that these types of con- verters require more than one comparator, and the random distribution of the comparators' offset can completely distort the output data. Conventional methods of offset cancellation require a closed feedback loop. Thus, the comparator must be slowed down to meet stability requirements. This paper describes a CMOS comparator which uses a

novel technique for reducing the offset. The technique allows the comparator to remain in an open-loop condition all the time, and hence to

operate much faster than the usual autozeroing schemes perniit.

Kh. Hadidi is currently with Yokogawa Electric Co.,

Tokyo,

Japan.

The Comparator Architecture The block diagram of the comparator is shown in Fig. 1. During the $2 = 1 half-period, the output-referred offset A Voff of the input

stage is stored in capacitors C at the auxiliary

input port of the dual-input second stage. In the second half-period (when $2 = 0) the first stage amplifies the differential input voltage Vdiff =

Vi, -Vrk plus its own input-referred

offset Voffl, and feeds the amplified signal to the

main input port of the second stage as voltage

V, (Fig. 2). Since the output voltage of the second stage is proportional to the difference

between its two input voltages, Voff is can- celled. The offset voltages of the two input ports of stage 2 remain in the signal path, but they are

divided by A, when referred back to the input, as is the clock-feedthrough noise of the offset

sampling switchies in the second stage. Note that

this method of offset cancellation does not require a negative feedback loop around the comparator, which would slow down its operation. Similar dual-input compensation was used earlier in CMOS amplifiers and data converters, but a feed-

back loop was used even in those cases2

The Circuit Design

16.1 .I IEEE 1992

CUSTOM INTEGRATED CIRCUITS CONFERENCE

Fig. 3 shows the schematic diagram for the first stage of the comparator. The currents injected by the input differential pair (IDP) to the low-impedance nodes have to be absorbed by M

and M,. Since only half of the input differential

0-7803-0246-x/92 $3.00 0 1992 IEEE

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k3Jl Fig. 1 Block diagram of the comparator.

signal appears as input to M, and half output differential signal appears as input we have 1 I of the to M,,

which gives a voltage gain A = g, 1/g,3. The gain is nominally about 13, but it varies slightly with the variation of the common-mode voltage in

the output of the stage. The source-coupled dev- ices M,, M, and M, average the output voltages and compare the average with the reference level "BIAS 2" to stabilize the output common-mode voltage. Also, the load devices M,, M, prevent large variations of the output common-mode vol-

tage at the cost of some gain variation.

Fig. 2 A detailed block diagram of the Comparator. The second stage is identical to the first one

except for the fact that it has two IDPs. The switches at the outputs of the first and second stages (Fig. 1) close briefly at the beginning of the clock-period to speed up the offset cancel- lation process. This, in conjunction with setting the comparator input to zero when $, = 1,

greatly reduces the hysteresis of the comparator. The latch used in the Comparator is shown in Fig. 4. It is very similar to the latch previously