CX918 中文技术资料

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MB88181PFT-G-001-BNDE1;中文规格书,Datasheet资料

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MB88181
■ BLOCK DIAGRAM
VDD
XOUT
Clock input Selector divider
Rf = 500 kΩ CLK1
XIN
Selector divider SSCG (with SS function) Power down
Oscillation frequency setting/Modulation setting
CLK2
Selector divider
CLK3
Divider PLL1 (without SS function)
Oscillation frequency setting
K5
Divider
CLK6
PLL2 (without SS function)
Oscillation frequency setting
■ OSCILLATION FREQUENCY
The frequencies of the PLL1, PLL2, PLL3, and SSCG can be determined by the following formula. Oscillation frequency = M N × (reference clock (input clock) frequency) [M is an integer between 8 and 512, N is an integer between 7 and 32] Note : From among the range of frequencies that can be selected by the above formula, the range of frequencies that can actually be generated is from 128 MHz to 400 MHz. M and N can be configured separately for each of the PLL1, PLL2, PLL3, and SSCG. Furthermore, these can be configured separately for each of the SL0, SL1 pin settings.

CDC318DLR中文资料

PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)CDC318DL OBSOLETE SSOP DL 48TBD Call TI Call TI CDC318DLROBSOLETESSOPDL48TBDCall TICall TI(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemicalanalysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM16-Dec-2006Addendum-Page 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityLow Power Wireless /lpw Telephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2006, Texas Instruments Incorporated。

XPGA资料

ispXPGA FamilyMarch 2003Preliminary Data SheetTM© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at /legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci ﬁcations and information herein are subject to change without notice.■Non-volatile, In ﬁnitely Recon ﬁgurable•Instant-on - Powers up in microseconds via on-chip E 2CMOS ® based memory •No external con ﬁguration memory•Excellent design security , no bit stream to intercept •Recon ﬁgure SRAM based logic in milliseconds■High Logic Density for System-levelIntegration•139K to 1.25M system gates •160 to 496 I/O•1.8V , 2.5V , and 3.3V V CC operation•Up to 414Kb sysMEM™ embedded memory■High Performance Programmable FunctionUnit (PFU)•Four LUT -4 per PFU supports wide and narrow functions•Dual ﬂip-ﬂops per LUT -4 for extensive pipelining •Dedicated logic for adders, multipliers, multiplex-ers, and counters■Variable-Length Interconnect RoutingTechnology•Optimum speed, power, and ﬂexibility for logic interconnections■ Flexible Memory Resources•Multiple sysMEM Embedded RAM Blocks–Single port, Dual port, and FIFO operation •64-bit distributed memory in each PFU–Single port, Double port, FIFO, and Shift Register operation■ Eight sysCLOCK™ Phase Locked Loops(PLLs) for Clock Management•T rue PLL technology•10MHz to 320MHz operation •Clock multiplication and division •Phase adjustment•Shift clocks in 250ps steps■ sysIO™ for High System Performance•High speed memory support through SSTL and HSTL•Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL•Standard logic supported through LVTTL, LVCMOS 3.3, 2.5, and 1.8•Programmable drive strength for series termination •Programmable bus maintenance■ sysHSI™ Capability for Ultra Fast SerialCommunications•Up to 850Mbps performance •Up to 20 channels per device•Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)■ Flexible Programming, Recon ﬁguration,and Testing•IEEE 1532 and 1149.1 compliant•Microprocessor con ﬁguration interface•Program E 2 CMOS while operating from SRAMTable 1. ispXPGA Family Selection GuideispXPGA 125ispXPGA 200ispXPGA 500ispXPGA 1200System Gates 139K 210K 476K 1.25M PFUs 48467617643844LUT -4s 19362704705615376Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR20244090sysHSI Channels 481220User I/O 160/176160/208336496Packaging256 fpBGA 516 fpBGA 1256 fpBGA 516 fpBGA 1516 fpBGA 1 900 fpBGA680 fpSBGA 1 900 fpBGA1.Thermally enhanced package.Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.Lattice Semiconductor ispXPGA Family Data SheetispXPGA Family OverviewThe ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile andinﬁnitely re-programmable. Other FPGA solutions force a compromise being either re-programmable or non-vola-tile. This family couples this capability with a mainstream architecture containing the features required for today’ssystem-level design.Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability.These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-tions. This capability also means that expensive external conﬁguration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be inﬁnitely reconﬁgured if desired. Both the SRAM and E2CMOS cells can be programmed and veriﬁed through the IEEE 1532 industry stan-dard. Additionally, the SRAM cells can be conﬁgured and read-back through the sysCONFIG™ peripheral port.The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M systemgates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-ing easy integration into the overall system.The system-level needs of designers are met through the incorporation of sysMEM dual-port memory blocks,sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications aresupported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serializa-tion (SERDES).The ispLEVER™ design tool from Lattice allows designers easy implementation of designs using the ispXPGAproduct. Synthesis library support is available for the major logic synthesis tools. The ispLEVER tool takes the out-put from these common synthesis packages and place and routes the design in the ispXPGA product. The toolallows ﬂoor planning and the management of other constraints within the device. The tool also provides outputs tocommon timing analysis tools for timing analysis.T o increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for theispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while usingpre-designed block to implement standard functions such as bus-interfaces, standard communication-interfaces,and memory-controllers.Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.Certain designs can run at over 300MHz. T able 2 details the performance of several building blocks commonlyused by logic designers.Table 2. ispXPGA Speed Performance for Typical Building BlocksFunction Performance8:1 Asynch MUX150 MHz1:32 Asynch Demultiplexer125 MHz8 x 8 2-LL Piped Multiplier225 MHz32-bit Up/Down Counter290 MHz32-bit Shift Register360 MHzLattice Semiconductor ispXPGA Family Data SheetArchitecture OverviewThe ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIOblocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and thesysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-ily implement their designs, since any logic function can be placed in any section of the device.The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They areoptimized for speed and ﬂexibility allowing complex designs to be implemented quickly and efﬁciently.The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registeredquickly to minimize setup times for high-speed designs. They also allow connections directly to the different logicelements for fast access to combinatorial functions.The sysMEM EBRs are large, fast memory elements that can be conﬁgured as RAM, ROM, FIFO, and other stor-age types. They are designed to facilitate both single and dual-port memory for high-speed applications.These three components of the architecture are interconnected via a high-speed, ﬂexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additionalrouting available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.The sysIO blocks consist of conﬁgurable input and output buffers connected directly to the PICs. These buffers canbe conﬁgured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices with-out the need for external transceivers.The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery(CDR) logic.The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increasedperformance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block foreach global clock tree in the device.Lattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice SemiconductorispXPGA Family Data SheetTable 5. ispXPGA Supported I/O StandardsTable 6. Differential Interface Standard Support 1sysIO StandardV CCO V REF V TT LVTTL 3.3V N/A N/A LVCMOS-3.3 3.3V N/A N/A LVCMOS-2.5 2.5V N/A N/A LVCMOS-1.8 1.8V N/A N/A PCI 3.3V N/A N/A AGP-1X3.3V N/A N/A SSTL3, Class I, II 3.3V 1.5V 1.5V SSTL2, Class I, II 2.5V 1.25V 1.25V HSTL, Class I 1.5V 0.75V 0.75V HSTL, Class III 1.5V 0.9V 1.5V GTL+N/A 1.0V 1.5V LVPECL 3.3V N/A N/A LVDS 1 2.5V N/A N/A BLVDS2.5VN/AN/A1.V CCO must be2.5V for high speed serial operations (sysHSI block).sysIO Buffer Not Using sysHSI BlocksysIO Buffer Using sysHSI Block LVDS Driver Supported with external resistor network SupportedReceiver Supported with standard termination Supported with standard termination BLVDS Driver Supported with external resistor network Not supportedReceiver Supported (may need termination)Supported (may need termination)LVPECLDriver Supported with external resistor network Not supportedReceiverSupported with terminationSupported with termination1.For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines,available at .Lattice Semiconductor ispXPGA Family Data SheetTable 7. sysHSI Block REFCLK Selections1sysHSI Block Available Global Clock Nets0CLK0, CLK1, CLK2, CLK31CLK0, CLK1, CLK2, CLK42CLK0, CLK1, CLK2, CLK53CLK0, CLK1, CLK3, CLK64CLK0, CLK1, CLK3, CLK75CLK0, CLK3, CLK5, CLK76CLK0, CLK2, CLK5, CLK77CLK0, CLK1, CLK5, CLK68CLK0, CLK5, CLK69CLK0, CLK5, CLK6, CLK71.T able 6 applies to all devices. Ignore sysHSI blocks not availablein a speciﬁc device.Conﬁguration and ProgrammingThe ispXPGA family of devices takes a unique approach to FPGA conﬁguration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA conﬁguration and the SRAM as the working conﬁgura-tion memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be conﬁgured either from the E2CMOS memory or from an external source, as shown in Figure 21.Figure 21 shows the different ports and modes that are used in the conﬁguration and programming of the ispXPGA devices. There are two possible ports that can be used for conﬁguration of the SRAM memory: the ISP port which is compliant to the IEEE 1149.1 T est Access Port (T AP) Std. and the ISP port which accommodates bit-wide conﬁg-uration. The sysCONFIG port allows byte-wide conﬁguration of the SRAM conﬁguration memory. When program-ming the E2CMOS memory, only the 1149.1 T AP can be used.Conﬁguration and programming done through the 1149.1 T est Access Port (T AP) are fully compliant to both the IEEE Std. 1149.1 Boundary Scan T AP speciﬁcation and the IEEE Std. 1532 In-System Conﬁguration speciﬁcation. T o conﬁgure or program the device using the 1149.1 T AP the device must be in the ISP mode. T o conﬁgure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM memory can be conﬁgured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-conﬁgured from the E2CMOS memory by executing a “REFRESH.” See Lattice technical note number TN1026, is pXP Conﬁguration Us age Guide, for more in depth information on the different programming modes, timing and wake-up, available at .Absolute Maximum Ratings 1, 2, 31.8V2.5V/3.3VSupply Voltage (V CC ). . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (V CCP ) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (V CCO ). . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 T AP Supply Voltage (V CCJ ). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied 4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Storage T emperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C Junction T emperature (T J ) with Power Applied . .-55 to 150°C. . . . . . . . . -55 to 150°C1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci ﬁcation is not implied (while programming, following the programming speci ﬁcations).2. Compliance with the Lattice Thermal Management technical note is required.3. All voltages referenced to GND.4. Overshoot and undershoot of -2V to (V IH (MAX) + 2) volts is permitted for a duration of <20nsRecommended Operating ConditionsE 2CMOS Erase Reprogram Speci ﬁcationsHot Socketing Characteristics 1, 2, 3, 4SymbolParameterMin Max Units V CCSupply Voltage for 1.8V device1.65 1.95V Supply Voltage for2.5V device 2.3 2.7V Supply Voltage for3.3V device3.0 3.6V V CCPSupply Voltage for PLL block for 1.8V device1.65 1.95V Supply Voltage for PLL block for2.5V device 2.3 2.7V Supply Voltage for PLL block for3.3V device3.0 3.6V V CCJ Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS 1.8V1.65 1.95V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS2.5V 2.3 2.7V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS3.3V 3.0 3.6V T J (COM)Junction T emperature Commercial Operation 085C T J (IND)Junction T emperature Industrial Operation-40105CParameterMin Max Units Erase/Reprogram Cycle 11,000—Cycles1.Valid over commercial temperature range.Symbol ParameterConditionMin Typ Max Units I DKInput or I/O Leakage Current0 ≤ V IN ≤ 3.0V—+/-50+/-800µA1. Insensitive to sequence of V CC and V CCO . However, assumes monotonic rise / fall rates for V CC and V CCO .2. LVTTL, LVCMOS only3. 0 < V CC ≤ V CC (MAX), 0 < V CCO ≤ V CCO (MAX)4.I DK is additive to I PU , I PD or I BH . Device defaults to pull-up until fuse circuitry is active.DC Electrical CharacteristicsOver Recommended Operating ConditionsSupply CurrentOver Recommended Operating ConditionsSymbol ParameterConditionMin Typ Max Units I IL , I IH 1Input or I/O Low Leakage 0 ≤ V IN < (V CCO - 0.2V)——10µA (V CCO - 0.2V) ≤ V IN ≤ 3.6V ——40µA I PU I/O Active Pull-up Current 0 ≤ V IN ≤ 0.7 V CCO30—150µA I PD I/O Active Pull-down CurrentV IL (MAX) ≤ V IN ≤ V IH (MAX)30—150µA I BHLS Bus Hold Low Sustaining Current V IN = V IL (MAX)30——µA I BHHS Bus Hold High Sustaining Current V IN = 0.7 V CCO 30——µA I BHLO Bus Hold Low Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA I BHHO Bus Hold High Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA V BHT Bus Hold T rip Points V CCO * 0.35—V CCO * 0.65V C 1I/O Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—8—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 2Clock Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 3Global Input Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pfV CC = 1.8V , V IO = 0 to V IH (MAX)——1.Input or I/O leakage current is measured with the pin con ﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled.2.T A = 25°C, f = 1.0MHz.Symbol ParameterCondition Min Typ Max Units I CC 1, 2Standby Core Operating Power Supply CurrentV CC = 3.3V —220—mA V CC = 2.5V —220—mA V CC = 1.8V —200—mA I CCO 3Standby Output Power Supply CurrentV CCO = 3.3V— 2.0—mA V CCO = 2.5V — 2.0—mA V CCO = 1.8V — 2.0—mA V CCO = 1.5V — 2.0—mA I CCP 4Standby PLL Operating Supply CurrentV CCP = 3.3V—17.0—mA V CCP = 2.5V —17.0—mA V CCP = 1.8V —15.0—mA I CCJ 5Standby IEEE 1149.1 T AP Power Supply CurrentV CCJ = 3.3V— 2.0—mA V CCJ = 2.5V — 1.5—mA V CCJ = 1.8V—1.0—mA1.T A = 25˚C, frequency = 1.0 MHz, device con ﬁgured with 16-bit counters.2.I CC varies with speci ﬁc device con ﬁguration and operating frequency. For more accurate power calculation use the ispXPGA Power Estimator.3.T A = 25˚C, per bank, no DC load, frequency = 0 MHz.4.T A = 25˚C, per PLL, frequency = 10 MHz.5.T A = 25˚CsysIO Differential Standards DC Electrical CharacteristicsParameter Description Test Conditions Min.Typ.Max. LVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM RT = 100 Ohm— 1.38V 1.60V V OL Output Low Voltage for V OP or V OM RT = 100 Ohm0.9V 1.03V—V OD Output Voltage Differential|V OP - V OM|, R T = 100 ohm250mV350mV450mV ∆V OD Change in V OD between high and low——50mVV OS Output Voltage Offset|V OP + V OM|/2, R T = 100 ohm 1.125V 1.25V 1.375V ∆V OS Change in V OS between H and L——50mV——24mA I OSD Output short circuit current V OD = 0V Driver outputsshortedBLVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM R T = 27Ω— 1.4V 1.80V V OL Output Low Voltage for V OP or V OM R T = 27Ω0.95V 1.1V—V OD Output Voltage Differential|V OP - V OM|, RT = 27Ω240mV300mV460mV ∆V OD Change in V OD Between H and L27mV V OS Output Voltage Offset|V OP + V OM| /2, RT = 27Ω 1.1V 1.3V 1.5V ∆V OS Change in V OS Between H and L27mVI OSD Output Short Circuit Current V OD = 0. Driver Outputs36mA65mAShorted.1.V OP and V OM are the two outputs of the LVDS/BLVDS output buffer.LVPECL1DCParameter Parameter Description Min.Max.Min.Max.Min.Max.Units V CCO 3.0 3.3 3.6V V IH Input Voltage High 1.49 2.72 1.49 2.72 1.49 2.72V V IL Input Voltage Low0.86 2.1250.86 2.1250.86 2.125V V OH Output Voltage High 1.8 2.11 1.92 2.28 2.13 2.41V V OL Output Voltage Low0.96 1.27 1.06 1.43 1.3 1.57V V DIFF Differential Input voltage0.3—0.3—0.3—V 1.These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 22). The V OH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.ispXPGA PFU Timing ParametersOver Recommended Operating ConditionsParameter Description-4-3Units Min.Max.Min.Max.Functional DelaysLUTst LUT44-Input LUT Delay—0.44—0.51ns t LUT55-Input LUT Delay—0.79—0.91ns t LUT66-Input LUT Delay—0.93— 1.07ns Shift Register (LUT)t LSR_S Shift Register Setup Time-0.62—-0.53—ns t LSR_H Shift Register Hold Time0.63—0.72—ns t LSR_CO Shift Register Clock to Output Delay—0.75—0.86ns Arithmetic Functionst LCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (Rip-ple)—0.09—0.10ns t LCTHRUL1MC Carry In to MC Carry Out Delay (Look Ahead)—0.05—0.06ns t LSTHRU MC Sum In to MC Sum Out Delay—0.45—0.52ns t LSINCOUT MC Sum In to MC Carry Out Delay—0.31—0.36ns t LCINSOUTR MC Carry In to MC Sum Out Delay (Ripple)—0.39—0.45ns t LCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead)—0.28—0.32ns Feed-thrut LFT PFU Feed-Thru Delay—0.16—0.18ns Distributed RAMt LRAM_CO Clock to RAM Output— 1.33— 1.53ns t LRAMAD_S Address Setup Time-0.40—-0.34—ns t LRAMD_S Data Setup Time0.22—0.25—ns t LRAMWE_S Write Enable Setup Time0.46—0.53—ns t LRAMAD_H Address Hold Time0.60—0.69—ns t LRAMD_H Data Hold Time0.11—0.13—ns t LRAMWE_H Write Enable Hold Time0.12—0.14—ns t LRAMCPW Clock Pulse Width (High or Low) 3.00— 3.45—ns t LRAMADO Address to Output Delay—0.93— 1.07ns Register/Latch DelaysRegisterst L_CO Register Clock to Output Delay—0.62—0.71ns t L_S Register Setup Time (Data before Clock)0.14—0.16—ns t L_H Register Hold Time (Data after Clock)-0.12—-0.10—ns t LCE_S Register Clock Enable Setup Time-0.11—-0.09—ns t LCE_H Register Clock Enable Hold Time0.11—0.13—ns Latchest L_GO Latch Gate to Output Delay—0.10—0.12ns t LL_S Latch Setup Time0.14—0.16—ns t LL_H Latch Hold Time-0.12—-0.10—ns t LLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12nsispXPGA PIC Timing ParametersReset/Sett LASSRO Asynchronous Set/Reset to Output — 1.17— 1.35ns t LASSRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t LASSRR Asynchronous Set/Reset Recovery —0.55—0.63ns t LSSR_S Synchronous Set/Reset Setup Time -0.03—-0.03—ns t LSSR_HSynchronous Set/Reset Hold Time0.03—0.03—ns1.t LCTHRUL quoted bit by bit.Timing v.2.0Parameter Description -4-3UnitsMin.Max.Min.Max.Register/Latch Delays t IO_CO Register Clock to Output Delay— 1.09— 1.25ns t IO_S Register Setup Time (Data before Clock)0.05—0.06—ns t IO_H Register Hold Time (Data after Clock)0.06—0.07—ns t IOCE_S Register Clock Enable Setup Time -0.03—-0.03—ns t IOCE_H Register Clock Enable Hold Time 0.13—0.15—ns t IO_GO Latch Gate to Output Delay —0.91— 1.05ns t IOL_S Latch Setup Time 0.05—0.06—ns t IOL_H Latch Hold Time0.06—0.07—ns t IOLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12ns t IOASRO Asynchronous Set/Reset to Output — 1.26— 1.45ns t IOASRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t IOASRR Asynchronous Set/Reset Recovery Time —0.25—0.29ns Input/Output Delayst IOBUF Output Buffer Delay — 1.06— 1.22ns t IOIN Input Buffer Delay —0.76—0.87ns t IOEN Output Enable Delay —0.56—0.64ns t IODIS Output Disable Delay —-0.10—-0.09ns t IOFTFeed-thru Delay—0.20—0.23nsTiming v.2.0ispXPGA PFU Timing Parameters (Continued)Over Recommended Operating ConditionsParameterDescription-4-3Units Min.Max.Min.Max.ispXPGA EBR Timing ParametersParameter Description-4-3Units Min.Max.Min.Max.Synchronous Writet EBSWAD_S Address Setup Delay0.61—0.70—nst EBSWAD_H Address Hold Delay-0.39—-0.33—nst EBSWCPW Clock Pulse Width— 3.40— 3.91nst EBSWWE_S Write Enable Setup Time-0.12—-0.10—nst EBSWWE_H Write Enable Hold Time0.16—0.18—nst EBSWD_S Data Setup Time0.28—0.32—nst EBSWD_H Data Hold Time-0.26—-0.22—ns Synchronous Readt EBSR_CO Clock to Data Delay— 2.19— 2.52nst EBSRAD_S Address Setup Delay0.10—0.12—nst EBSRAD_H Address Hold Delay-0.07—-0.06—nst EBSRCPW Clock Pulse Width— 3.40— 3.91nst EBSRCE_S Clock Enable Setup Time-1.71—-1.45—nst EBSRCE_H Clock Enable Hold Time 1.69— 1.94—nst EBSRWE_S Write Enable Setup Time-0.17—-0.14—nst EBSRWE_H Write Enable Hold Time0.12—0.14—nst EBSRWEEN Write Enable to Data Enable Time— 1.05— 1.21nst EBSRWEDIS Write Enable to Data Disable Time— 1.02— 1.17nst EBSREN Output Enable to Data Enable Time— 1.05— 1.21nst EBSRDIS Output Enable to Data Disable Time—0.86—0.99ns Asynchronous Readt EBARADO Address to New Valid Data Delay— 2.46— 2.83nst EBARAD_H Address to Previous Valid Data Delay— 2.17— 2.50nst EBARWEEN Write Enable to Data Enable Time— 1.04— 1.20nst EBARWEDIS Write Enable to Data Disable Time— 1.01— 1.16nst EBAREN Output Enable to Data Enable Time— 1.05— 1.21nst EBARDIS Output Enable to Data Disable Time—0.86—0.99nsTiming v.2.0ispXPGA Family Timing AddersParameter DescriptionBaseParameter-4-3Units Min.Max.Min.Max.Optional Adderst INDIO Input Delay—— 6.0— 6.9ns t IOI Input AdjustersLVTTL_in Using 3.3V TTL t IOIN— 0.5—0.5ns LVCMOS_18_in Using 1.8V CMOS t IOIN— 0.0—0.0ns LVCMOS_25_in Using 2.5V CMOS t IOIN— 0.3—0.3ns LVCMOS_33_in Using 3.3V CMOS t IOIN— 0.5—0.5ns AGP_1X_in Using AGP 1x t IOIN— 1.0— 1.0ns CTT25_in Using CTT 2.5V t IOIN— 1.0— 1.0ns CTT33_in Using CTT 3.3V t IOIN— 1.0— 1.0ns GTL+_in Using GTL+t IOIN— 0.5—0.5ns HSTL_I_in Using HSTL 2.5V, Class I t IOIN—0.5—0.5ns HSTL_III_in Using HSTL 2.5V, Class III t IOIN—0.5—0.5ns LVDS_in Using Low VoltageDifferential Signaling (LVDS)t IOIN— 0.8—0.8nsBLVDS_in Using Bus Low VoltageDifferential Signaling (BLVDS)t IOIN—0.8—0.8ns LVPECL_in Using Low Voltage PECL t IOIN— 0.8—0.8ns PCI_in Using PCI t IOIN— 1.0— 1.0ns SSTL2_I_in Using SSTL 2.5V, Class I t IOIN— 0.8—0.8ns SSTL2_II_in Using SSTL 2.5V, Class II t IOIN— 0.5—0.5ns SSTL3_I_in Using SSTL 3.3V, Class I t IOIN— 0.8—0.8ns SSTL3_II_in Using SSTL 3.3V, Class II t IOIN— 0.8—0.8ns t IOO Output AdjustersSlow Slew Using Slow Slew (LVTTL andLVCMOS Outputs only)t IOBUF, t IOEN—0.7—0.7nsLVTTL_out Using 3.3V TTL Drive t IOBUF, t IOEN,t IODIS— 1.0 — 1.0 nsLVCMOS_18_4mA_out Using 1.8V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.8—0.8nsLVCMOS_18_5.33mA_out Using 1.8V CMOS Standard,5.33mA Drive t IOBUF, t IOEN,t IODIS—0.6—0.6nsLVCMOS_18_8mA_out Using 1.8V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.0—0.0nsLVCMOS_18_12mA_out Using 1.8V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.2—0.2nsLVCMOS_25_4mA_out Using 2.5V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.7—0.7nsLVCMOS_25_5.33mA_out Using 2.5V CMOS Standard,5.33 mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_8mA_out Using 2.5V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_12mA_out Using 2.5V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_16mA_out Using 2.5V CMOS Standard,16mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_33_4mA_outUsing 3.3V CMOS Standard, 4mA Drive t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drivet IOBUF , t IOEN, t IODIS —0.7—0.7ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns AGP_1X_out Using AGP 1x Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT25_out Using CTT 2.5V t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT33_out Using CTT 3.3V t IOBUF , t IOEN, t IODIS—0.5—0.5ns GTL+_out Using GTL+t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_I_out Using HSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_III_out Using HSTL 2.5V , Class III t IOBUF , t IOEN, t IODIS—0.5—0.5ns LVDS_out Using Low Voltage Differen-tial Signaling (LVDS)t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns BLVDS_out Using Bus Low Voltage Differ-ential Signaling (BLVDS)t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVPECL_out Using Low Voltage PECL t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns PCI_out Using PCI Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_I_out Using SSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_II_out Using SSTL 2.5V , Class II t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_I_out Using SSTL 3.3V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_II_outUsing SSTL 3.3V , Class IIt IOBUF , t IOEN, t IODIS—0.5—0.5nsTiming v.2.0ispXPGA Family Timing Adders (Continued)ParameterDescriptionBase Parameter-4-3Units Min.Max.Min.Max.。

TS78L18CXRF资料

TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTO-92SOT-23 SOP-8SOT-89General DescriptionThe TS78L00 Series of positive voltage Regulators are inexpensive, easy-to-use devices suitable for a multitude of applications that require a regulated supply of up to 100mA. Like their higher power TS7800 and TS78M00 Series cousins, these regulators feature internal current limiting and thermal shutdown making them remarkably rugged. No external components are required with the TS78L00 devices in many applications.These devices offer a substantial performance advantage over the traditional zener diode-resistor combination, as output impedance and quiescent current are substantially reduced.Features● Output Voltage Range 3.3 to 24V ● Output current up to 100mA ● No external components required ● Internal thermal overload protection ● Internal short-circuit current limiting ● Output transistor safe-area compensation ● Output voltage offered in 4% toleranceOrdering InformationPart No.PackagePackingTS78L xx CT B0 TO-92 1Kpcs / Bulk TS78L xx CT A3 TO-92 2Kpcs/ Ammo TS78L xx ACY RM SOT-89 1Kpcs / 7” Reel TS78L xx CY RM SOT-89 1Kpcs / 7” Reel TS78L xx CS RL SOP-8 2.5Kpcs / 13” Reel TS78L xx CX RF SOT-23 3Kpcs / 7” Reel Note: Where xx denote voltage optionStandard Application CircuitAbsolute Maximum Rating (Ta = 25o C unless otherwise noted)ParameterSymbolLimitUnitTS78L0330 TS78L05 ~ TS78L18 35 DC Input Voltage TS78L24V IN40V Power DissipationP D Internal Limited WOperating Junction Temperature T J 0 ~ +125 oC Storage Temperature Range T STG-65~+150o CA common ground is required between the input and the output voltages. The input voltage must remain typically 2.0V above the output voltage even during the low point on the Input ripple voltage.XX = these two digits of the type number indicate voltage. * = Cin is required if regulator is located an appreciabledistance from power supply filter. ** = Co is not needed for stability; however, it does improvetransient response.Pin Definition: 1. Output 2. Ground3. InputPin Definition:1. Output 8. Input2. Ground 7. Ground3. Ground 6. Ground4. N/C5. N/CPin Definition: 1. Output2. Input3. GroundPin Definition:TS78L00ACY 1. Output 2. Ground 3. InputTS78L00CY 1. Input 2. Ground 3. OutputTS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTS78L03 Electrical Characteristics(Vin=8.3V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC3.173 3.3 3.432 Output voltageVout5.8V ≤Vin ≤20V, 5mA ≤Iout ≤100mA 3.142 3.3 3.465 VLine Regulation REGline Tj=25oC 5.8V ≤Vin ≤20V Iout=40mA-- 50 150 5mA ≤Iout ≤100mA-- 15 60 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 5 30 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6 5.8V ≤Vin ≤20V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 40 -- µV Ripple Rejection Ratio RR f=120Hz, 5.8V ≤Vin ≤20V 41 49 -- dB Voltage DropVdrop Iout=100mA, Tj=25oC-- 2 -- V Peak Output CurrentIo peakTj=25oC-- 0.15 -- A Temperature Coefficient ofOutput VoltageΔVout/ ΔTjIout=5mA, 0oC ≤Tj ≤125o C---0.2--mV/ oCTS78L05 Electrical Characteristics(Vin=10V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC4.80 55.20 Output voltageVout7.5V ≤Vin ≤20V, 5mA ≤Iout ≤100mA 4.75 5 5.25 VLine Regulation REGline Tj=25oC 7.5V ≤Vin ≤20V Iout=100mA-- 50 150 5mA ≤Iout ≤100mA-- 20 60 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 10 30 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6 7.5V ≤Vin ≤20V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 40 -- µV Ripple Rejection RatioRRf=120Hz, 7.5V ≤Vin ≤20V4149--dBVoltage Drop Vdrop Iout=100mA, Tj=25oC -- 1.7 -- VPeak Output Current Io peak Tj=25oC -- 0.15 -- A Temperature Coefficient of Output VoltageΔVout/ ΔTj Iout=5mA, 0o C ≤Tj ≤125o C -- -0.65 -- mV/oC● Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible, and thermal effects must be taken into account separately.● This specification applies only for DC power dissipation permitted by absolute maximum ratings.TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTS78L06 Electrical CharacteristicsVin=12V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC5.76 66.24 Output voltageVout8.5V ≤Vin ≤21V, 5mA ≤Iout ≤100mA5.70 66.30 VLine Regulation REGline Tj=25oC8.5V ≤Vin ≤21V Iout=40mA-- 50 150 5mA ≤Iout ≤100mA -- 12 60 Load Regulation REGloadTj=25oC5mA ≤Iout ≤40mA -- 4 30 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6 8.5V ≤Vin ≤21V-- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA-- -- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 40 -- µV Ripple Rejection Ratio RR f=120Hz, 8.5V ≤Vin ≤21V41 49 -- dB Voltage DropVdropIout=100mA, Tj=25oC -- 1.7 -- V Peak Output Current Io peak Tj=25oC-- 0.15 -- A Temperature Coefficient ofOutput VoltageΔVout/ ΔTjIout= 5mA, 0oC ≤Tj ≤125oC---0.75--mV/oCTS78L08 Electrical CharacteristicsVin=14V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC7.69 8 8.32 Output voltageVout10.5V ≤Vin ≤23V, 5mA ≤Iout ≤100mA 7.61 8 8.40 VLine Regulation REGline Tj=25oC 10.5V ≤Vin ≤23V Iout=40mA-- 80 160 5mA ≤Iout ≤100mA-- 25 80 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 10 40 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6 10.5V ≤Vin ≤23V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 60 -- µV Ripple Rejection RatioRRf=120Hz, 10.5V ≤Vin ≤23V3757--dBVoltage Drop Vdrop Iout=100mA, Tj=25oC -- 1.7 -- VPeak Output Current Io peak Tj=25oC -- 0.15 -- A Temperature Coefficient of Output VoltageΔVout/ ΔTj Iout=5mA, 0o C ≤Tj ≤125o C -- -0.8 -- mV/oC● Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible, and thermal effects must be taken into account separately.● This specification applies only for DC power dissipation permitted by absolute maximum ratings.TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTS78L09 Electrical CharacteristicsVin=15V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC8.65 9 9.36 Output voltageVout11.5V ≤Vin ≤23V, 5mA ≤Iout ≤100mA8.57 9 9.45 VLine Regulation REGline Tj=25oC11.5V ≤Vin ≤23V Iout=40mA -- 90 180 5mA ≤Iout ≤100mA -- 30 90 Load Regulation REGloadTj=25oC5mA ≤Iout ≤40mA-- 15 45 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6 11.5V ≤Vin ≤23V-- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA-- -- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 60 -- µV Ripple Rejection Ratio RR f=120Hz, 11.5V ≤Vin ≤23V37 57 -- dB Voltage DropVdropIout=100mA, Tj=25oC -- 1.7 -- V Peak Output Current Io peak Tj=25oC--0.15 -- A Temperature Coefficient ofOutput VoltageΔVout/ ΔTjIout=5mA, 0oC ≤Tj ≤125oC---0.9--mV/oCTS78L12 Electrical CharacteristicsVin=19V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC11.53 12 12.48 Output voltageVout14.5V ≤Vin ≤27V, 5mA ≤Iout ≤100mA11.42 12 12.60 VLine Regulation REGline Tj=25oC14.5V ≤Vin ≤27V Iout=40mA-- 120 240 5mA ≤Iout ≤100mA -- 40 120 Load Regulation REGloadTj=25oC5mA ≤Iout ≤40mA -- 20 60 mVQuiescent Current Iq Iout=0, Tj=25oC-- 3 6.5 14.5V ≤Vin ≤27V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA-- -- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 80 -- µV Ripple Rejection Ratio RR f=120Hz, 14.5V ≤Vin ≤27V37 42 -- dB Voltage DropVdropIout=100mA, Tj=25oC--1.7--VPeak Output Current Io peak Tj=25oC -- 0.15 -- A Temperature Coefficient of Output VoltageΔVout/ ΔTj Iout=5mA, 0o C ≤Tj ≤125o C -- -1.0 -- mV/oC● Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible, and thermal effects must be taken into account separately.● This specification applies only for DC power dissipation permitted by absolute maximum ratings.TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTS78L15 Electrical CharacteristicsVin=23V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC14.42 15 15.60 Output voltageVout17.5V ≤Vin ≤30V, 5mA ≤Iout ≤100mA 14.28 15 15.75 VLine Regulation REGline Tj=25oC 17.5V ≤Vin ≤30V Iout=40mA-- 150 300 5mA ≤Iout ≤100mA-- 50 150 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 25 75 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6.6 17.5V ≤Vin ≤30V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 90 -- µV Ripple Rejection RatioRRf=120Hz, 17.5V ≤Vin ≤30V 34 39 -- dB Voltage Drop Vdrop Iout=100mA, Tj=25oC-- 1.7 -- V Peak Output Current Io peak Tj=25oC-- 0.15 -- A Temperature Coefficient ofOutput VoltageΔVout/ ΔTjIout=5mA, 0oC ≤Tj ≤125o C---1.3--mV/ oCTS78L18 Electrical CharacteristicsVin=27V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC17.30 18 18.72 Output voltageVout21V ≤Vin ≤33V, 5mA ≤Iout ≤100mA 17.14 18 18.90 VLine Regulation REGline Tj=25oC21≤Vin ≤33V Iout=40mA-- 180 360 5mA ≤Iout ≤100mA-- 60 180 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 30 90 mVQuiescent Current Iq Iout=0, Tj=25oC -- 3 6.5 21V ≤Vin ≤33V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 150 -- µV Ripple Rejection Ratio RR f=120Hz, 21V ≤Vin ≤33V 33 48 -- dB Voltage DropVdrop Iout=100mA, Tj=25oC-- 1.7 -- V Peak Output CurrentIo peakTj=25oC-- 0.15 -- A Temperature Coefficient ofOutput VoltageΔVout/ ΔTjIout=5mA, 0oC ≤Tj ≤125o C---1.5--mV/oC● Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible, and thermal effects must be taken into account separately.● This specification applies only for DC power dissipation permitted by absolute maximum ratings.TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTS78L24 Electrical CharacteristicsVin=33V, Iout=40mA, 0oC ≤Tj ≤125oC, Cin=0.33uF, Cout=0.1uF; unless otherwise specified.)ParameterSymbolTest ConditionMinTypMaxUnitTj=25oC23.07 24 24.96 Output voltageVout27V ≤Vin ≤38V, 5mA ≤Iout ≤100mA 22.85 24 25.20 VLine Regulation REGline Tj=25oC 27≤Vin ≤38V Iout=40mA-- 200 400 5mA ≤Iout ≤100mA-- 80 240 Load Regulation REGloadTj=25o C5mA ≤Iout ≤40mA -- 40 120 mVQuiescent Current Iq Iout=0, Tj=25oC -- 4 7 27V ≤Vin ≤38V -- -- 1.5 Quiescent Current Change ΔIq 5mA ≤Iout ≤40mA---- 0.1 mA Output Noise Voltage Vn 10Hz ≤f ≤100KHz, Tj=25oC -- 200 -- µV Ripple Rejection RatioRRf=120Hz, 27V ≤Vin ≤38V3145--dBVoltage Drop Vdrop Iout=100mA, Tj=25oC -- 1.7 -- VPeak Output Current Io peak Tj=25oC -- 0.15 -- A Temperature Coefficient of Output VoltageΔVout/ ΔTj Iout=5mA, 0o C ≤Tj ≤125o C -- -2.0 -- mV/oC● Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible, and thermal effects must be taken into account separately.● This specification applies only for DC power dissipation permitted by absolute maximum ratings.TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorApplication InformationDesign ConsiderationsThe TS78L00 Series of fixed voltage regulators are designed with Thermal Overload Protection that shuts down the circuit when subjected to an excessive power overload condition. Internal Short Circuit protection Limits the maximum current the circuit will pass.In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with a capacitor if the regulator is connected to the power supply filter with long wire lengths, or if the output load capacitance is large. The input bypass capacitor should be selected to provide good high-frequency characteristics to insure stable operation under all load conditions. A 0.33uF or larger tantalum, mylar, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulators input terminals. Good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. Bypassing the output is also recommended.FIGURE 2 – ±15V Tracking Voltage RegulatorFIGURE 7 – Current RegulatorThe TS78L00 regulators can also be used as a current source when connected as above. In order to minimize dissipation the TS78L05 is chosen in this application. Resistor R determines the current as follows:I IB =3.8mA over lined and load changesFor example, a 100mA current source would require R tobe a 50Ω. 1/2W resistor and the output voltage compliancewould be the input voltage less 7V.FIGURE 8 – ±15V Tracking Voltage RegulatorTS78L00 Series3-Terminal 100mA Positive Voltage RegulatorTO-92 Mechanical DrawingMarking DiagramXX = Output Voltage(03=3.3V, 05=5V, 06=6V, 08=8V, 09=9V, 12=12V, 15=15V, 18=18V, 24=24V) Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L= Lot CodeTO-92 DIMENSION MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.30 4.70 0.169 0.185 B 4.30 4.70 0.169 0.185 C 14.30(typ) 0.563(typ) D 0.43 0.49 0.017 0.019 E 2.19 2.81 0.086 0.111 F 3.30 3.70 0.130 0.146 G 2.42 2.66 0.095 0.105 H0.37 0.43 0.015 0.017TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorSOT-89 Mechanical DrawingMarking DiagramXX = Output Voltage(03=3.3V, 05=5V, 06=6V, 08=8V, 09=9V, 12=12V, 15=15V, 18=18V, 24=24V) Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L = Lot CodeXX = Output Voltage(03=3.3V, 05=5V, 06=6V, 08=8V, 09=9V, 12=12V, 15=15V, 18=18V, 24=24V) Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L = Lot CodeSOT-89 DIMENSION MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.40 4.60 0.173 0.181 B 1.50 1.7 0.059 0.070 C 2.30 2.60 0.090 0.102 D 0.40 0.52 0.016 0.020 E 1.50 1.50 0.059 0.059 F 3.00 3.00 0.118 0.118 G 0.89 1.20 0.035 0.047 H 4.05 4.25 0.159 0.167 I 1.4 1.6 0.055 0.068 J0.35 0.44 0.014 0.017TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorSOP-8 Mechanical DrawingMarking DiagramXX = Output Voltage(03=3.3V, 05=5V, 06=6V, 08=8V, 09=9V, 12=12V, 15=15V, 18=18V, 24=24V) Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L= Lot CodeSOP-8 DIMENSION MILLIMETERS INCHES DIM MIN MAX MIN MAX. A 4.80 5.00 0.189 0.196 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049G 1.27BSC 0.05BSC K 0.10 0.25 0.004 0.009 M 0º 7º 0º 7º P 5.80 6.20 0.229 0.244 R0.25 0.50 0.010 0.019TS78L00 Series3-Terminal 100mA Positive Voltage RegulatorSOT-23 Mechanical DrawingMarking DiagramL3 = Device Voltage Code(L3=3.3V, L5=5V, L6=6V, L8=8V, L9=9V, L1=10V, L2=12V, A=15V, D=18V, J=24V) Y = Year Code M = Month Code(A =Jan, B =Feb, C =Mar, D =Apl, E =May, F =Jun, G =Jul, H =Aug, I =Sep, J =Oct, K =Nov, L =Dec) L = Lot CodeSOT-23 DIMENSION MILLIMETERS INCHES DIM MIN MAX MIN MAX.A 0.95 BSC 0.037 BSC A1 1.9 BSC 0.074 BSCB 2.60 3.00 0.102 0.118C 1.40 1.70 0.055 0.067D 2.80 3.10 0.110 0.122E 1.00 1.30 0.039 0.051F 0.00 0.10 0.000 0.004G 0.35 0.50 0.014 0.020H 0.10 0.20 0.004 0.008I 0.30 0.60 0.0120.024 J5º10º5º10ºTS78L00 Series3-Terminal 100mA Positive Voltage RegulatorNoticeSpecifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale.。

9M31中文资料

元器件交易网源自元器件交易网9M31
X-Band Magnetron
9M31 is a fixed frequency pulsed type X-band magnetron, designed to operate in the frequency range of 9.38 to 9.44GHz with a peak output power of 50kW. It is packaged and waveguide output type and forced air cooled. ---- MAXIMUM RATINGS ---Peak anode current Peak anode power input Duty cycle Pulse duration Rate of rise of voltage pulse Anode temperature V.S.W.R. at the output coupler ---- ELECTRICAL ---Heater voltage (Note 1) 6.3 Preheat time Peak anode voltage (Note 2) 12.0 Peak output power (Note 2) Frequency (Note2) Note: 1. Measured with heater voltage of 6.3V and no anode input power, the heater current limits are 0.9A minimum, 1.1A maximum. For average pulse input powers less than 150 watts, the heater voltage must be reduced within 3 seconds after the application of h. t. according to the following schedule: Pi Volts 150 (Pi=mean input power in watts.) Ef = 6.3 1 − 2. Measured at peak anode current 12.0A. For further information on the use of the magnetron, Please contact New JRC. New JRC reserves the right to change the specification of goods without notice. Rev.1 Min 5.7 120 11.0 40 9.38 Typical Max 6.9 13.0 9.44 Unit V S kV kW GHz Min 3.5 Max 16.0 230 0.001 2.5 100 100 1.5:1 Unit A kW us kV/us degree centigrade -

宝马3系E91手册技术资料：mfp-tnu_e91_arbeitsbuch_en

WorkbookE91 Complete vehicleBMW ServiceThe information contained in this document is intended for BMW Aftersales staff.Refer to the latest relevant "BMW Service" information for any changes/supplements to the Technical Data.Information status: June 2005conceptinfo@bmw.de© 2005 BMW AGAftersales Training, München, Germany.Reprints of this manual or its parts require the written approval of BMW AG,München.WorkbookE91 Complete vehicleContentsE91 Complete vehicle Test questions119Workbook E91 BodyWorksheet 1: Introduction The new BMW 3 Series Touring (E91) will celebrate its world premiere at the International Motor Show in Frankfurt (15th to 29th September 2005).The market introduction in Europe will take place parallel to this event: The fourth generation of the "small" Touring will be available at the dealers as from 17th September.As no other vehicle in its class, the new 3Series Touring offers new dimensions in styling,flexibility and performance.It combines high performance driving dynamics with functional versatility.With these performance features it will assume a leading role in this highly competitive market.Time: 15 minutes Have a good look at the car and make a note of all the technical highlights you do not recognize from the E90.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________9 Worksheet 2: BodyThe panorama sunroof on the E91is designed as an inner-running slide/tilt sunroof with two glass panels and two floating rooflines.By increasing the glass area by about 140% compared to the slide/tilt sunroof on the E46/ 3,the panorama sunroof enhances the feeling for space both for those seated in the front as well as for the rear occupants.Although the E91panorama sunroof is based on that of the E83, it does feature several distinctive changes. The 50mm wide air gap is located at the front and not between the floating rooflines as on the E83. The wind deflector is moved by the floating roofline motor in connection with a sophisticated mechanism. The wind deflector is controlled in relation to the speed.It therefore effectively eliminates the low-frequency drumming that occurs at a speed of approx.70km/h as well as the high-frequency noise at speeds above 120km/h. This is achieved by the net-type wind deflector assuming two different height settings thus effectively counteracting the respective noise disturbance.The glass panels, floating rooflines and wind deflector function fully electronically and are operated by means of standard BMW sunroof controls in the form of a switch integrated in the roof functions centre.Time: 10 minutesUsing the repair instructions, adjust the panorama sunroof panels correctly.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________239Worksheet 3: Body Both glass panels of the E91 panorama sunroof can be disassembled. The mounting screws must be released also when adjusting the panels.The two floating rooflines can also be removed. In addition, the two electric motors and the wind deflector can be removed and installed with the panorama sunroof module installed in place.If problems arise regarding the cableassemblies,it is recommenced to replace the complete module.Time: 10 minutes Using the repair instructions, remove both glass panels of the panorama sunroof.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________49Worksheet 4: BodyTime: 10 minutes 1 -Individual components of the panorama sunroof Using the repair instructions, remove both floating rooflines of the E91 panorama sunroof.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________Worksheet 5: Body Time: 5 minutesExpose the front drive motor of the panorama sunroof so that the hole for emergencyoperation is accessible.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________56Worksheet 6: BodyTime: 20 minutes 2 -Panorama sunroof E91Using the repair instructions,reassemble the panorama sunroof so that it is fully operable and correctly adjust the panels.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________Worksheet 7: Body Time: 5 minutesUsing the repair instructions, install the panorama sunroof.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________78Worksheet 8: BodyTime: 5 minutes 3 -Panorama sunroof E91Perform the emergency closing operation for the panorama sunroof.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________9Worksheet 9: Body Time: 10 minutes 4 -E91 Luggage compartmentRemove the combination roller blind and fold down the back seats. Locate the wetcompartment, tool kit and the operating button for the towing hitch.Locate the components 1 to 13 and name them.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________10Worksheet 10: BodyCombination roller blind •Roller blind cover with convenient opening function •Net partition function for load area •Net partition function for load area with backrests folded down Roller blind cover with convenient opening function When the retaining fixture for the roller blind cover is released automatically, the holding rod moves upward in the guide rails on the left and right together with the roller blind cover,opening up the load area. This makes it possible for the customer to load the luggage compartment by opening the rear window.This function is also activated by opening the rear hatch, allowing the customer to conveniently place and store items of luggage in the luggage compartment.Time: 15 minutes 5 -Automatic operation of the roller blind cover when opening thewindow/rear hatch Establish the relationship between opening the rear hatch/rear window and the combination roller e the system schematic for this purpose and verify your findings on the vehicle.Notes: ____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________Worksheet 11: Electrical/electronic systems Time: 10 minutesUsing the system schematic, work out the functional principle of the panorama sunroofelectrical system.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________11126 -System schematic - panorama sunroof13Worksheet 12: Electrical/electronic systems Time: 10 minutes 7 -Example of the signal progression when releasing the rear hatch or rear window Index Explanation Index Explanation1Identification transmitter 6Central locking, rear hatch 2Rear window antenna 7Central locking, rear window3Remote control receiver in diversity module 8Release for combination roller blind,left4Car access system 2 CAS 29Release for combination roller blind,right5Junction box JB K-CAN Body CANUsing the system schematic,work out the electrical functional principle of the central locking system.Notes:________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________14ContentsE91 SummarySummary1 Overview of the most important features.119Summary E91 Complete vehicleOverview of the most important features.The most important aspects of the E91electrical/electronic systems are summarized in the following table.This list provides you with the most important details in concise form and also enables you to once again check the most important points of this participant's manual.Vehicle systems network Bus systemsThe systemnetwork ofthe E91is essentially the same as those of theE90.The bus systems have been adopted from the E90and adapted to therequirements of the E91.The control unit for the panorama glass sunroof is a new addition tothe bus system and is located on the K-CAN.Power supplyThe power supply system has been adopted from the E90.Energy managementThe power management from the E90 is used in the E91 and theterminal 30g concept has been extended.Even more control units are now incorporated in the terminal 30gconcept. These control units are:•Panorama glass sunroof MDS•Seat heating SH•Active steering AL•Longitudinal dynamics management LDM•Electric fuel pump control unit EKP•Electronic transmission control EGS•Active cruise control 2ACC 2•Satellite radio (SDARS) only for US vehicles•Digital radio (IBOC In Band On Channel) only for US vehicles.。

DS90C385AMTX中文资料

µA
31
45
mA
37
50
mA
48
60
mA
55
65
mA

2
DS90C385A
元器件交易网
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Duration
Continuous
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)
+260˚C
Maximum Package Power Dissipation Capacity @ 25˚C
f = 25 MHz f = 40 MHz f = 65 MHz f = 87.5 MHz
Min Typ Max Units
2.0
VCC
V
0
0.8
V
−0.79 −1.5
V
+1.8 +10
µA
−10
0
µA
250 345 450
mV
35
mV
1.13 1.25 1.38
V
35
mV
−3.5 −5
mA
±1 ±10
Block Diagram
DS90C385A
Order Number DS90C385AMT See NS Package Number MTD56

VCD维修资料数据

主2006-4-270:34:06VCD维修数据资料下载引脚数据大全振峰会员提供资料整理制作，我给他加10分了,有资料的请提供我会加分的。

[ 本贴由马生于04-5-15 20:53 最后编辑]#2 2006-4-27 0:34:20 VCD维修数据资料下载引脚数据大全在那里呢？？#3 2006-4-27 0:35:11 索引第一章看视盘机电路图的基本任务和方法第二章看视盘机电路图的基础知识第三章 ESS+SAMSUNG方案系列VCD影碟机第四章 SUNPLUS+PHILIPS方案系列VCD影碟机第五章 ESS+MTK方案系列DVD影碟机第六章 SOC方案（MTK1369）系列DVD影碟机第七章 ESS+Panasonic方案系列DVD影碟机第八章ESS+ALI方案系列DVD影碟机附表1：VCD-330G功能引脚及实测电压参考值KB9223：RF处理KS9284：伺服处理、DSP处理KA9259D：五通道伺服驱动放大ICESS3207：音视频数模转换及CPU功能ES3210：MPEG-1解码附表2：DVD-880功能引脚及实测电压参考值MT1366：RF放大处理、自动激光功率控制 MT1388：SSP、DSP处理 24C02：电可擦写可编程储存器CS4334：两声道音频数模转换IC CS4955：视频编码、视频DAC附表3：DVD-510功能引脚及实测电压参考值MN102H60EGA：伺服控制CPU MN103S26EGA：DSP、SSP处理ES6018：解码处理24C02：电可擦写可编程储存器AV2188：六声道音频数模转换IC附表4：DVD-948P功能引脚及实测电压参考值SP-3721A(M5703)：RF放大处理M5705：伺服DSP处理BA5954FP：四通道伺服驱动放大ICBA6849FP：主轴电机驱动集成电路MC3472：高速处理放大器ES6028：解码处理AV2188：六声道音频数模转换IC第一章看视盘机电路图的基本任务和方法CD唱机和VCD视盘机已经进入普通百姓家庭，DVD视盘机也开始大量普及，各种兼容性激光视盘机纷纷登场。

珍贵资料-cy7c68013中文手册

CY7C68013A, CY7C68014ACY7C68015A, CY7C68016A EZ-USB FX2LP (TM) USB 微控制器高速 USB 外设控制器1. 特色 (CY7C68013A/14A/15A/16A)■USB 2.0 USB IF 高速性能且经过认证 (TID # 40460272)■单芯片集成 USB 2.0 收发器、智能串行接口引擎 (SIE) 和增强型 8051 微处理器■适用性、外观和功能均与FX2兼容❐引脚兼容❐目标代码兼容❐功能兼容（FX2LP 是超集）■超低功耗：I CC在任何模式下都不超过 85 mA❐适合总线和电池供电的应用■软件：8051 代码运行介质：❐内部 RAM，通过 USB 下载❐内部 RAM，从 EEPROM 加载❐外部存储设备（128 引脚封装）■16 K 字节片上代码/数据 RAM■四个可编程的 BULK/INTERRUPT/ISOCHRONOUS 端点❐缓冲区大小选项：两倍，三倍，四倍■附加的可编程(BULK/INTERRUPT) 64 位端点■8 位或 16 位外部数据接口■可生成智能介质标准错误校正码 ECC ■通用可编程接口 (General Programmable Interface，GPIF)❐可与大多数并行接口直接连接❐由可编程波形描述符和配置寄存器定义波形❐支持多个 Ready (RDY) 输入和 Control (CTL) 输出■符合行业标准的集成增强型 8051❐48 MHz、24 MHz 或 12 MHz CPU 操作❐每个指令周期四个时钟❐两个 USART❐三个计数器/定时器❐扩展的中断系统❐两个数据指针■3.3V 工作电压，容限输入为 5V■向量化 USB 中断和 GPIF/FIFO 中断■分离的 CONTROL 传输设置部分和数据部分数据缓冲■集成 I2C 控制器，在 100 或 400 kHz 下运行■集成的四个先进先出 (FIFO) 缓冲❐集成胶合逻辑和 FIFO 有助于降低系统成本❐与 16 位总线之间的自动转换❐可主-从操作❐使用外部时钟或异步选通脉冲❐易于与 ASIC 和 DSP IC 相连的接口■有商业和工业温度等级供选择（除 VFBGA 外的所有封装）1.1 特色（仅限 CY7C68013A/14A ）■CY7C68014A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68013A ：适合非电池供电应用❐挂起电流：300 μA (typ)■有五种无铅封装供选择，可包含多达 40 个 GPIO ❐128 引脚 TQFP （40 个 GPIO ）、100 引脚 TQFP （40 个 GPIO ）、56 引脚 QFN （24 个 GPIO ）、56 引脚 SSOP （24 个 GPIO ）和 56 引脚 VFBGA （24 个 GPIO ）1.2 特色（仅限 CY7C68015A/16A ）■CY7C68016A ：适合电池供电应用❐挂起电流：100 μA (typ)■CY7C68015A ：适合非电池供电应用❐挂起电流：300 μA (typ)■采用无铅 56 引脚 QFN 封装（26 个 GPIO ）❐比 CY7C68013A/14A 多 2 个 GPIO ，可在同样的空间内实现额外的功能赛普拉斯半导体公司（赛普拉斯）的 EZ-USB FX2LP ™ (CY7C68013A/14A) 是高集成、低功耗 USB 2.0 微控制器EZ-USB FX2™ (CY7C68013) 的一个低功耗版本。

UXB02070G9CRP00中文资料

For technical questions, contact: ff3cresistors@Document Number: 28726UXA 0204, UXB 0207, UXE 0414Vishay BeyschlagHigh Precision Leaded ResistorsDESCRIPTIONUXA 0204, UXB 0207 and UXE 0414 high precision leaded thin film resistors combine the proven reliability of the professional products with an exceptional level of precision and stability. Therefore they are perfectly suited for applications in the fields of precision test and measuring equipment and particularly for the design of calibration references and standards.FEATURES•Superior thin film technology•Exceptional low TCR: ± 02 ppm/K to ± 10 ppm/K •Super tight tolerance: ± 0.01 % to ± 0.25 %•Exceptional overall stability: class 0.02•Wide resistance range: 22 Ω to 1 M Ω•Lead (Pb)-free solder contacts•Pure tin plating provides compatibility with lead (Pb)-free and lead containing soldering processes•Compatible with “Restriction of the use of Hazardous Substances” (RoHS) directive 2002/95/EC (issue 2004)APPLICATIONS•Precision test and measuring equipment•Design of calibration references and standardsMETRIC SIZEDIN:020*********CECC:ABDTECHNICAL SPECIFICATIONSDESCRIPTION UXA 0204UXB 0207UXE 0414CECC size AB DResistance range 22 Ω to 221 k Ω10 Ω to 1 M Ω22 Ω to 511 k ΩResistance tolerance ± 0.25 %; ± 0.1 %; ± 0.05 %; ± 0.01 %± 0.1 %; ± 0.05 %Temperature coefficient ± 10ppm/K; ± 05ppm/K; ± 02ppm/K ± 10ppm/K; ± 05ppm/KOperation modeprecision precision precision Climatic category (LCT/UCT/days)20/125/5620/125/5620/125/56Rated dissipation:P 850.05W 0.125 W 0.25 W P 700.1 W 0.25W 0.5W Operating voltage, U max AC/DC 200 V 250 V 300 V Film temperature125°C 125°C 125°C Max. resistance change at P 70for resistance range, ΔR /R max., after:100 Ωto 100 k Ω100 Ωto 250 k Ω100 Ωto 100 k Ω2000h≤ 0.05 %≤ 0.05 %≤ 0.05 %Max. resistance change at P 85for resistance range, ΔR /R max., after:100 Ωto 100 k Ω100 Ωto 250 k Ω100 Ωto 100 k Ω1000h ≤ 0.02 %≤ 0.02 %≤ 0.02 %8000h ≤ 0.04 %≤ 0.04 %≤ 0.04 %225000h≤ 0.12 %≤ 0.12 %≤ 0.12 %Specified lifetime225 000h225 000h225 000hPermissible voltage against ambient :1 minute 300V 500V 800V continuous75V 75V 75V Failure rate≤ 0.7 x 10-9/h≤ 0.3 x 10-9/h≤ 0.1 x 10-9/hDocument Number: 28726For technical questions, contact: ff3cresistors@UXA 0204, UXB 0207, UXE 0414High Precision Leaded ResistorsVishay Beyschlag12NC INFORMATIONComponents may be ordered by using either a simple clear text ordering code, see “Type Description and Ordering Code” or Vishay BCcomponents’ unique 12NC.Numeric Ordering Code (12NC)•The resistors have a 12-digit Part Number starting with 2312.•The subsequent 4digits indicate the resistor type,specification and packaging; see the 12NC Part Number table.•The remaining 4digits indicate the resistance value:–The first 3digits indicate the resistance value.–The last digit indicates the resistance decade in accordance with the 12NC Indicating Resistance Decade table.Last Digit of 12NC Indicating Resistance Decade12NC ExampleThe Part Number of a UXA 0204 resistor, value 47 k Ω and TCR 10 with ± 0.1 % tolerance, supplied on bandolier in a box of 1000 units is: 2312 662 34703.Note:(1) Readable 12NC coding of resistance values is restricted to values with three significant digits. For resistance values with more than three significant digits, a non readable sequential number will be issued by the factory for each requested combination of resistance value and tolerance.RESISTANCE DECADELAST DIGIT10 Ωto 99.9 Ω9100 Ωto 999 Ω11 k Ω to 9.99 k Ω210 k Ωto 99.9 k Ω3100k Ω to 999 k Ω412NC PART NUMBER - resistor type and packagingDESCRIPTIONORDERING CODE 2312........BANDOLIER IN BOX BANDOLIER IN BOX BANDOLIER ON REEL BANDOLIER ON REEL BANDOLIER ON REEL TYPETCRTOL.CU 100 units C1 1000 units R1 1000 units R2 2500 units RP 5000 units UXA 0204± 10 ppm/K± 0.25 %562 2....662 2....462 2....--± 0.1 %562 3....662 3....462 3....--± 0.05 %562 4....662 4....462 4....--± 0.01 %562 7....662 7....462 7....--(1)562 91...662 91...462 91...--± 05 ppm/K± 0.25 %563 2....663 2....463 2....--± 0.1 %563 3....663 3....463 3....--± 0.05 %563 4....663 4....463 4....--± 0.01 %563 7....663 7....463 7....--(1)563 91...663 91...463 91...--± 02 ppm/K± 0.25 %564 2....664 2....464 2....--± 0.1 %564 3....664 3....464 3....--± 0.05 %564 4....664 4....464 4....--± 0.01 %564 7....664 7....464 7....--(1)564 91...664 91...464 91...--UXB 0207± 10 ppm/K± 0.25 %572 2....672 2....472 2....-577 2....± 0.1 %572 3....672 3....472 3....-577 3....± 0.05 %572 4....672 4....472 4....-577 4....± 0.01 %572 7....672 7....472 7....-577 7. (1)572 91...672 91...472 91...-577 91...± 05 ppm/K± 0.25 %573 2....673 2....473 2....-578 2....± 0.1 %573 3....673 3....473 3....-578 3....± 0.05 %573 4....673 4....473 4....-578 4....± 0.01 %573 7....673 7....473 7....-578 7. (1)573 91...673 91....473 91...-578 91...± 02 ppm/K± 0.25 %574 2....674 2....474 2....-579 2....± 0.1 %574 3....674 3....474 3....-579 3....± 0.05 %574 4....674 4....474 4....-579 4....± 0.01 %574 7....674 7....474 7....-579 7. (1)574 91...674 91...474 91...-579 91...UXE 0414± 10 ppm/K± 0.1 %592 3....692 3....-597 3....-± 0.05 %592 4....692 4....-597 4....-(1)592 91...692 91...-597 91...-± 05 ppm/K± 0.1 %593 3....693 3....-598 3....-± 0.05 %593 4....693 4....-598 4....-(1)593 91...693 91...-598 91...- For technical questions, contact: ff3cresistors@Document Number: 28726UXA 0204, UXB 0207, UXE 0414Vishay BeyschlagHigh Precision Leaded ResistorsNotes:(1) Please refer to table PACKAGING, see next page.Products can be ordered using either the Product Description or the 12NC. The PART NUMBER is shown to facilitate the introduction of a unified part numbering system.DIMENSIONSPART NUMBER AND PRODUCT DESCRIPTION UX SERIESPart Numbering: UXB02070F1001AC100MODEL/SIZE SPECIAL CHARACTERTCRVALUETOLERANCE PACKAGINGSPECIALUXA0204UXB0207UXE04140 = neutralH = ± 2 ppm/K G = ± 5 ppm/K F = ± 10 ppm/K3 digit value 1 digit multiplier MULTIPLIER 9 = *10-1 2 = *1020 = *100 3 = *1031 = *1014 = *104T = ± 0.01 %A = ± 0.05 %B = ± 0.1 %C = ± 0.25 %C1CU R1R2RPup to 2 digits 00 = standardProduct Description: UXB 0207-10 0.05 % C1 1K0UXB 0207100.05 %C11K0MODEL SIZE TCR TOLERANCE PACKAGING (1)RESIST ANCE VALUEUXA UXB UXE020*********± 2 ppm/K ± 5 ppm/K ± 10 ppm/K± 0.01 %± 0.05 %± 0.1 %± 0.25 %C1CU R1R2RP1K0 = 1.0 k Ω47K = 47 k Ω50R5 = 50.5 ΩDIMENSIONS - leaded resistor types, mass and relevant physical dimensionsTYPE D max (mm)L max (mm)d nom (mm)I min (mm)M min (mm)MASS (mg)UXA 0204 1.6 3.60.529.0 5.0125UXB 0207 2.5 6.30.628.07.5220UXE 04144.011.90.831.015.0750SCRIPT MARKING - printed resistance value and letter coding for TCR and toleranceRESISTANCE VALUETOL.(%)LETTER CODETCR (ppm/K)LETTER CODEClear text code for value± 0.25C ± 10B ± 0.1B ± 05A ± 0.05A ± 02T ± 0.01T−−B 0200F 17UX 00A C 110Document Number: 28726For technical questions, contact: ff3cresistors@UXA 0204, UXB 0207, UXE 0414High Precision Leaded ResistorsVishay BeyschlagNotes:(1) Resistance values to be selected from the E192 series, for other values please contact the factory.(2) TCR 10 and TCR 05 are specified over the temperature range from - 20°C to + 85°C.(3) TCR 02 is specified over the temperature range from 0°C to + 60°C.DESCRIPTIONProduction is strictly controlled and follows an extensive set of instructions established for reproducibility. A homogeneous film of metal alloy is deposited on a high grade ceramic body (85 % Al 2O 3) and conditioned to achieve the desired temperature coefficient. Nickel plated steel termination caps are firmly pressed on the metallized rods.Special laser devices are used repeatedly to achieve the target value by slowly and smoothly cutting a helical groove in the resistive layer without damaging the ceramics. A further conditioning is applied in order to stabilise the trimming result. Connecting wires of electrolytic copper plated with pure tin are welded to the termination caps. The resistors are covered by protective coating designed for electrical, mechanical and climatic protection.The terminations receive a final pure tin on nickel plating. Script marking designates the resistance value plus coded TCR and tolerance.The result of the determined production is verified by an accelerated ageing (burn-in) and extensive testing procedure performed on 100 % of the individual resistors.Only accepted products are stuck directly on the adhesive tapes in accordance with IEC 60286-1.ASSEMBLYThe resistors are suitable for processing on automatic insertion equipment and cutting and bending machines.E xcellent solderability is proven, even after extended storage. They are suitable for automatic soldering using wave or dipping. The encapsulation is resistant to all cleaning solvents commonly used in the electronics industry,including alcohols, esters and aqueous solutions. The suitability of conformal coatings, if applied, shall be qualified by appropriate means to ensure the long-term stability of the whole system.APPROVALSWhere applicable, the resistors are tested in accordance with CECC 40101-806 which refers to EN 60115-1 and EN 140100.Vishay B EYSCHLAG has achieved "Approval of Manufacturer" in accordance with EN 100114-1PACKAGINGMODEL REELBOXBANDOLIER ON REELCODE PIECES/BOXCODE UXA 1000R11001000CU C1UXB 10005000R1RP 1001000CU C1UXE2500R21001000CU C1TEMPERATURE COEFFICIENT AND RESISTANCE RANGEDESCRIPTIONRESISTANCE VALUE (1)TCRTOLERANCE UXA 0204UXB 0207UXE 0414± 10 ppm/K (2)± 0.25 %22 Ω to 221 k Ω10 Ω to 1 M Ω-± 0.1 %43 Ω to 221 k Ω10 Ω to 1 M Ω22 Ω to 511k Ω± 0.05 %100 Ω to 180 k Ω24 Ω to 301 k Ω100 Ω to 301k Ω± 0.01 %200 Ω to 150 k Ω24 Ω to 301 k Ω-± 05 ppm/K (2)± 0.25 %47 Ω to 150 k Ω10 Ω to 1 M Ω-± 0.1 %47 Ω to 150 k Ω10 Ω to 1 M Ω47 Ω to 301k Ω± 0.05 %100 Ω to 150 k Ω24Ω to 221 k Ω100 Ω to 301k Ω± 0.01 %200 Ω to 150 k Ω24 Ω to 221 k Ω-± 02 ppm/K (3)± 0.25 %100 Ω to 100 k Ω100 Ω to 150 k Ω-± 0.1 %100 Ω to 100 k Ω100 Ω to 150 k Ω-± 0.05 %150 Ω to 100 k Ω150 Ω to 150 k Ω-± 0.01 %200 Ω to 100 k Ω200 Ω to 150 k Ω- For technical questions, contact: ff3cresistors@Document Number: 28726UXA 0204, UXB 0207, UXE 0414Vishay BeyschlagHigh Precision Leaded ResistorsFUNCTIONAL DESCRIPTIONDerating - Precision OperationTemperature RiseDocument Number: 28726For technical questions, contact: ff3cresistors@UXA 0204, UXB 0207, UXE 0414High Precision Leaded ResistorsVishay BeyschlagTESTS AND REQUIREMENTSE ssentially all tests are carried out in accordance with the following specifications:E N 140000/IE C 60115-1, Generic specification (includes tests)E N 140100/IE C 60115-2, Sectional specification (includes schedule for qualification approval)CECC 40101-806, Detail specification (includes schedule for conformance inspection)Most of the components are approved in accordance with the uropean CE CC-system, where applicable. The Test Procedures and Requirements table contains only the most important tests. For the full test schedule refer to the documents listed above. The testing also covers most of the requirements specified by EIA/IS-703 and JIS-C-5202.The tests are carried out in accordance with IEC 60 068 and under standard atmospheric conditions in accordance withIE C 60068-1, 5.3. Climatic category LCT/UCT/56 (rated temperature range: Lower Category Temperature, Upper Category Temperature; damp heat, long term, 56 days) is valid.Unless otherwise specified the following values apply:Temperature: 15 °C to 35 °C Relative humidity: 45 % to 75 %Air pressure: 86 kPa to 106 kPa (860 mbar to 1060 mbar).For testing the components are mounted on a test board in accordance with IE C 60115-1, 4.31 unless otherwise specified.In the Test Procedures and Requirements table only the tests and requirements are listed with reference to the relevant clauses of IEC 60115-1 and IEC 60068-2; a short description of the test procedure is also given.TEST PROCEDURES AND REQUIREMENTSIEC 60115-1CLAUSEIEC 60068-2TEST METHODTESTPROCEDUREREQUIREMENTSPERMISSIBLE CHANGE (ΔR )Stability for product types:UXA 0204100 Ω to 100 k Ω22Ω to < 100Ω;> 100 k Ω to 221 k Ω -UXB 0207100 Ω to 250 k Ω40.2Ω to < 100 Ω;> 250k Ω to 301 k Ω10Ω to < 40.2 Ω;> 301 k Ω to 1 M ΩUXE 0414100 Ω to 100 k Ω22Ω to < 100 Ω;> 100k Ω to 511 k Ω-4.5-resistance (ΔR /R )± 0.25 %; ± 0.1 %; ± 0.05 %; ± 0.01 %4.8.4.2-temperature coefficientat 20/LCT/20 °C and 20/UCT/20 °C± 10 ppm/K; ± 05 ppm/K; ± 02 ppm/K4.25.1-enduranceroom temperature;U = orU = U max ;1.5 h on; 0.5 h off 70°C; 2000 h ± (0.05 %R +0.01Ω)± (0.05 %R +0.01Ω)± (0.05 %R +0.01Ω)85°C; 1000 h ± (0.02 %R +0.01Ω)± (0.03 %R +0.01Ω)±(0.04 %R +0.01Ω)85°C; 8000 h± (0.04 %R +0.01Ω)± (0.06 %R +0.01Ω)± (0.08 %R +0.01Ω)P 70 x R For technical questions, contact: ff3cresistors@Document Number: 28726UXA 0204, UXB 0207, UXE 0414Vishay BeyschlagHigh Precision Leaded Resistors4.25.3-endurance atupper category temperature 125°C; 1000 h ± (0.04 % R +0.01Ω)± (0.06 %R +0.01Ω)± (0.08 %R +0.01Ω)4.24 3 (Ca)damp heat,steady state (40± 2)°C; 56days; (93 ± 3) %RH± (0.04 %R +0.01Ω)± (0.05 %R +0.01Ω)± (0.06 %R +0.01Ω)4.23climatic sequence:4.23.22 (Ba)dry heat 125°C; 16h 4.23.330 (Db)damp heat, cyclic55°C; 24h;90% to 100%RH;1 cycle4.23.4 1 (Aa)cold - 55 °C; 2h 4.23.513 (M)low air pressure 8.5kPa;2h;15 °C to 35°C 4.23.630 (Db)damp heat, cyclic55°C; 5days;95% to 100%RH;5 cycles ± (0.04 %R +0.01 Ω)no visible damage± (0.05 %R +0.01Ω)no visible damage± (0.06 %R +0.01Ω)no visible damage4.13-short time overload room temperature;U = 2.5 x or U = 2x U max ; 5 s ± (0.01 %R +0.01Ω)no visible damage ± (0.01 %R +0.01Ω)no visible damage ± (0.02 %R +0.01Ω)no visible damage4.1914 (Na)rapid change of temperature 30minutes at LCT and 30minutes at UCT;5cycles ± (0.01 %R +0.01Ω)no visible damage ± (0.01 %R +0.01Ω)no visible damage ± (0.02 % R +0.01Ω)no visible damage4.2945 (XA)component solvent resistanceisopropyl alcohol + 23 °C; toothbrushmethod marking legible;no visible damage4.18.220 (Tb)resistance to soldering heat unmounted components; (260± 5)°C; (10± 1)s ± (0.01 % R +0.01Ω)no visible damage ± (0.01 %R +0.01Ω)no visible damage ± (0.02 %R +0.01Ω)no visible damage4.1720 (T a)solderability + 235°C; 2 s solderbath methodgood tinning (Š 95 % coverage, no visible damage)TEST PROCEDURES AND REQUIREMENTSIEC 60115-1CLAUSEIEC 60068-2TEST METHODTESTPROCEDUREREQUIREMENTSPERMISSIBLE CHANGE (ΔR )Stability for producttypes:UXA 0204100 Ω to 100 k Ω22Ω to < 100Ω;> 100 k Ω to 221 k Ω -UXB 0207100 Ω to 250 k Ω40.2Ω to < 100 Ω;> 250k Ω to 301 k Ω10Ω to < 40.2 Ω;> 301 k Ω to 1 M ΩUXE 0414100 Ω to 100 k Ω22Ω to < 100 Ω;> 100k Ω to 511 k Ω-P 70 x RDocument Number: 28726For technical questions, contact: ff3cresistors@UXA 0204, UXB 0207, UXE 0414High Precision Leaded ResistorsVishay Beyschlag4.226 (B4)vibration6 h; 10 Hz to 2000 Hz 1.5 mm or 196 m/s 2± (0.01 %R +0.01Ω)± (0.01 %R +0.01Ω)± (0.02 %R +0.01Ω)4.1621 (Ua 1)21 (Ub)21 (Uc)robustness ofterminations tensile, bending andtorsion ± (0.01 %R +0.01Ω)± (0.01 %R +0.01Ω)±(0.02%R +0.01Ω)4.7-voltage proofU RMS = 100 V; 60 sno flashover or breakdownTEST PROCEDURES AND REQUIREMENTSIEC 60115-1CLAUSEIEC 60068-2TEST METHODTESTPROCEDUREREQUIREMENTSPERMISSIBLE CHANGE (ΔR )Stability for product types:UXA 0204100 Ω to 100 k Ω22Ω to < 100Ω;> 100 k Ω to 221 k Ω -UXB 0207100 Ω to 250 k Ω40.2Ω to < 100 Ω;> 250k Ω to 301 k Ω10Ω to < 40.2 Ω;> 301 k Ω to 1 M ΩUXE 0414100 Ω to 100 k Ω22Ω to < 100 Ω;> 100k Ω to 511 k Ω-Legal Disclaimer NoticeVishay Document Number: NoticeSpecifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.。

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一、总体介绍
1.简单说明
是一颗车载充电器芯片，采用SOT23-6封装，输入范围10V～40V
（典型为12V、24V），输出为5V，最大输出电流为3A/2A（具体值由检流电阻
Rsen决定）。在负载很重时（Iload需求>2A/1A），实现恒流功能（CC），Iload实
际=2A/1A，设计精度8%；在负载较轻时（Iload<2A/1A），实现恒压功能（CV），
Vo=5V，设计精度3%。
并带有OTP、OVP、OCP、短路保护、cable补偿，提供轻载工作模式。

2.应用电路

CX918

CX918
深圳市诚芯微科技有限公司ＣＸ９１８

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二、
测试数据

1. 12V/24V转5V（恒流1A）工作的I/V 曲线

恒压恒流工作的V/I曲线

0
1
2
3
4
5
6

010020030040050060070080090010001100120
0

Iout（mA）

V
o
u
t
（
V
）
VIN=12V
VIN=24V
VOUT=4.9
VOUT=5.1

负载在1A以内时，芯片工作在恒压模式下，输出稳定在4.85～5.15V，负载超
过1A，输出降低，负载电流恒定供给1A，直到输出拉低到1.5V左右，芯片关断
（短路保护）不工作。

2. 线性调整率和负载调整率：
线性调整率

4.91
4.93
4.95
4.97
4.99
5.01
5.03

101214161820222426283032343638
输入电压（V）

输
出
电
压
（
V
）
Iout=0
lout=1A

CX918

CX918
深圳市诚芯微科技有限公司ＣＸ９１８

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负载调整率

4.93
4.94
4.95
4.96
4.97
4.98
4.99
5
5.01

00.20.40.60.811.2
负载电流（A）

输
出
电
压
（
V
）
VIN=12V
VIN=24V

3. 12V转5V（恒流1A）测试数据及效率图
Vin(V) Iin(A) Vout(V) Iout(A) 效率
11.89 0.25 2 1.025 68.97%
11.88 0.294 2.5 1.027 73.51%
11.84 0.345 3 1.028 75.50%
11.9 0.38 3.5 1.031 79.80%
11.87 0.425 4 1.033 81.91%
11.89 0.47 4.5 1.037 83.50%

恒流工作效率

60.00%
65.00%
70.00%
75.00%
80.00%
85.00%

1.522.533.544.55
输出电压(V)

效
率
VIN=12V IOUT=1A

CX918
深圳市诚芯微科技有限公司ＣＸ９１８

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Vin(V) Iin(A) Vout(V) Iout(A) 效率
12.02 0.047 5 0.1 88.50%
11.98 0.116 4.98 0.25 89.59%
11.87 0.188 4.98 0.4 89.26%
11.82 0.237 4.97 0.5 88.71%
11.89 0.284 4.96 0.6 88.13%
11.83 0.36 4.96 0.75 87.35%
11.87 0.383 4.95 0.8 87.11%
11.91 0.485 4.94 1 85.52%

恒压工作效率

70.00%
75.00%
80.00%
85.00%
90.00%
95.00%

00.20.40.60.81
负载电流（A）

效
率
VIN=12V

4. 24V转5V（恒流1A）测试数据及效率图
Vin(V) Iin(A) Vout(V) Iout(A) 效率
24.01 0.136 2 1.03 63.09%
24.01 0.158 2.5 1.033 68.08%
24.02 0.18 3 1.035 71.82%
24.02 0.202 3.5 1.037 74.80%
24.01 0.224 4 1.04 77.35%
24.01 0.247 4.5 1.045 79.29%

CX918

深圳市诚芯微科技有限公司ＣＸ９１８

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恒流工作效率

60.00%
65.00%
70.00%
75.00%
80.00%
85.00%

1.522.533.544.55
输出电压(V)

效
率
VIN=24V IOUT=1A

Vin(V) Iin(A) Vout(V) Iout(A) 效率
24.03 0.025 5 0.1 83.23%
23.97 0.061 4.99 0.25 85.32%
23.95 0.098 4.98 0.4 84.87%
23.96 0.123 4.98 0.5 84.49%
23.91 0.149 4.97 0.6 83.70%
23.9 0.188 4.96 0.75 82.79%
23.94 0.201 4.96 0.8 82.46%
23.9 0.254 4.95 1 81.54%

恒压工作效率

70.00%
75.00%
80.00%
85.00%
90.00%
95.00%

00.20.40.60.81
负载电流（A）

效
率
VIN=24V

深圳市诚芯微科技有限公司ＣＸ９１８

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三、 PCB板布局建议：
1. 流大电流的线要粗，短，不拐弯。
2. 功率器件组成的环路面积要求小。
3. 输入电解电容紧挨第1脚（VIN）和2脚（GND），主要是减少输入电源布
线寄生的电感，电阻产生的高压开关毛刺干扰。
4. SW端走线要粗，短，不拐弯。电感和续流二极管要紧挨SW端。

L
o
a
d
图：
CX918

CX918

CX918 PCB
深圳市诚芯微科技有限公司ＣＸ９１８

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器件备注品牌单价币种含税
贴片集成块
SOT23-6
ME2307 MOS SOT23-3 ME 0.033 USD 0%
100uH 电感功率电感100uH 1.4A伟峰达、风华0.55 RMB 0%
68uF 35V 电解电容_68uF/35V 凯特、艾华 0.0453 RMB 0%
68uF 35V 电解电容_68uF/35V 凯特、艾华 0.0453 RMB 0%
560uF 16V 凯特、艾华 0.1 RMB 17%
68uH 伟峰达、风华0.16 RMB 17%
SB340 二极管_SB340 3A 40V BYD、ST 0.21368 RMB 0%

50毫欧电阻 1 % 风华 0.05 RMB 0%
1uF瓷片电容 0805 TDK 0.03 RMB 0%
保险丝 250V/2A RMB 0%
器件总数：8

与TL494对比分析
保护及滤波电路 6
发光二极管 1
Schottky 1
相同部分

Total 8
NPN三极管 2S9014
PNP三极管 2MJD45H11G、S9012
Zenner 1IN5258B
普通二极管 2IN4148 0.1
普通电阻 19 0.1
检流电阻 1100mΩ 0.5W 2%
30.1uF 50V 0.1
电容 1220uF 10V
10.001uF 50V 0.03
120pF 0.03
电感 1150uH 1.25A
IC 1TL494IN

TL494

器件总数 35 494方案成本偏高 0.36

CX918CX918CXW
CX918BOM
深圳市诚芯微科技有限公司ＣＸ９１８

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