12位二进制移位计数器74HC4040

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
6
Philips Semiconductors
12-stage binary ripple counter
AC WAVEFORMS
Product specification
Product specification
74HC/HCT4040
FEATURES
• Output capability: standard • ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with “4040” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT4040 12-stage binary ripple counter
Product specification File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
12-stage binary ripple counter
Output capability: standard ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
50 8 10 3 92
fmax
maximum clock pulse 6.0 27
frequency
30 82
35 98
150
190
30
38
26
33
100
125
20
25
17
21
185
230
37
46
31
39
75
95
15
19
13
16
100 20 17
100 20 17
65 13 11
4.8 24 28
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
12-stage binary ripple counter
Fig.4 Functional diagram.
tPHL/ tPLH propagation delay CP to Q0
19 40
50
tPHL/ tPLH propagation delay Qn to Qn+1
10 20
25
tPHL
propagation delay
MR to Qn
23 45
56
tTHL/ tTLH output transition time
22
18
tTHL/ tTLH output transition time
19
7
6
tW
clock pulse width
80 14
HIGH or LOW
16 5
14 4
tW
master reset pulse 80 22
width; HIGH
16 8
14 6
trem
removal time
MR to CP
December 1990
5
Philips Semiconductors
12-stage binary ripple counter
Product specification
74HC/HCT4040
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
PIN DESCRIPTION
PIN NO. 8 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 10 11 16
SYMBOL GND Q0 to Q11 CP MR VCC
Product specification
74HC/HCT4040
NAME AND FUNCTION ground (0 V) parallel outputs clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) positive supply voltage
APPLICATIONS • Frequency dividing circuits • Time delay circuits • Control counters
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
20
24
tW
master reset pulse
16 6
width; HIGH
20
24
trem
removal time
MR to CP
10 2
13
15
fmax
maximum clock pulse 30 72
24
20
frequency
ns 4.5 Fig.7 ns 4.5 Fig.7 ns 4.5 Fig.7 MHz 4.5 Fig.7
INPUT UNIT LOAD COEFFICIENT
CP
0.85
MR
1.10
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL PARAMETER
74HCT
+25
−40 to +85
min. typ. max. min. max.
225 45 38
150 30 26
280 56 48
110 22 19
120 24 20
120 24 20
75 15 13
4.0 20 24
ns ns ns ns ns ns ns MHz
TEST CONDITIONS
VCC WAVEFORMS (V)
2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.7 4.5 6.0
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
47
CP to Q0
17
Hale Waihona Puke 14tPHL/ tPLH propagation delay
28
Qn to Qn+1
10
8
tPHL
propagation delay
61
MR to Qn
Fig.5 Logic diagram.
Product specification
74HC/HCT4040
FUNCTION TABLE
INPUTS
CP
MR
↑
L
↓
L
X
H
OUTPUTS
Qn no change
count L
Notes
1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW clock transition
UNIT
ns ns MHz pF pF
ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
12-stage binary ripple counter
7 15
19
TEST CONDITIONS
−40 to +125
UNIT